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> Is this for research, or a product. If product, is cost a concern? > Is your heart set on using an FPGA, or would you consider cheaper > alternatives even if it means you don't get to play with those neat > FPGAs? This should be a product; thus cost makes sense. > Is this for a VoIP system? If so, 512 samples at 8kHz will add 64 mS > of latency. I.e., lag would make conversation quality suffer. This is not a problem for a recording system. > You could probably use 8 dual ported FIFOs and the AXIS reads from > these FIFOs could be decoded. E.g., base+0 for ch 0, base+1 for ch 1, > etc. I was asked for expediency of doing this looking for an efficient way of reading streams from perephriental. Thanks for approving.Article: 66876
if you intend to implement the filter in an FPGA, it will be a pain to have
so many derived clocks.
if you do partial reconfiguration, the probability of P&R trouble can be
very high...
just my 2c...
Kelvin
"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0402280111.14a14564@posting.google.com...
> "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
> > Working on a polyphase decimator and interpolator. I'm trying to use
the
> > same chunk-o-logic to implement both functions. In either case, it is
> > easiest to drive the control logic from the fastest of the two clocks.
I'm
> > trying to figure out the most elegant way to achieve this. Any
thoughts,
> > ideas, links?
> >
> > Thanks,
>
> If you can work this out, it would be the easiest:
>
> Say you have a set of frequencies you want to handle:
>
> {f1, f2, f3, f4...fn}
>
> Clock your control logic at a frequency that can generate all of these
> other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
> control clock to be 30 whateverHz. To clock data in or out of the
> decimator/interpolators, use clock enables that are synchronous to the
> data and the control clock but have a duration of 1 control clock.
>
> Slightly off topic, but if you're doing this fixed point, you might
> have to adjust gains depending on input and output rate for consistent
> scaling.
Article: 66877hey, for now i just use AREA_GROUP "AreaGroupName" RANGE = SLICE_X0Y79:SLICE_X27Y54 ; INST "/" AREA_GROUP = " AreaGroupName " ; as area constraint but i can't really find how you can place your individual components? let's say you have a root component A which is composed by components B and C how can you say that you want B in the range X0Y0:X10Y10 C in the range X11Y0:X20Y10 and if possible A in the range X0Y0:X30Y30 i thought it should be something like INST "/B" ... or INST "/A/B"... but it all gives an error ... btw i'm using xst (ise6.1) ... thanx in advance for you comments, kind regards, YArticle: 66878
Active contour model is used widly in machine vision and most of them are implemented on PC. Does anyone knows any documents or reference papers which describe the method of how to implement the active contour model(snake) on FPGA?Article: 66879
"khoa nguyen" <jeffn@ihug.com.au> wrote in message news:<c1p5k1$5sm$1@lust.ihug.co.nz>... > I'd like to support the ARM and IA32 ISA on an FPGA. At the moment Im unsure > if I can do this. So what I thought is that if only I have some small clean > test bench of both ISA's, then I could start supporting those small set of > instructions. Later on I would add in the rest. > > Im wondering if there's anyone that happens to have some small clean test > benchs or even applications, then could you forward them to me. > > thanks heaps. About the time when Pentium 100 was introduced, there were a number of authers that wrote books on optimising x86 code to run as fast as possible. I have a few of these but in the office so I can't recall names v books. The jist of one of these " ... Inner Loops ..." was that if you limited yourself to certain ops, you could get x86 to perform very well indeed ie 1 or 2 ops per cycle if paired right. He breaks the instruction set down into many groups, the fastest, the oks, the maybes, the never use ect, & the whatever. If you build a risc to execute those 1st 2-3 groups you would have a risc that doesn't execute most x86 code since most compilers probably generate some of the lesser codes from time to time. Also the risc would suffer the same horrible design decisions that Intel made almost 30yrs ago. IE var length byte encodings. Now as any AMD/Intel person would say, even though its horrible, those wierd var length ops are understood, its possible to do in VLSI with transister muxes very well so it becomes a minor headache. But FPGAs are expensive to use muxes to the extent x86 needs them. The alternative is to use time based state machine to peel the ops apart but that would be very slow. I would suggest staying away from x86 ISA as being the most complex underpowered ISA around. I would suggest staying away from Arm as their lawyers are aggresive, but it is a much easier target. regards johnjakson_usa_comArticle: 66880
Are you trying to use Windows NT? Xilinx no longer supports NT and this causes both Impact and Core Generator to crash on my system. Mahim Mishra wrote: > I am trying to configure a toy application with a small FPGA component > and a small PoewerPC component on a Xilinx xc2vp20 FPGA mounted on an > AFX development board. I am using Xilinx EDK 6.1.2 and Xilinx ISE > 6.1.03i. I am able to generate run all the compilation steps, but when > I try to configure the FPGA using the generated .bit, .bmm and .elf > files, Impact crashes with the error message > > "FATAL_ERROR:GuiUtilities:WinApp.c:657: $Revision - ...." > > The Xlinx Answers Database is not being very useful. Does anyone have > any idea what I may be doing wrong? > > Thanks, > MahimArticle: 66881
On Fri, 20 Feb 2004 00:12:00 GMT, Martin Euredjian wrote: >> When I reply to a top-posted message with a sig -- like yours -- >> everything below the sig is gone, as here. The _)(*&^%$#@!! news program >> snips it all silently. > >Really? That's amazing. Why would they do that? Because it's implicit in the Usenet standards. The signature seperator is defined as a line consisting of: <hyphen><hyphen><space><eol> One of the relevant standards (possibly RFC850, but I can't remember for sure) states that the sig should always be stripped in replies, and the better newspeaders do it automatically. Usenet standards always assume bottom-posting, so this behaviour is convenient. >Maybe you need to try a different reader. I'm using Outlook Express and >directly off the Web when travelling with a browser. Outlook Express breaks all sorts of standards, and can't be regarded as a real news reader in consequence (it's barely adequate even as a mail client). As an example, OE strips all trailing spaces on lines, so it cannot generate a standard-compliant sig seperator. It also does quoting incorrectly, by adding a space following the quote character, and by wrapping quoted lines at the same length as new text (it will also wrap continuous strings - hence the fragmented URLs in OE posts). I can't even begin to illustrate all of OE's misbehaviour, but this paragraph demonstrates one of it's more fatuous foibles - OE users can't even read it, since it's assumed to be a script attachment! -- MaxArticle: 66882
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0402240800.32041d0d@posting.google.com... > > I have a board that has a XCF02S and Spartan 3 400 (ES) connected in a > > JTAG chain (the XCF02S is first in the chain). Attempting to > > initialise the chain in Impact fails because the IDCODE coming out of > > the FPGA is invalid (I have verified this on a scope - It is > > reproducibly incorrect, and always the same value). Looking at the TDO > > pin of the XCF02S / TDI pin of the FPGA, I can see that the IDCODE > > coming out of the XCF02S is correct. > > > > If I take the XCF02S out of the chain, then the IDCODE from the FPGA > > is correct and Impact is able to program the device. > > > > Should the value on the TDI pin of the FPGA effect the output of the > > IDCODE? Sure, all commands are shifted serially through the chain, so a problem upstream will cause malfunctions downstream. > I just tried reversing the order of the JTAG chain (FPGA first, then > PROM) and it now works. After numerious experiments, it seems that if > there is any activity on the FPGA's TDI pin, then the IDCODE wont be > output successfully. > We've seen different problems with an XCF02S in the chain ahead of a Spartan 2 part. Done never goes high on the Spartan when attempting JTAG programming. Take the XCF02 out of the chain and it works. Discovered that if the XCF02 is blank, then we can program the Spartan OK. Xilinx has some answer records (18644 and others) on related issues, but that didn't seem to apply to us.Article: 66883
There is a netlist synthesied, say, for an ASIC technology. The netlist should be prototyped on FPGA. Therefore, it should be implemented by FPGA vendor's tools. Implementation should be done automatically for any netlist given in EDIF format. Functionality of primitives is known. One of the solutions is to create a VHDL netlist and resynthesize. It would be possible to bypass VHDL export and synthesis by building (on-the-fly) a macro-library of the ASIC primitives out of vendor's primitives, specifically out of Xilinx's UniSim primitives. Please, give the idea, what are the macro-libs and how can they be created? Thanks.Article: 66884
On Tue, 24 Feb 2004 13:30:28 GMT, Randy Yates wrote: >Perhaps the problem isn't top- or bottom-posting per se, but that the >quoting method used is inconsistent. If folks are careful to ensure >the "Tom says:" lines are properly maintained and use the same quote >character and indentation style, either posting style is fairly easily- >parsed, in my opinion. While your point is entirely sensible, it just doesn't work, since the most common "news client" in use is probably Outlook Express (Outlook proper can't do NNTP at all), and it simply ignores many Usenet standards. OE users are prevented from quoting correctly, or even generating a standard sig separator. Personally, I'm not too fussed about top-posting per se. What does irritate is the lazy poster who can't be bothered to edit the quoted text at all, so you end up with reams of irrelevant chat going back to the original post. I'm just as likely to ignore such a post irrespective of whether the new text is at the top or the bottom. -- MaxArticle: 66885
Max wrote: > I can't even > begin to illustrate all of OE's misbehaviour, but this paragraph > demonstrates one of it's more fatuous foibles - OE users can't even > read it, since it's assumed to be a script attachment! I don't want to continue an OT conversation posted to so many groups, but can you explain what that means? Why does OE assume the above paragraph is a script attachment? I don't see anything special about it. Hmmm... is it the word begin at the start of a line with two spaces after it? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66886
"valentin tihomirov" wrote: > There is a netlist synthesized, say, for an ASIC technology. The netlist > should be prototyped on FPGA. Therefore, it should be implemented by FPGA > vendor's tools. Implementation should be done automatically for any netlist > given in EDIF format. Consider getting vhdl source code and running synthesis for each target. > It would be possible > to bypass VHDL export and synthesis by building (on-the-fly) a macro-library > of the ASIC primitives out of vendor's primitives, specifically out of > Xilinx's UniSim primitives. Possible, but it might be more efficient in time and gates to write synth code from scratch. -- Mike TreselerArticle: 66887
"Avinash Sharma" wrote: > is it true that one-hot encoding for FSM's is used in FPGA's? If so, > why? is it due to the large amount of registers available i.e: enough > registers to store all states? what kind of encoding is using in ASIC's? Try it both ways and see for yourself. Be sure to cover all the state cases. see thread: http://groups.google.com/groups?q=vhdl+one+hot+fsm+stuck+nic -- Mike TreselerArticle: 66888
Hi, to everyone who thought about doing calculations with netlists . eg. external pins, internal states are known (from reset state) to figure out the remaining signals, lets say 100% visibility. Does anybody thought about that? kind regards, thomasArticle: 66889
"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:c1qck8$1ld1dc$1@ID-212430.news.uni-berlin.de... > There is a netlist synthesied, say, for an ASIC technology. The netlist > should be prototyped on FPGA. Therefore, it should be implemented by FPGA > vendor's tools. Implementation should be done automatically for any netlist > given in EDIF format. Functionality of primitives is known. One of the > solutions is to create a VHDL netlist and resynthesize. It would be possible > to bypass VHDL export and synthesis by building (on-the-fly) a macro-library > of the ASIC primitives out of vendor's primitives, specifically out of > Xilinx's UniSim primitives. Please, give the idea, what are the macro-libs > and how can they be created? Thanks. > I think it would be possible to make, say, a Perl script that would convert ASIC primitives into FPGA primitives. I don't know if it would be very efficient, though. The ASIC primitives will be things like AND gates, whereas the FPGA primitives are LUTs that can absorb several gates. A very simple scripts would map a single gate to a single LUT and not be efficient, so the best bet is to resynthesize the source if you can. I suppose if you could do that, you wouldn't be asking the question though. -KevinArticle: 66890
hi, I've bought an evaluation board with a Spartan II on it and made a JTAG cable with the schematic : http://www.embeddedtronics.com/public/Electronics/xiprog/schematics/xiprog_s chematic.pdf I'm using ISE webpack 6.1 My cable is detected : Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. LPT base address = 0378h. Cable connection established. CB_PROGRESS_END - End Operation. Elapsed time = 1 sec. The pbl is when I try to retreive the boundary scan chain, Impact find a bunch of 28 non xilinx devices. In fact there is only the xc2s100 on the board.... When i've search on the web for a solution i've found that it may be possible to change the LPT clock speed by adding an environment variable but the speed is always set to 200kHz... Thanks for your answers Damien (excuse me for my english)Article: 66891
Clock enables are your friend. The processing of the samples does not have to
be spaced equally in time. All that matters is that the samples are spaced
equally when converting to/from analog. For example, if the sampling is at
15/16 of the filter's clock, you can disable the filter for one clock in 16.
It makes the filtering much easier with multiple sample rates if the whole
filter ban is running off a single clock. With bit serial filters, you get
even more flexibility.
"Kelvin @ SG" wrote:
> if you intend to implement the filter in an FPGA, it will be a pain to have
> so many derived clocks.
> if you do partial reconfiguration, the probability of P&R trouble can be
> very high...
>
> just my 2c...
>
> Kelvin
>
> "William Wallace" <msm30@yahoo.com> wrote in message
> news:7e4865b7.0402280111.14a14564@posting.google.com...
> > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
> news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
> > > Working on a polyphase decimator and interpolator. I'm trying to use
> the
> > > same chunk-o-logic to implement both functions. In either case, it is
> > > easiest to drive the control logic from the fastest of the two clocks.
> I'm
> > > trying to figure out the most elegant way to achieve this. Any
> thoughts,
> > > ideas, links?
> > >
> > > Thanks,
> >
> > If you can work this out, it would be the easiest:
> >
> > Say you have a set of frequencies you want to handle:
> >
> > {f1, f2, f3, f4...fn}
> >
> > Clock your control logic at a frequency that can generate all of these
> > other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
> > control clock to be 30 whateverHz. To clock data in or out of the
> > decimator/interpolators, use clock enables that are synchronous to the
> > data and the control clock but have a duration of 1 control clock.
> >
> > Slightly off topic, but if you're doing this fixed point, you might
> > have to adjust gains depending on input and output rate for consistent
> > scaling.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66892Marc Guardiani <marc@guardiani.com> wrote in message news:<HK10c.6931$TF2.3072@nwrdny02.gnilink.net>... > Are you trying to use Windows NT? Should have mentioned this. I am using Windows XP. > > Mahim Mishra wrote: > > I am trying to configure a toy application with a small FPGA component > > and a small PoewerPC component on a Xilinx xc2vp20 FPGA mounted on an > > AFX development board. I am using Xilinx EDK 6.1.2 and Xilinx ISE > > 6.1.03i. I am able to generate run all the compilation steps, but when > > I try to configure the FPGA using the generated .bit, .bmm and .elf > > files, Impact crashes with the error message > > > > "FATAL_ERROR:GuiUtilities:WinApp.c:657: $Revision - ...." > > > > The Xlinx Answers Database is not being very useful. Does anyone have > > any idea what I may be doing wrong? > > > > Thanks, > > MahimArticle: 66893
I have a Virtex xc2vp20 FPGA mounted on a Xilinx HW-AFX-FF1152 board. The FPGA is in a JTAG chain with two ROM modules, although I am not using the ROM modules right now. I am trying to learn how to use the embedded PowerPC module on the FPGA, and for this purpose, trying to implement the example design that Xilinx gives with their EDK tutorial. After I carry out all the implementation steps (with some small modifications to account for my board) and generate a bitstream, I am not able to download it onto the FPGA using iMPACT. iMPACT reports "Programming stopped: Done did not go high". The "DONE" LED on the board does light up, however, but the application does nothing (of course, I have no way of knowing if the application is correctly implemented at this stage). Also, the board's "Program" button becomes completely unresponsive after the failed configuration and I have to power-cycle the board to use it again. Here is the setup I have: 1. HW-AFX-FF1152 board, Virtex2Pro xc2vp20 FPGA 2. Xilinx ISE 6.1.03i 3. Xilinx EDK 6.1.2 4. Windows XP on the host machine 5. Configuration with JTAG using the Parallel Cable IV I have done all the sanity checks I could think of, and also looked through whatever the web had to offer but that has not fixed my problem. Does anyone have any ideas why I may be seeing this? Thanks, Mahim PS: I have been asking for a lot of help lately. I am more-or-less a complete newbie to hardware, and in a situation where I have to learn a lot really fast :(Article: 66894
On Sat, 28 Feb 2004 11:53:43 -0500, rickman wrote: >I don't want to continue an OT conversation posted to so many groups, Nor did I, really, since I don't like cross-posting either, but I don't know what groups the participants in this thread inhabit, so... >but can you explain what that means? Why does OE assume the above >paragraph is a script attachment? I don't see anything special about >it. Hmmm... is it the word >begin at the start of a line with two spaces after it? Yep - got it in one. OE will strip off the lines at the end of the post, and claim that they constitute an attachment named "to illustrate all of OE's misbehaviour, but this paragraph.dat" - ROTFLMAO! There's also a massive security hole there, though I don't think I'll go into detail. It's only one such flaw amongst a multitude, however. -- MaxArticle: 66895
On Sat, 28 Feb 2004 15:29:36 +0000 (UTC), Max wrote: >As an example, OE strips all trailing spaces on lines, >so it cannot generate a standard-compliant sig seperator. Apparently, that particular bug has been fixed in recent OE versions. ISTR OE v6 did resolve quite a few of the sillier deficiencies, but there's still enough left to make life interesting ;o) -- MaxArticle: 66896
I am surprised nobody really answered to the point! Software is when sequencing through the algorithm is done using INSTRUCTION power Hardware is when sequencing through the algorithm is done using LOGIC power...!!! "Thomas Stanka" <usenet_10@stanka-web.de> wrote in message news:ef424d2c.0402252351.44e57e4c@posting.google.com... > Hello OP, > > hope you got an better name in your next life. > > omnipresent@hotmail.com (OP) wrote: > > Feeling really intelligent today.. I would like to know some basic > > stuff.. > > > > What is the difference between a hardware implementation of an > > algorithm and a software one. > > HW & SW are uncomparable in general because SW w/o HW makes no sence. > > In some context you speak of HW or SW solution when you mean the > decission to use either > - a general purpose CPU (eg. micro controller) and write the > appropriate SW for this CPU > or > - build an ASIC (application specific IC, could of course be a fpga > too) that solves your problem. > > In general is an ASIC faster and fits better in your special needs for > reliability, power consumption and size, but tends to be more > expensive (unless huge quantities) and you have big trouble when you > find a better algorithm for your problem. > > You would think twice before using an ASIC for data compression on the > other hand it's impossible to do very high speed realtime data > processing (eg. 10GB Switch) with a CPU. > > bye ThomasArticle: 66897
He didn't say how many frequencies he was going to use, or what kind
of FPGA, or how many bits in the samples. But even if he had 20
different frequencies, you could do all in a single FPGA and use a
provisioned register to select the input and output chip enable rates,
as well as the frequency dedendant filter gains (if any).
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<c1ppdl$d3v$1@reader01.singnet.com.sg>...
> if you intend to implement the filter in an FPGA, it will be a pain to have
> so many derived clocks.
> if you do partial reconfiguration, the probability of P&R trouble can be
> very high...
>
> just my 2c...
>
> Kelvin
>
>
>
> "William Wallace" <msm30@yahoo.com> wrote in message
> news:7e4865b7.0402280111.14a14564@posting.google.com...
> > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
> news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
> > > Working on a polyphase decimator and interpolator. I'm trying to use
> the
> > > same chunk-o-logic to implement both functions. In either case, it is
> > > easiest to drive the control logic from the fastest of the two clocks.
> I'm
> > > trying to figure out the most elegant way to achieve this. Any
> thoughts,
> > > ideas, links?
> > >
> > > Thanks,
> >
> > If you can work this out, it would be the easiest:
> >
> > Say you have a set of frequencies you want to handle:
> >
> > {f1, f2, f3, f4...fn}
> >
> > Clock your control logic at a frequency that can generate all of these
> > other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
> > control clock to be 30 whateverHz. To clock data in or out of the
> > decimator/interpolators, use clock enables that are synchronous to the
> > data and the control clock but have a duration of 1 control clock.
> >
> > Slightly off topic, but if you're doing this fixed point, you might
> > have to adjust gains depending on input and output rate for consistent
> > scaling.
Article: 66898I forgot to mention - "Instruction Power" assumes that you have a processor executing the algorithm... "Shiraz Kaleel" <shirazkh@comcast.net> wrote in message news:pIqdna9k1f02EtzdRVn-uA@comcast.com... > I am surprised nobody really answered to the point! > > Software is when sequencing through the algorithm is done using INSTRUCTION > power > > Hardware is when sequencing through the algorithm is done using LOGIC > power...!!! > > > > "Thomas Stanka" <usenet_10@stanka-web.de> wrote in message > news:ef424d2c.0402252351.44e57e4c@posting.google.com... > > Hello OP, > > > > hope you got an better name in your next life. > > > > omnipresent@hotmail.com (OP) wrote: > > > Feeling really intelligent today.. I would like to know some basic > > > stuff.. > > > > > > What is the difference between a hardware implementation of an > > > algorithm and a software one. > > > > HW & SW are uncomparable in general because SW w/o HW makes no sence. > > > > In some context you speak of HW or SW solution when you mean the > > decission to use either > > - a general purpose CPU (eg. micro controller) and write the > > appropriate SW for this CPU > > or > > - build an ASIC (application specific IC, could of course be a fpga > > too) that solves your problem. > > > > In general is an ASIC faster and fits better in your special needs for > > reliability, power consumption and size, but tends to be more > > expensive (unless huge quantities) and you have big trouble when you > > find a better algorithm for your problem. > > > > You would think twice before using an ASIC for data compression on the > > other hand it's impossible to do very high speed realtime data > > processing (eg. 10GB Switch) with a CPU. > > > > bye Thomas > >Article: 66899
hi, Never mind the question, i found the problem : my cable from the dongle to the board was too long (about 1 metre) i've make it shorter and everything was fine. I post this solution to help if someone has the same pbl : > The pbl is when I try to retreive the boundary scan chain, Impact find a > bunch of 28 non xilinx devices. > In fact there is only the xc2s100 and a parallel prom on the board.... As I'm beginning with xilinx targets I may ask some other questions... be ready :) bye Damien
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