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Messages from 67025

Article: 67025
Subject: Re: Need to speed up Stratix compiles.
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 04 Mar 2004 01:37:14 -0000
Links: << >>  << T >>  << A >>
>This has been implemented in some ASIC tools already. Actually Xilinx
>has been doing some very simple parallel processing in ISE (on Solaris
>and now Linux) for a long time. Multiple iterations of "par" can run
>in parallel on multiple hosts, then you pick the best result. This is
>of course, extremely coarse grained compared to what I indicated
>above.

Last I checked, multiple PAR runs didn't gain much if you
had a well floor-planned system.  That was a long time ago.
Has anything changed?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 67026
Subject: Jitter in DLLs vs PLLs
From: "Michael Chan" <m.chan1@uq.edu.au>
Date: 4 Mar 2004 01:38:09 GMT
Links: << >>  << T >>  << A >>
Just wondering if anyone can point me to some articals or papers that analyse
the characteristics of xilinx DLLs vs altera PLLs.

Thanks.



Article: 67027
Subject: Re: Different Finite Field Multipliers!!!
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Thu, 04 Mar 2004 01:39:52 GMT
Links: << >>  << T >>  << A >>
I don't know if I understand the question exactly but finite field
multiplier implementations are shown in Lin & Costello and also Sweeney's
book, which is more introductory.
-Kevin

"OP" <omnipresent@hotmail.com> wrote in message
news:a0539759.0403031405.4f790e93@posting.google.com...
> Hello,
>
> I would like to the different Finite Field Multipliers used for doing
> Finite Field Multiplication? Also specifically ones that do in
> Polynomial Basis??
>
> and for FPGA Implementation too!!!!
>
> any help regards to references to these design of multipliers and if
> possible a reference to the comparison of different multipliers would
> greatly appreciated.
>
> Thanx. OP.



Article: 67028
Subject: Re: Need to speed up Stratix compiles.
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Thu, 04 Mar 2004 01:41:14 GMT
Links: << >>  << T >>  << A >>
Hi Rick,

> We can all speculate about the relative merits of processor
> enhancements, but these machines are very complex and the only real way
> to tell what helps is to try it.  Since we are not all ancient Greeks
> philosophizing in our armchairs, it would be a good idea to pick a
> design and to run it on a few different workstations, hopefully
> including an AMD64.

I agree.  That's why my original posting makes reference to some SPEC
results showing that 64-bit code on Athlon64 is ~5% slower than the same
programs compiled in 32-bit code.  One specific SPEC sub-component is a tool
called VPR, which is an academic place & route tool for FPGAs.  It shows a
8% slow-down.  While by no means comprehensive, I think this gives an idea
of how much speed to expect out of 64-bit vs. 32-bit code, at least for now.

I've forwarded your comments on how nice it would be to see some results for
different system configurations on to the relevant groups in Altera.  My
personal experience (going from PII to PIII to P4) has been that SPEC2000 is
a pretty good proxy for Quartus performance, especially for place & route
limited designs.

Regards,

Paul



Article: 67029
Subject: Re: Need to speed up Stratix compiles.
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Thu, 04 Mar 2004 01:55:50 GMT
Links: << >>  << T >>  << A >>
Hi Max,

> Is there any possibility of making Quartus multi-threaded? That
> strikes me as the most likely way to get a dramatic performance
> increase, though I know it's not always easy to achieve with heuristic
> apps.

It's hard to use fine-grained parallelism on place-and-route tools like
Quartus.  This doesn't mean that people (academia, industry) haven't tried
and aren't still trying, but I wouldn't hold my breath.  See my previous
posting on this topic:
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&q=Paul+Leventis+multi-threaded

Of course, coarse-grained parallelism (running multiple place-and-route runs
on multiple machines) is much easier.  Quartus II ships with a pretty cool
tool called Design Space Explorer.  This tool tries out a whole bunch of
Quartus settings and random seeds on your design in order to find the
settings that optimize performance.  This requires multiple runs of Quartus.
DSE is capable of farming these runs off to multiple CPUs/computers through
LSF or a built-in distributed computing engine.

To find out more about DSE and coarse-grained parallelism, please see the
section entitled "DSE Advanced Information" in
http://www.altera.com/literature/hb/qts/qts_qii52008.pdf

Regards,

Paul Leventis
Altera Corp.



Article: 67030
Subject: Re: Dongle compatibility
From: msm30@yahoo.com (William Wallace)
Date: 3 Mar 2004 18:02:56 -0800
Links: << >>  << T >>  << A >>
Did you verify that you had your port settings correct in the 
laptop's BIOS?


eastwood132@yahoo.com (Ted Lechman) wrote in message news:<b89924f9.0403021447.48ec865d@posting.google.com>...
> I've discovered incompatability between the ModelSim dongle and
> certain notebook computer's printer ports: They are
> 
> 1. Toshiba Satellite S150s (I would suspect all Satellites). I've
> experienced this personally. I had to returnthis notebook and get a
> CompaqPresario 2500 in its place to make sure the dongle works.
> 2. Sony notebooks ( my local distributor has had this problem).
> 
> The rumor is that its a voltage incompatabilty issue, but I'm not
> sure.
> 
> Ted Lechman
> Utica, NY

Article: 67031
Subject: Re: TRST Pin in Altera FPGAs
From: msm30@yahoo.com (William Wallace)
Date: 3 Mar 2004 18:03:40 -0800
Links: << >>  << T >>  << A >>
TRST is often used.  

erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c21e5p$jnd$1@sunnews.cern.ch>...
> The JTAG Standard defines a JTAG reset pin, TRST. This pin is little 
> used. All Altera docs (Datasheets, ANs) define this pin but write 
> nothing about its usage. Therefore we did not connect it at all. But we 
> experience problems in the JTAG chain: some EPC chips (especially big 
> ones, like EPC8) almost never finish the Verification phase. I am 
> wondering if this can be due to the unconnected TRST pins?
> 
> Janos Ero
> CERN Div. EP

Article: 67032
Subject: Xilinx Webpack 6.2 and Verilog `define ?
From: nospam <none@nowhere.net>
Date: Thu, 04 Mar 2004 03:54:50 GMT
Links: << >>  << T >>  << A >>
I've tried to define a macro-expansion in some Verilog-RTL ...

`define MAXIMUM2( x, y ) ( ((x)>(y)) ? (x) : (y) )

...

parameter IN_WIDTH = 24;
parameter OUT_WIDTH = 32;
parameter BUS_WIDTH = `MAXIMUM2( IN_WIDTH, OUT_WIDTH );

This compiles and evalutates correctly under Modelsim 5.6,
NC-Verilog 4.0, Design Compiler 2003.06-SP1, etc.

But Xilinx Webpack 6.2i spits out an error message saying
something like "`MAXIMUM2 not defined."

...

I'm guessing Xilinx's preprocessor doesn't do macros?
Will this be supported in the future?


Article: 67033
Subject: Re: XST ff merging - how do I "preserve" flip flops
From: Ray Andraka <ray@andraka.com>
Date: Wed, 03 Mar 2004 23:12:10 -0500
Links: << >>  << T >>  << A >>
Synplify used to do that too, and before that, syn_preserve didn't work
at all.  splitting the input to the flip-flops and putting syn_keeps on
them saves the day.  For some reason the tools have an easier go at it by
keeping signals rather than attempting to preserve registers.  Don't know
why.

Allan Herriman wrote:

> On Tue, 2 Mar 2004 13:34:26 +0800, "Peng Cong" <pc_dragon@sohu.com>
> wrote:
>
> >Why you need follow 2 attribute?
> >// synthesis attribute keep of e is "true"
> >// synthesis attribute keep of f is "true"
> >e and f are not flip-flop.
> >
> >Remove them should be OK
>
> Remove them and watch XST merge the two flip flops.  (I know; I tried
> it.)
>
> I suggest you read the XST documentation.
>
> Regards,
> Allan.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 67034
Subject: Anyone else using the USB JTAG board from Mesa Electronics
From: javaguy11111@yahoo.com (db)
Date: 3 Mar 2004 20:25:04 -0800
Links: << >>  << T >>  << A >>
I am trying to write a loopback test for my USB JTAG board I bought
from Mesa Electronics. I keep having problems with getting repeating
bytes coming back from the board when I read back. Sometimes I can
only go a few bytes without errors and sometimes I can go serveral
thousand bytes before I get an error.

My test bench in verilog seems to be okay and behaves as expected, but
things do not work correctly when I run from the board. I used some
usb sniffing software to verify that the dupes are coming from the
board and not from my driver software.

Ideally it would be nice to know if someone else has written similar
code and might even be able share it.

For the moment I totally stumped as to what the problem is. I will be
happy to post the code I have written so far if anyone is interested
in looking it over.

Article: 67035
Subject: Re: Need to speed up Stratix compiles.
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 03 Mar 2004 23:40:48 -0500
Links: << >>  << T >>  << A >>
"Paul Leventis (at home)" wrote:
> 
> I agree.  That's why my original posting makes reference to some SPEC
> results showing that 64-bit code on Athlon64 is ~5% slower than the same
> programs compiled in 32-bit code.  One specific SPEC sub-component is a tool
> called VPR, which is an academic place & route tool for FPGAs.  It shows a
> 8% slow-down.  While by no means comprehensive, I think this gives an idea
> of how much speed to expect out of 64-bit vs. 32-bit code, at least for now.
> 
> I've forwarded your comments on how nice it would be to see some results for
> different system configurations on to the relevant groups in Altera.  My
> personal experience (going from PII to PIII to P4) has been that SPEC2000 is
> a pretty good proxy for Quartus performance, especially for place & route
> limited designs.

That is very interesting information.  I was not aware of the AMD 64-bit
code was running slower than 32-bit code.  I am sure that you won't see
much of that on the AMD web site.  I may check in the PC building
newsgroups to see what results they are finding.  They seem to be a
bunch that get to the skinny of things like this.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 67036
Subject: Re: Xilinx Spartan 3 configuration
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 04 Mar 2004 01:04:33 -0500
Links: << >>  << T >>  << A >>
Chen Wei Tseng wrote:
> 
> Rick,
> 
> abort happens asynchronously (doesn't need to see CCLK rising edge for
> it to take place). And to avoid this, CS must be deasserted first.
> 
> The data pins will be asynchrounously driven by the FPGA with the
> WRITE_B changes to high, but the status words (cfgerr_b, dalign, rip,
> in_abort_b, 4'b1111) is clocked out to data pin [7:0] by CCLK
> 
> Regards, Wei

I just want to make sure I understand this correctly.  I belive what you
are saying is that the Spartan 3 data sheet is correct and xapp176 is
not correct and this section should be ignored, right?  

What did I miss?  Does xapp176 only apply to the Spartan II and the
Spartan 3 has changed?  I have gone back over xapp176 and it describes
in great detail how these controls work.  

"WRITE may be de-asserted and re-asserted as many times as necessary,
just as long as it is Low before the next rising CCLK edge." 

However, I must say I still have not figured out how to connect the FPGA
to a CPU data bus without a CPLD in between.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 67037
Subject: Re: XST ff merging - how do I "preserve" flip flops
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 04 Mar 2004 17:06:15 +1100
Links: << >>  << T >>  << A >>
On Thu, 04 Mar 2004 12:01:26 +1100, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

>On Tue, 2 Mar 2004 13:34:26 +0800, "Peng Cong" <pc_dragon@sohu.com>
>wrote:
>
>>Why you need follow 2 attribute?
>>// synthesis attribute keep of e is "true"
>>// synthesis attribute keep of f is "true"
>>e and f are not flip-flop.
>>
>>Remove them should be OK
>
>Remove them and watch XST merge the two flip flops.  (I know; I tried
>it.)
>
>I suggest you read the XST documentation.

To clarify, a preserve attribute on the output of the flip flops would
stop them from being merged.  XST does not support such an attribute,
hence the ugly workaround using keep attributes on the inputs of the
flip flops.

I need to use attributes to do a few things:
1.  Placement
2.  Preventing flip flops from being merged
3.  Preventing flip flops from being replicated
4.  Preventing buffers from being inserted into high-fanout logic

#1 isn't too bad, but the others are needlessly difficult in XST.

Regards,
Allan.

Article: 67038
Subject: EDK and LMB peripherals...
From: "Antonio Di Stefano" <NO.antoniodistefano@SPAM.infinito.it>
Date: Thu, 04 Mar 2004 06:26:50 GMT
Links: << >>  << T >>  << A >>
Hi all,
I wonder if (using the Xilinx EDK 6.1) is it possible to
create custom IP peripherals that employs the LMB bus
instead of the OPB. The LMB bus has many limitations, but it
is "cheaper" than OPB, and it would be useful to connect
simple peripherals to it.

T.I.A.
Antonio




Article: 67039
Subject: Re: EDK and LMB peripherals...
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 04 Mar 2004 16:54:52 +1000
Links: << >>  << T >>  << A >>
Antonio Di Stefano wrote:
> Hi all,
> I wonder if (using the Xilinx EDK 6.1) is it possible to
> create custom IP peripherals that employs the LMB bus
> instead of the OPB. The LMB bus has many limitations, but it
> is "cheaper" than OPB, and it would be useful to connect
> simple peripherals to it.

FSL (Fast Simplex Links) is even cheaper - and probably much better 
suited to what you might have in mind.

Regards,

John


Article: 67040
Subject: Module design:why design can't run in "virtex2"
From: skywave <chb@sst.bao.ac.cn>
Date: Wed, 3 Mar 2004 23:30:05 -0800
Links: << >>  << T >>  << A >>
I have some problems when I am running the modular design flow in Xilinx ISE 
5.1i. After entering the top-level design codes and synthesizing them 
successfully, I enter commands like this"ngdbuild -p xc2v3000-bf957-6 -uc 
alu.ucf -modular initial alu.ngc alu.ngd", and I get a failed message"can't run 
ngdbuild in modular design mode for 'virtex2' architecture".I don't know why. 

Article: 67041
Subject: Re: Need to speed up Stratix compiles.
From: Petter Gustad <newsmailcomp5@gustad.com>
Date: 04 Mar 2004 10:19:16 +0100
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) writes:

> Last I checked, multiple PAR runs didn't gain much if you
> had a well floor-planned system.  That was a long time ago.

True. If you don;t have a highly congested design with a high degree of
utilization you will probably not gain that much.

My point was that this was an example of a *very simple* parallelism
done by Xilinx. It would be more optimal (and much more difficult) to
make a parallel version of a single iteration of "par".

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 67042
Subject: Re: XST ff merging - how do I "preserve" flip flops
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 04 Mar 2004 21:31:18 +1100
Links: << >>  << T >>  << A >>
On Tue, 02 Mar 2004 05:08:06 +1100, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

[snip]

I didn't see Brian's post on my server, but google found it.

// synthesis attribute equivalent_register_removal of c is "no"
// synthesis attribute equivalent_register_removal of d is "no"


Silly me.  I was looking for constraints in the constraints guide, and
this one isn't listed there.

Thanks,
Allan.

Article: 67043
Subject: Re: XST ff merging - how do I "preserve" flip flops
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 04 Mar 2004 21:32:54 +1100
Links: << >>  << T >>  << A >>
On Thu, 04 Mar 2004 21:31:18 +1100, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

>On Tue, 02 Mar 2004 05:08:06 +1100, Allan Herriman
><allan.herriman.hates.spam@ctam.com.au.invalid> wrote:
>
>[snip]
>
>I didn't see Brian's post on my server, but google found it.
>
>// synthesis attribute equivalent_register_removal of c is "no"
>// synthesis attribute equivalent_register_removal of d is "no"
>
>
>Silly me.  I was looking for constraints in the constraints guide, and
>this one isn't listed there.

Hang on, it *is* there.  I don't understand how I missed it.

Oh well.

Allan.

Article: 67044
Subject: Re: XST ff merging - how do I "preserve" flip flops
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Thu, 4 Mar 2004 11:17:13 -0000
Links: << >>  << T >>  << A >>
If the attribute setting does not work, or you don't want to turn off global
removal of duplicates for the whole design, and you happen to have a spare
I/O. Make sure the I/O is in a known state say pulled-up. Ensure the pin is
defined as input or bi-directional. Use the input(bi) as a enable signal
into your register choosing the "enabled" state to be the one you use and is
always true. Don't do the same to copy register. They are now different and
the synthesiser wouldn't remove the duplicate. Very crude approach but
usually works.

You can do a similar thing by having one reg with a reset and one reg
without reset but you need to ensure that this does not cause you other
issues. There many variations you use I will leave to find the most
suitable.

John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:16s640hupdiocn3a94shc4oid0cdrdu4p8@4ax.com...
> Hi,
> I'm trying to code this structure in Verilog.  There are two flip
> flops (c and d) that are identical.  XST 6.1.3 wants to merge them
> together.  I want to stop it from doing that.
>
>                     e   .---.  c
>                   +-----|D Q|-----
>                   |   +-|>C |
>     a   .---. b   |   | |   |
>     ----|D Q|-----+   | '---'
>      +--|>C |     |   |
>      |  |   |     |   |
>      |  '---'     | f | .---.  d
>      |            +-----|D Q|-----
>  clk-+----------------+-|>C |
>                         |   |
>                         '---'
>
> created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
>
>
> I am giving the -equivalent_register_removal YES option to XST (it's
> needed elsewhere in the design) so I have to use attributes to stop
> XST from merging these particular ffs, since I don't wish to
> instantiate unisim components.
>
> When I use the keep attribute on all of c, d, e and f, XST still
> merges the ffs, and comes back with this warning:
>
> WARNING:Xst:638 - in unit foo Conflict on KEEP property on signal e
> and f f signal will be lost.
>
> [ Warning 638 isn't in the Xilinx documentation or the answers
> database. ]
>
> Here's the Verilog:
>
> module foo
> (
>     input  wire clk,
>     input  wire a,
>     output reg  c,
>     output reg  d
> );
>
> reg b;
>
> wire e = b;
> wire f = b;
>
> // synthesis attribute keep of c is "true"
> // synthesis attribute keep of d is "true"
> // synthesis attribute keep of e is "true"
> // synthesis attribute keep of f is "true"
>
> always @(posedge clk)
> begin
>     b <= a;
>     c <= e;
>     d <= f;
> end
>
> endmodule
>
>
> I have a working solution: add BUFs as follows:
>
> BUF buf_e (.I(b), .O(e));
> BUF buf_f (.I(b), .O(f));
>
> This produces the correct result after synthesis, but I wish to avoid
> using unisim components, because (1) they slow my simulation (even BUF
> contains a specify block!), (2) they aren't portable, and (3) I
> shouldn't have to.
>
>
> Questions:
> - What am I doing wrong?  ("Expecting too much from XST" is not an
> acceptable answer.)
> - How can I write the Verilog such that I get the correct result after
> synthesis without needing to instantiate unisim components?
>
> Hint to Xilinx: a "preserve" attribute would be really handy.  The
> other synthesis vendors have it.  Why doesn't XST?
>
> Thanks,
> Allan.



Article: 67045
Subject: mersenne twister
From: "Bevan Weiss" <kaizen__@NOSPAMhotmail.com>
Date: Fri, 5 Mar 2004 00:29:01 +1300
Links: << >>  << T >>  << A >>
I'm trying to find some information on how the mersenne twister pseudo
random number generator would be implemented in hardware.  So far the only
descriptions I can find for the algorithm relate to 32bit (or more) software
operations.

If anyone has any information on how I might go about such an implementation
or any links on where I might be able to get more information on how to
perform such an implementation it would be greatly appreciated.

Thanks,
Bevan Weiss



Article: 67046
Subject: Xilinx VirtexII Pro downloading with Platform Flash ?
From: dominique.deniau@sercel.fr (Deniau)
Date: 4 Mar 2004 04:38:55 -0800
Links: << >>  << T >>  << A >>
Hello,
Does anybody have downloaded a VirtexII Pro 2VP7 with a platform Flash
XCF08P  in Master SelectMap mode ?
Thanks.

Article: 67047
Subject: Re: Xilinx Webpack 6.2 and Verilog `define ?
From: dej@coup.inode.org (David Jones)
Date: Thu, 04 Mar 2004 12:54:06 GMT
Links: << >>  << T >>  << A >>
In article <eMx1c.19775$hK6.943@newssvr29.news.prodigy.com>,
nospam  <none@nowhere.net> wrote:
>
>`define MAXIMUM2( x, y ) ( ((x)>(y)) ? (x) : (y) )
>
>But Xilinx Webpack 6.2i spits out an error message saying
>something like "`MAXIMUM2 not defined."
>
>I'm guessing Xilinx's preprocessor doesn't do macros?
>Will this be supported in the future?

It's not so much a "don't do macros" issue - I think all Verilog
implementations must do basic macros to be useful, but many don't
do arguments.

Yes, arguments are standard as of 1995, but I have seen many tools
not support them.

Article: 67048
Subject: DMA PCI-X core
From: Matthias =?iso-8859-1?Q?M=FCller?= <spam*mur@iis.fhg.de>
Date: Thu, 04 Mar 2004 15:02:25 +0100
Links: << >>  << T >>  << A >>
Hello,
I want to perform a DMA via the Xilinx PCI-X core (64bit/133MHz) to the
system's DRAM. Therefore I want to act as a busmaster and transfer
4K-byte blocks (maximum bytecount) in initiator-burst-transfers. The
problem is that the DMA can be aborted at any time, so I have to
calculate the appropriate new byte-address, request the bus again and so
on. This can be a rather complicated design, so my question is: is there
any way to simplify a DMA like descriped above or are there any
interface-modules for the Xilinx PCI-X core which work as DMA-controller
for the core.
Futhermore I'm looking for a simulation-model for the PCI-X-bus-side.
Thank you for help,
Matthias


Article: 67049
Subject: Re: Jitter in DLLs vs PLLs
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 04 Mar 2004 08:12:01 -0800
Links: << >>  << T >>  << A >>
http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf

Is a side by side bench test of the DLL vs the PLL in a "real" situation 
where IOs and logic are switching, not just a quiet side by side 
back-off of a do-nothing design.

As frequencies increase, delays decrease, jitter fast becomes the number 
one problem in a design.

Realizing this, we have many tools, design notes, suggestions, and 
techniques to minimize jitter, and maximize performance.

Also,

http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf

is an excellent newly written description of the DCM (includes DLL) for 
Spartan 3 which also makes for good reading.

Austin

Michael Chan wrote:
> Just wondering if anyone can point me to some articals or papers that analyse
> the characteristics of xilinx DLLs vs altera PLLs.
> 
> Thanks.
> 
> 



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