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Mike Treseler <mike.treseler@flukenetworks.com> wrote: > You can wait UNTIL an expression has a value of true or > you can wait ON a signal_id for *any* value change. Modelsim don't come along with mysig<='1'; wait for 1 us;-- to allow signal update wait until mysig='1'; because mysig is allready '1'. In my opinion this is a bug, Modelsim should perform a test if mysig is allready '1' (Maybe there's someone out correcting my opinion). The code above needs a explicite if clause. bye ThomasArticle: 58901
Marc, By a very strange coincidence, a Belgian friend of mine (well, he's from Bruges so he's a bit weird :) who designs very tiny RF and micro boards (mostly portable stuff using MSP430) happened to have a kit from www.kanda.com that uses the AT40K chip. He offered it to me - complete with tool chain - for as long as I need it. So, it looks like I'm AVR'ing for now, but I'd rather be drinking a nice cold Orval. Rob Marc Van Riet wrote: > > But you are considering the Altera EP1C3 or the Actel APA150. Very hasty > comparison : > - dedicated flip flops : EP1C3 = 2910, APA150 = 0 (well, 6000), FPSLIC = > 2800 > - ram bits : EP1C3 = 60K, APA150 = 36K, FPSLIC = 128K (?) > Just to say the FPSLIC doesn't seem that small. Don't know how efficient > the architecture is though. > > Just a note : the AVR core and peripherals are not implemented in the FPGA, > they are on dedicated silicon. So they are not wasting any space. > > But of course it depends on the applications you have in mind. If you > didn't plan to have a microcontroller core, then this is not the device > you're looking for. Otherwise the device seems like a good idea, but didn't > hear of many people using it though. As Rickman mentioned, fear of it being > cancelled after a few years may have to do with this. > > Regards, > Marc > > "Rob Judd" <judd@ob-wan.com> wrote in message > news:3F2D5868.C49B912E@ob-wan.com... > > 40K gates is way too small for anything I'm considering, and the "added > > value" stuff just wastes internal space. We all know where to find AVR > > core and serial if we want it. > > > > Rob > > > > > > Marc Van Riet wrote: > > > > > > Anyone any experience with the FPSLIC devices ? They have several > packages > > > with low pin count (84 PLCC, 100 VQFP, 144 TQFP). Only up to 40Kgates > FPGA > > > (2800 registers), but you do have a processor core, and several > peripherals, > > > and 32Kbytes + 16 Kbytes of memory already built-in. > > > > > > Marc > > >Article: 58902
> Is there a way to perform the comands in batch mode or place them into > bitstream file? In my prev. message i ask about tools doing this. get JAM player, write some JAM functions and talk to the JTAG port anyway you wish. you can as example use BSCANVIRTEX and connect it to ICAP and reconfig or use use normal JTAG config commands or send commands to your custom JTAG functions/register (USER1, USER2 commands) :) anttiArticle: 58903
Martin, Copyright? Copyleft? Hey, if I do an I-Q converter, can I use CopyOrthogonal? Rob (at 90 degrees to reality) Martin Schoeberl wrote: > > BSD licencense is popular, but the original had some problems see: > http://www.gnu.org/philosophy/bsd.html > So get a copy of the 'new' version or state it like suggested 'revised BSD > license'. > Martin > > -- > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/ > > "Pacbell User" <dont_reply@dont_reply.com> schrieb im Newsbeitrag > news:sSgXa.472$gC7.418@newssvr23.news.prodigy.com... > > I would like to contribute a multi-cycle (slow, but area-compact) > > (Hehe, someone else already released a pipelined integer-divider, > > to the opencores.org repository. Gence I'm marketing my divider as > > 'compact'!) > > I am reading through the FAQ, and one part has me a bit confused... > > > > === > > > > The 'licensing' portion -- I understand that the 'GPL' license > > is fairly restrictive in that it forces derivative works to be > > distributed in documented *AND* modifiable form. > > > > My goal is to let *anyone* use my integer-divider as they see > > fit. If they want to use it in a closed commercial project, that's > > fine. It seems like a GPL-release cannot be used in a closed > > project, is that correct? > > > > So under which license should I release my divider? LGPL, BSD, etc.?!? > > > > ... > > > > Also, is Xilinx Webpack 5.1ISE the final version that will run > > under Win98se (no flames please)? The newer versions refuse to install. > > > >Article: 58904
"Thomas Stanka" <thomas@stanka-web.de> wrote in message news:d92cdee8.0308040057.30784b34@posting.google.com... > Mike Treseler <mike.treseler@flukenetworks.com> wrote: > > You can wait UNTIL an expression has a value of true or > > you can wait ON a signal_id for *any* value change. > > Modelsim don't come along with > > mysig<='1'; > wait for 1 us;-- to allow signal update > wait until mysig='1'; > > because mysig is allready '1'. In my opinion this is a bug, Modelsim > should perform a test if mysig is allready '1' (Maybe there's someone > out correcting my opinion). > No, it's not a bug. It's the way VHDL is defined. As someone else said, a wait statement is implicitly sensitive to all the signals in the boolean condition. So in your example, you can re-write wait until mysig = '1'; as wait on mysig until mysig = '1'; In Rick's original example, where the testbench "hung", you can sometimes use this approach wait until ArmStart for 100 us; -- 100 us timeout if ArmStart'EVENT then -- yippee, event occurred before time out -- so carry on else report "ArmStart didn't occur within 100 us - Doh!"; end if; regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 58905
I want to generate clocks of different frequencies of 150 Mhz, 38 Mhz, 8Khz from a clock of frequency 2048KHz. The factor comes out to be very odd. Can anyone please suggest me how can I do that? Regards MonibArticle: 58906
Hi I achieved only 550kBps, but I didn't do any soft emulation or negociation. If your port is set to epp/ecp, there's a register in the ecp configurations that changes the mode of the port to ecp, epp or spp. If your port is set to epp in the bios, it should allways be so... Ricardo Yash Bansal <yash@boa.ece.ucdavis.edu> wrote in message news:<Pine.HPX.4.21.0307311327130.17547-100000@boa.ece.ucdavis.edu>... > On Thu, 31 Jul 2003, Jon Elson wrote: > > > Yes, I have 2 commercial products using this. I get about 800 nS/byte > > with a short > > IEEE-1284 cable. Note that the PC EPP chips don't follow the IEEE-1284 > > standard, > > they don't delay the strobes, but present them about the same time as > > the data > > port changes. So, you have to apply delays to the strobes in your device. > > Then, you have to have the handshake signals bounce back through the cable > > twice (once to tell the CPU data is available, then the request from the CPU > > has to go away, then the remote device has to un-busy the bus.) > > I don't use any overhead software, but map to the port and control it > > directly > > with inline assembler directives in the C code for x86 INB and OUTB > > instructions. > > What are the products that you use? 800nsec/byte transfer rate is great > and will solve all my problems. Currently I get about 10usec/byte as I am > emulating the EPP protocol in SW. I have written a State-Machine in the > FPGA for implementing the EPP protocol but have not done the > EPP negotiation part. On the PC side acquisition software, all I did > was to write a user-level program that made use of the libieee1284 > functions. > > I am hoping that after implementing the negotiation in the FPGA, the EPP > protocol will run directly without having to emulate it in PC. > > My aim is to transfer 40KBytes/sec of data from FPGA to PC using parallel > port. > > Thanks,-Yash > > > > 1 Meg Byte/second is pretty ambitious, given the performance of the chips. > > If you have long blocks of data to transfer (several K bytes in one > > block) then > > the DMA mode of transfer may go a little faster. I haven't done this, > > as 20 bytes or > > so at a time is the most I can do with my particular device. > > > > What is the rate of data transfer you are getting now? What method are > > you using to access the parallel port? > > > > JonArticle: 58907
Hi Rob, After reading the ProASIC Plus data sheet, I believe you should be comparing to a Cyclone EP1C3, not a EP1C6. > EP1C6 (a better comparison) - 6K LE's (registers), 92K ram > APA150 - 150K gates, 6K registers, 36K ram The APA series uses a logic cell that can be either a 3-input LUT or a flop. Cyclone (EP1Cx) has a 4-input LUT _and_ a register, plus a bunch of dedicated circuitry for performing asynchronous clear, asynchronous load, synchronous clear, synchronous load, clock enable, dynamic add/subtract, and other stuff I'm probably forgetting. The register and LUT can feed one another, or can be used independently, allowing LUTs and flops to be packed together into a single cell. So my guess is that a APA150 with 6K cells will be somewhere in the neighbourhood of the density of a EP1C3. In addition, the APA devices are manufactured on a .22u technology with programmable cells, while Cyclone is manufactured on a 0.13u copper process. My guess is that Cyclone will be signficantly faster. Of course, your best bet is to get your hands on the CAD tools and push the big green button :-). Cyclone is supported in the Web Edition of Quartus II 3.0, available at www.altera.com. Regards, Paul Leventis Altera Corp.Article: 58908
Rob, > Copyright? Copyleft? Hey, if I do an I-Q converter, can I use > CopyOrthogonal? I didn't invent these words and I find them also strange ;-) Martin > > Rob (at 90 degrees to reality) > > > Martin Schoeberl wrote: > > > > BSD licencense is popular, but the original had some problems see: > > http://www.gnu.org/philosophy/bsd.html > > So get a copy of the 'new' version or state it like suggested 'revised BSD > > license'. > > Martin > > > > -- > > -------------------------------------------------------- > > JOP - a Java Processor core for FPGAs now > > on Cyclone: http://www.jopdesign.com/cyclone/ > > > > "Pacbell User" <dont_reply@dont_reply.com> schrieb im Newsbeitrag > > news:sSgXa.472$gC7.418@newssvr23.news.prodigy.com... > > > I would like to contribute a multi-cycle (slow, but area-compact) > > > (Hehe, someone else already released a pipelined integer-divider, > > > to the opencores.org repository. Gence I'm marketing my divider as > > > 'compact'!) > > > I am reading through the FAQ, and one part has me a bit confused... > > > > > > === > > > > > > The 'licensing' portion -- I understand that the 'GPL' license > > > is fairly restrictive in that it forces derivative works to be > > > distributed in documented *AND* modifiable form. > > > > > > My goal is to let *anyone* use my integer-divider as they see > > > fit. If they want to use it in a closed commercial project, that's > > > fine. It seems like a GPL-release cannot be used in a closed > > > project, is that correct? > > > > > > So under which license should I release my divider? LGPL, BSD, etc.?!? > > > > > > ... > > > > > > Also, is Xilinx Webpack 5.1ISE the final version that will run > > > under Win98se (no flames please)? The newer versions refuse to install. > > > > > >Article: 58909
Hi, I want to design an electrical interface for my stm-1 card. This card uses PMC5342 (SPECTRA) chip from PMC-Sierra for overhead termination. Spectra chip only has optical output. I want to use LXT6155 (stm-1 transceiver for coax cable or fiber). The problem with spectra is that LXT6155 gets data and clock signal from system side (in serial mode), but Spectra encodes data and clock signal on the single line, so I need to extract clock and data signal from spectra outputs. There are some chipsets for this in the market. I am not sure about this design, because i have seen some stm-1 boards from other vendors with Spectra and LXT6155 chipsets, but they have'nt use any clock and data recovery chipsets. Please guide me about this. Best regards Masoud Naderi.Article: 58910
Hi, I have to connect a LCD-I2C to my FPGA. My LCD can be supplied only with 5V, and I have only a 3.3V. Do you know a low cost step-up dc-dc converter solution. I only need 2 mA as output current. Regards, LaurentArticle: 58911
Don't waste your time. Think 2 sec. If the wait until was sensitive on condition level and your signal ARM_Bus_Start is true for 10ns and your simulator's resolution is set at 1ps then the process would be executed 10000 times in row. Your simulation will take 6 month to execute. Check in your vhdl book. If you don't have a book, I recommend The Designer's Guide to VHDL by Peter Ashenden. P.A. wrote in is book : the condition is tested whenever an event occurs on any of the signals mentioned in the condition. regards FE Sr ASIC Designer "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F2DF114.F6DDB8AE@yahoo.com... > Mike Treseler wrote: > > > > rickman wrote: > > > . . . > > > differently and reaches the end of the process. At the top of this > > > process, it waits for the "Start" signal again, but if the "Start" flag > > > is already set, it hangs. > > > > > > So does a wait statement always perform an edge detect by default? > > > > No. > > You can wait UNTIL an expression has a value of true or > > you can wait ON a signal_id for *any* value change. > > > > > Here is my wait statement... > > > wait until ARM_Bus_Start or rising_edge(Reset); > > > If ARM_Bus_Start is already set when this executes, the process hangs > > > here. > > > > Consider View, Source > > and setting some breakpoints. > > Run/step code and watch the signals. > > > > Either the wait is in a different process > > or ARM_Bus_Start is not true at the right time. > > I did look at everything in detail in the simulator. The wait statement > shown above executes with ARM_Bus_Start set to true and the process is > hung at that wait. I have solved the problem by testing ARM_Bus_Start > before I execute the wait and it runs as expected. So it is pretty > clear that the issue is the wait requiring a change in state of a signal > in the expression before it evaluates the expression. > > I will try some more tests when I get a chance. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58912
cfk, Not "all", just one extra per Vcco power/ground pin pair is all that is required to reduce ground bounce by another 20% (roughly). The IO is set to a strong standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is connected to the ground plane just like a ground pin. Adding pins past the first leads to a very small improvement (not worth it). Making these grounds adjacent to clock inputs, or Vref pins can also aid in the reduction of user pcb crosstalk. The packages already have 3X spacing for every Vref, which means that x-talk coupling to/from Vref pins is 1/9 that of the coupling to any other pin in the package (ie, the package is not the 'problem'). Austin cfk wrote: > And just to add a little spice to that broth, it was suggested one of the > local Xilinx support folks on our last design to ground all the unused IOB > pins and create more of a "virtual ground" (their term, not mine). > > "William LenihanIii" <lenihan3we@earthlink.net> wrote in message > news:5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net... > > We will be designing with a large (xc2v6000) Virtex-II part in a ball-grid > > array package that has maybe ~1000 balls, but we are using fairly few > (~250) > > "mission logic" I/O. Add in power & ground, configuration, etc., we will > > have 100's of general-purpose I/O balls that are not needed. > > > > What should we do with them? Ground them? Let them float? If we can let > them > > float, do we even need a solder pad on the PWB for them to "land on"? > > > >Article: 58913
> > > > > > Or maybe there is a way to configure NIOSes SDRAM controller to support > > > two NIOS CPUs instead of using that external arbiter? > > > > > > > The second thing I can suggest, and would recommend, is to make use of > > our own bus arbitration logic. You can in fact connect two (or more) > > masters (two Nios', DMA, your own custom master, another > > microprocessor) to any avalon slave, including the SDRAM controller. > > > > I believe that in the end I will use this controller, but for now I just have > to use the "external" arbiter, because this controller/arbiter allows me to > access the SDRAM directly through the PCI (the development board is a PCI card) I've decided to use Nios'es SDRAM controller, so please disregard my last question - that third-party arbiter caused too much problems. So thanks anyway, YevgenyArticle: 58914
Rick, My point exactly. If you simulate a TTL driver, you will note it can't pull up enough to violate our spec, and so no resistor is required. Of course, it has to be a TTL driver, and not a CMOS driver! Now given anyone can build a pcb and sell it, I would go with the TI, or Quickswitch NMOS pass-gate voltage limiter part to be safe (and 100% compatible). Austin rickman wrote: > Austin Lesea wrote: > > > > Rick, > > > > Fair enough. If it has to drive all the way to 5.0 V CMOS, then you have outlined > > your constraints. > > > > Too bad that they did not choose to be TTL compatible. > > Are you talking about the PC/104 bus? That is based on the ISA bus, > which IIRC predates FPGAs. I think you mean too bad it is not limited > to TTL thresholds. Even TTL logic outputs can and will rise above 3.6 > volts if lightly loaded. The pullup resistors are there for wire ORing > of a few signals (like ENDXFER- and IOCH16-) which I am sure you are > familiar with. The pullups are stiff to give speed. How else would you > have done that? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58915
Anything is possible, But you can't use 90nm for 5V. The minimum size you can use is .35u. A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit tough. But then again, where is the $? Peter and I are engineers, not marketeers, so we defer to the marketing folks who seem to know just how large (small) the 5V market is.... Austin "B. Joshua Rosen" wrote: > Peter, Austin, > > Is it possible to build 5V IOs on a 90nm process? The world is full of > antique buses that aren't going to go away anytime soon. A couple of > medium sized devices targeted at the legacy bus interface market would be > useful. I'd suggest doing two devices, a XC3S1500 and a XC3S400 with > 5V/3.3V IOs. You could toss the multipliers, those aren't useful in this > application, as well as all of the fancy modern IO standards which also > aren't needed for this application, block RAM is important because bridges > need large FIFOs. The other thing that you would want to do is modify the > DCM so that it could support lower clock frequencies, 10Mhz -20Mhz is > common in this world.Article: 58916
Hal, Filters with a Q of ~ 100 provide a fairly substantial reduction of jitter (~20:1 measured reduction in jitter with Q ~ 120). LC at least. Crystal not required. RC too low Q. Austin Hal Murray wrote: > >So clever people used the DDS to create a sine wave, then filtered the > >sine wave with an analog filter, then used a comparator to slice it back > >into the digital domain, with reduced jitter. > > What sort of analog filter do I need for this approach? > > Do I need a serious narrow band pass filter? Aka a crystal if > I want a real good one, which probably means I should just get > a packaged osc. > > Or will a simple R/C low pass filter that cuts off at the target > frequency provide enough attenuation at the 3rd/5th harmonics > to make a low-jitter clock? > > R/C filters are pretty cheap. You might need some ugly op-amps > and more Rs and Cs to get several poles. [But logic is cheap too, > especially if you already have an FPGA and board space is critical.] > > > But it is a tortuous detour, and faster multi-phase DDS > > seems to be so much simpler... > > That just reduced the jitter by a factor of "multi". Right? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 58917
Hi all, Could any one tell me where I can find a sample VHDL code for interfacing a Motorola MPC860 (External Bus Operation : Single-Beat Transferts and Burst Transferts) with a FPGA ?. Thanks lot in advance P..Article: 58918
Hi, Can someone tell me if there is a Xuart Lite driver for Linux already and where I might find the patches before I continue with writing one? Cheers, Jon.Article: 58919
They have no magic rule. Everything depend of your design. If your target is a FPGA 4 inputs lut base (Altera, Xilinx) and you have a lot of combinatorial stuff with more than 4 signals per equation and small among of flip-flop and no ram then you will need a high ratio. For example: In the past, I saw a 25k gates .35u standard cell where the equivalent smallest Xilinx FPGA part was a 2 millions gates (1:80 ratio). If your target is a CPLD and your design need a lot of xor or flip-flop then you will blow-up all CPLD because normally they have only one xor and one dff per macrocell. So check your design, the target technology and do your best. regards FE "Jay" <yuhaiwen@hotmail.com> wrote in message news:bgkjsj$oujal$1@ID-195883.news.uni-berlin.de... > Hi all, > > I'm doing prototyping for ASICs. Before I start my work, I have to estimate > the gates the FPGA or CPLD would use. > I know it's hard to get a precise result. I just want some common answer, > 1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just > logic) > Please tell me your experience. > > Thanks, > Jay > >Article: 58920
Thomas Stanka wrote: > > Mike Treseler <mike.treseler@flukenetworks.com> wrote: > > You can wait UNTIL an expression has a value of true or > > you can wait ON a signal_id for *any* value change. > > Modelsim don't come along with > > mysig<='1'; > wait for 1 us;-- to allow signal update > wait until mysig='1'; > > because mysig is allready '1'. In my opinion this is a bug, Modelsim > should perform a test if mysig is allready '1' (Maybe there's someone > out correcting my opinion). > > The code above needs a explicite if clause. I read the LRM more fully and it does clearly say that a wait statement suspends the process until either the timeout expires or an event occurs on the "sensitivity list". This sensitivity list includes all the signals in the condition clause as well as the signals in the sensitivity clause. Now that I think about it, since you can use variables in the condition clause, you can construct a wait that will never resume because there are no signals to be placed in the sensitivity list. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58921
Austin Lesea wrote: > > Rick, > > My point exactly. If you simulate a TTL driver, you will note it can't pull up enough > to violate our spec, and so no resistor is required. The TTL I am familiar with, running from 5 volt Vcc can and does pull above 3.6 volts, which I belive is your max value. I have seen this on the scope many times. But then drawing a bit of current brings it down so your inputs may well live with this current. > Of course, it has to be a TTL driver, and not a CMOS driver! > > Now given anyone can build a pcb and sell it, I would go with the TI, or Quickswitch > NMOS pass-gate voltage limiter part to be safe (and 100% compatible). I think we have had this conversation before. PC/104 is not a large format with loads of room for interface chips. It is much preferred to use a 5 volt tolerant FPGA. That is why I am planning to use the Altera ACEX EP1K30 as the PC/104 interface chip. If Xilinx had support in the current tools for the Spartan XL, I would likely consider that chip. And of course all the Virtex derived devices are not options because of the large startup current surge. Of course there are additional circuits that can be added to make the Xilinx chips work in this socket, but why add complexity when a single chip will do the job? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58922
Austin Lesea wrote: > > Anything is possible, > > But you can't use 90nm for 5V. The minimum size you can use is .35u. > > A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit > tough. > > But then again, where is the $? > > Peter and I are engineers, not marketeers, so we defer to the marketing folks > who seem to know just how large (small) the 5V market is.... > > Austin At what process size does the 3.3 volt compatibility go away? I have never understood why the voltage is a problem. I understand that the thin oxide for the gate will not take the voltage. But I don't see why the IO transistors can't be made with thicker oxides. All chips have thick oxides all over the chip on many layers for isolation. Seems pretty simple to add one more oxide layer for the IO transistor gates. I understand that this will slow the chip IO a bit and may add a bit of cost, but it is no technical hurdle and 5 volt is still a market. To be able to address the 5 volt sockets in addition to the regular market seems to be a win-win. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58923
Rick, It has to do with the foundires. What do you offer as your lowest cost standard CMOS process? .18/.35 was really popular (and still is). .15/.35 was the half-step between .18 and .13. .13/.25 is the dominat process right now (3.3V is a tough push, and has to be done carefully, and 5V is definitely gone) 90nm/.25u is what we are in for Spartan 3, so there has to be a reason (like all those three letter companies that offer standard CMOS processes....) If you havce 90nm/.35u (no reason why it can't be done), you lose all your speed and area by having to drive the huge .35u transistors (makes for a more expensive die). For that reason, IOs remain a few steps back on the shrink curve. Austin rickman wrote: > Austin Lesea wrote: > > > > Anything is possible, > > > > But you can't use 90nm for 5V. The minimum size you can use is .35u. > > > > A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit > > tough. > > > > But then again, where is the $? > > > > Peter and I are engineers, not marketeers, so we defer to the marketing folks > > who seem to know just how large (small) the 5V market is.... > > > > Austin > > At what process size does the 3.3 volt compatibility go away? > > I have never understood why the voltage is a problem. I understand that > the thin oxide for the gate will not take the voltage. But I don't see > why the IO transistors can't be made with thicker oxides. All chips > have thick oxides all over the chip on many layers for isolation. Seems > pretty simple to add one more oxide layer for the IO transistor gates. > > I understand that this will slow the chip IO a bit and may add a bit of > cost, but it is no technical hurdle and 5 volt is still a market. To be > able to address the 5 volt sockets in addition to the regular market > seems to be a win-win. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58924
As others have suggested, TCP is something that implemented entirely in hardware, would be pretty resource intensive. There are many operations going on which are well suited for an embedded CPU to handle. Acceleration (or off-loading) can be done by handling things such as checksum calculations in hardware... in the end, I think that you'll see many embedded Ethernet solutions (on FPGA or not) use a mix of HW and SW to implement everything. Also, if you're willing to take a look at unsupported IP (in contrast to commercial IP), I would also second that you take a look at the opencores.org 10/100 MAC. It has been ported to support the Nios CPU (and Plugs IP stack)... in my own playing with it, it takes just over 2500LEs and has its own integrated DMA controller - its really well architected. The port (ready to drop into SOPC Builder if you want to give it a try with Nios) is available from MaCo-Engineering (www.maco-engineering.de), in the "Download" page. Jesse Kempa Altera Corp. jkempa at altera dot com erik.coenders@philips.com (Erik Coenders) wrote in message news:<f5fc2c9a.0307310717.4d340e4a@posting.google.com>... > Hi, > > As a study for a project I need to investigate the possibility of > implementing a tiny TCP/IP stack and tiny MAC controller on FPGA. This > stack is capable to transfer some data packets directly into S(D)RAM > without help of the microcontroller. Thus a simple communication via > Ethernet from the desktop PC is required for download/upload to/from > the memory. > > The FPGA board is attached to an Ethernet PHY device such as DP83847A. > In this case a MAC controller was implemented in FPGA but the FPGA > utilitization is too high. There is less room available for other > blocks. My intention is to build a small TCP/IP stack and MAC blocks > in the FPGA and the transaction between FPGA/Ethernet PHY and the > desktop PC has to kept as simple as possible. Thus no heavy/extensive > protocol is needed. > > The questions raised are: > 1. What is the minimum TCP/IP function set required to do simple file > transfer and etc.? > 2. Is it possible to perform all tasks only in FPGA without help of > the microprocessor? > 3. Are there any resources (VHDL code and C program on PC) available > on this topic? > > I will welcome all comments and suggestions. please feel free to write > us at erik.coenders@philips.com Thank you all.
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