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To simplify the explanation: Any I/O tolerates any voltage between slightly below ground to slightly above Vcco. That is a basic fact and applies to all manufacturers. The interesting question is: What happens when you drive the pin substantially ( i.e.>0.5 V) above Vcco. Then the pin either has a diode to Vcco and you need a current-limiting resistor. Or the pin does not have such a diode to Vcco, and you can drive the pin higher, but you finally rely on some other protection device (SCR?) clamping at a higher voltage to prevent damage to the device (gate oxide breakdown). Peter Alfke =============== Prashant wrote: > > Austin, > Thank you very much for the explanation. I wanted to be sure that I > understood the problem well. It would have been nice if xilinx had > that feature. I also did find out that Apex20KE would not support 1.8V > input or output signals unless the Vccio was at 1.8V. So my assumption > in my earlier email was wrong. Although, at Vccio = 3.3V, the inputs > are 2.5 and 3.3V tolerant. > > Regards, > Prashant > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F284FDE.71CE8DCF@xilinx.com>... > > Pete, > > > > We win some, we lose some. You never know what "feature" (or latent bug) will > > be the deciding factor. > > > > But thanks for the feedback. I was well aware of the issue and the tradeoffs. > > If folks want that 5V input tolerance without limiting resistors, they can > > still buy Xilinx and use Spartan II, or Virtex. > > > > Austin > > > > Pete Fraser wrote: > > > > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > > > news:3F282CEE.521DD3E1@xilinx.com... > > > > > > > The reason why we "do not have this feature" is that the IO ESD cell > > > > required for that feature is a non standard cell design (ie not a foundry > > > > supported standard ESD IO cell). > > > > > > Thanks for the explanation. It's the first time I've > > > heard it in adequate detail. > > > > > > However, you should know that it has cost you > > > at least two designs that I know of.Article: 58726
"emilia" <enoorsal2002@yahoo.com> wrote in message news:5eaba488.0307310635.63a5efa6@posting.google.com... > Hi All, > > I have some questions regarding my frequency counter design which is > using xc4085xl-09-bg560. I am using Xilinx Foundation series 2.1i. > This Frequency Counter is to measure frequency from QCM (Quartz > Crystal Microbalance sensor) which operate at 10MHz. There will be 8 > QCM input hence i am using 8 clock input. There is probably no reason to use global buffers for any of the QCM inputs. If you are just measuring their frequencies, each QCM input is probably only driving a single counter, which is then sampled into the system clock domain. Since each QCM load is small, you don't need a global buffer. You just need one for the system clock. -KevinArticle: 58727
nospam wrote: > The MSB of the phase accumulator *is* your squarewave clock. The only > problem is its edges jitters by as much as the phase accumulator clock > period, in your case 25ns which is a bit embarrassing as the edges of the > clock you are trying to generate are only 23ns apart. > > You only on chip solution is to use a faster phase accumulator clock to > reduce the output jitter to an acceptable level. Not quite true. You can get creative and use eight offset accumulators and eight clocks (we have plenty of global clocks) staggered through the clock period and thus reduce the basic jitter by a factor 8. Run at 200 MHz, and the jitter ends up +/- 300 ps, perhaps acceptable... Duty cycle is not an issue (beyond jitter). Frequency resolution is just a question of accumulator length. Peter AlfkeArticle: 58728
> > I did a functional simulation but I have timing problems with embedded > ram cells that are not detected by static analysis (either dc or > quartus). Consider inferring the ram instead of instancing. Much easier to simulate. -- Mike TreselerArticle: 58729
Nikos Annitsakis wrote: > Hi all. > > I am trying to learn VHDL on my own using textbooks and the Altera > MaxPlusII Baseline simulator. Consider running simulation before synthesis. Consider using direct instances. Here's a related example: http://groups.google.com/groups?q=treseler+structural+testbenches -- Mike TreselerArticle: 58730
Jacques athow wrote: >I have a project that needs a 21.48MHZ clock input. But the problem is >that I dont have that type of oscillator. As the project is going to >be in an large FPGA , is it possible to generate using coregen and a >40MHZ square source(the FPGA clock), a dds with adequate resolution >and that at a certain phase increment, would in turn generate the >21.48MHZ needed but as a sinusoid. > >Now, in order to complete the design, the signal would remain in the >digital domain and pass through some clipping logic, which would give >a '1' when the sine value is greater than an arbritrary index. > There IS no sine wave. Just use the most significant bit of the accumulator, and you'll have a square wave with a very nearly 50% duty cycle (depending on the number of accumulator bits). JonArticle: 58731
Yash Bansal wrote: >Hi, > >I am currently trying to perform a readout from FPGA to a LINUX PC using >parallel port. I have implemented the state-machine for EPP communication >in the FPGA and it works well however the system is slow. > >I think this is because EPP devices are supposed to negotiate the best >available transfer mode during initialization but the FPGA is not >currently setup to do that. As a result, I had to fall back on software >emulation of the data transfer handshaking. > >I was wondering if anyone has experience performing readout from FPGA >using EPP. My aim is to get 1MByte/sec communication. Any help would be >appreciated. > > Yes, I have 2 commercial products using this. I get about 800 nS/byte with a short IEEE-1284 cable. Note that the PC EPP chips don't follow the IEEE-1284 standard, they don't delay the strobes, but present them about the same time as the data port changes. So, you have to apply delays to the strobes in your device. Then, you have to have the handshake signals bounce back through the cable twice (once to tell the CPU data is available, then the request from the CPU has to go away, then the remote device has to un-busy the bus.) I don't use any overhead software, but map to the port and control it directly with inline assembler directives in the C code for x86 INB and OUTB instructions. 1 Meg Byte/second is pretty ambitious, given the performance of the chips. If you have long blocks of data to transfer (several K bytes in one block) then the DMA mode of transfer may go a little faster. I haven't done this, as 20 bytes or so at a time is the most I can do with my particular device. What is the rate of data transfer you are getting now? What method are you using to access the parallel port? JonArticle: 58732
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qh8yqftzf2.fsf_-_@ruckus.brouhaha.com>... > Austin Lesea <Austin.Lesea@xilinx.com> writes: > > Hyperlynx handles connectors, daughter cards, etc. It just gets complex, which is not so much of a problem, as it is reality. > > The web site and data sheet look great. But what input formats for the > PCB design do they support? Any open formats? I use Eagle, which isn't > listed. I wouldn't mind writing a translator to some other open format > if necessary, but if they only support proprietary formats it won't do > me any good. The hyperlynx7_ext.pdf tells us that: BoardSim is compatible with these PCB layout systems: • Mentor Graphics PADS® PowerPCB™, Expedition™, Board Station® • Cadence Allegro, SPECCTRA and OrCAD Layout • Altium Protel and P-CAD • Zuken CADStar, Visula and CR3000/5000 PWS So, I guess they don't support Eagle, although I would imagine that you could call them to find out for sure, and if they don't, you can always ask them to add that support. > And what does a single-user license for Hyperlynx EXT cost? Easily in four figures -- an order of magnitude more expense than Eagle. Of course, depending on your board's complexity (and what your engineering time is worth), that might be cheaper than a board spin. --aArticle: 58733
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F2923F5.32975097@yahoo.com>... > Prasanna wrote: > > > > Here are some examples I can think of. > > > > Lets say you have a mode bit that you use in your logic and you know > > some paths specifically do not exist when the core is not in that > > mode, that becomes a false path. > > > > Lets say, you do a complex logic such as a CRC and find that your > > final CRC evaluation takes more than one clock cycle (based on byte > > enables) and cannot meet the speed requirements. You can pipeline the > > data and calculate final CRC in multiple clock cycles. > > This is exactly what multicycle is not. If you allowed the CRC > calculation to have two or three clock cycles for the logic delays to > settle out and used an enable on the register at the end, that would be > a multicycle path. This requires a separate multicycle timing spec > since otherwise the tool will try to optimize this to get it to run in > one clock cycle. If you add pipeline registers, then each stage will > need to be done in a single clock cycle and will definitely *not* be > multicycle. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX I guess you know what I meant on multicycle path on calculating final CRC. I was not mainly addressing the issue how to use pipeline here. I used the word pipeline there to address the issue of what do you do with the incoming data when the logic is taking multiple clock cycles to complete a job. I think designers do understand how to keep data stable for more clocks with enables. Guess I focussed my point this time on multicycle path.Article: 58734
The sine wave... I agree that this design does not need any sine wave, but here is why people seem to think it does: It's well known that DDS creates bad jitter, sometimes unacceptable amounts of it. So clever people used the DDS to create a sine wave, then filtered the sine wave with an analog filter, then used a comparator to slice it back into the digital domain, with reduced jitter. I suppose that trick is in the back of people's minds. But it is a tortuous detour, and faster multi-phase DDS seems to be so much simpler... Peter Alfke ========== Jon Elson wrote: > There IS no sine wave. Just use the most significant bit of the > accumulator, > and you'll have a square wave with a very nearly 50% duty cycle (depending > on the number of accumulator bits). > > JonArticle: 58735
Andy, That is why people should all just buy Hyperlynx (or equivalent*): it saves you money in board spins (in fact the first kit and respin would pay for it in most cases). Don't just take my word for it, ask anyone who has had to do board respins due to SI problems. The Hyperlynx folks did a super job, and even though they are now owned by Mentor (who also has some even fancier and much more powerful tools -- for more money of course), I still like Hyperlynx for its ability to do the fastest and easiest "what ifs" of any tool on the market. Austin *Note: for really powerful tools, I also like Cadence SpectraQuest. You can not go wrong with any of them! Andy Peters wrote: > Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qh8yqftzf2.fsf_-_@ruckus.brouhaha.com>... > > Austin Lesea <Austin.Lesea@xilinx.com> writes: > > > Hyperlynx handles connectors, daughter cards, etc. It just gets complex, which is not so much of a problem, as it is reality. > > > > The web site and data sheet look great. But what input formats for the > > PCB design do they support? Any open formats? I use Eagle, which isn't > > listed. I wouldn't mind writing a translator to some other open format > > if necessary, but if they only support proprietary formats it won't do > > me any good. > > The hyperlynx7_ext.pdf tells us that: > > BoardSim is compatible with these PCB layout systems: > • Mentor Graphics PADS® PowerPCB™, Expedition™, > Board Station® > • Cadence Allegro, SPECCTRA and OrCAD Layout > • Altium Protel and P-CAD > • Zuken CADStar, Visula and CR3000/5000 PWS > > So, I guess they don't support Eagle, although I would imagine that > you could call them to find out for sure, and if they don't, you can > always ask them to add that support. > > > And what does a single-user license for Hyperlynx EXT cost? > > Easily in four figures -- an order of magnitude more expense than > Eagle. Of course, depending on your board's complexity (and what your > engineering time is worth), that might be cheaper than a board spin. > > --aArticle: 58736
On Thu, 31 Jul 2003, Jon Elson wrote: > Yes, I have 2 commercial products using this. I get about 800 nS/byte > with a short > IEEE-1284 cable. Note that the PC EPP chips don't follow the IEEE-1284 > standard, > they don't delay the strobes, but present them about the same time as > the data > port changes. So, you have to apply delays to the strobes in your device. > Then, you have to have the handshake signals bounce back through the cable > twice (once to tell the CPU data is available, then the request from the CPU > has to go away, then the remote device has to un-busy the bus.) > I don't use any overhead software, but map to the port and control it > directly > with inline assembler directives in the C code for x86 INB and OUTB > instructions. What are the products that you use? 800nsec/byte transfer rate is great and will solve all my problems. Currently I get about 10usec/byte as I am emulating the EPP protocol in SW. I have written a State-Machine in the FPGA for implementing the EPP protocol but have not done the EPP negotiation part. On the PC side acquisition software, all I did was to write a user-level program that made use of the libieee1284 functions. I am hoping that after implementing the negotiation in the FPGA, the EPP protocol will run directly without having to emulate it in PC. My aim is to transfer 40KBytes/sec of data from FPGA to PC using parallel port. Thanks,-Yash > 1 Meg Byte/second is pretty ambitious, given the performance of the chips. > If you have long blocks of data to transfer (several K bytes in one > block) then > the DMA mode of transfer may go a little faster. I haven't done this, > as 20 bytes or > so at a time is the most I can do with my particular device. > > What is the rate of data transfer you are getting now? What method are > you using to access the parallel port? > > JonArticle: 58737
Here is a time-proven hardware design for bit-serial binary to parallel BCD conversion. (I published this in 1973 in the Fairchild TTL Applications Handbook). Implement a bunch of 4-bit loadable shift register, but do not interconnect them. For each shift register drive a 4-bit adder (without carry in, but with carry output) from the 4 shift register outputs. Put a binary eleven (B) as other input on the adder. Connect the adder outputs to the shift register load inputs, but skewed one position downstream ( bit 0 of the adder drives bit 1 of the shift register ). Then use the carry output as load enable for "its" shift register, and also as input for the LSB of the downstream shift register ( both as shift- and as load- input) The S3 output ( most significant sum) goes nowhere. That's it. Shifting in binary data (MSB first) doubles the binary value on every shift. The adder monitors this and, on its carry output, signals that there is a value 5 or larger, which needs intervention: add 3 before the next shift ( which is equivalent to adding 6 after having shifted it) and load a carry into the next higher bit position. The neat trick is that the 4-bit adder simultaneously adds eleven to create a carry that detects the need for modification, and also adds three to do the modification. Shift in binary data, MSB first, and watch the BCD develop on the parallel shift register outputs. Note that BCD needs more bit positions than binary, so leave some headroom. Works like a champ, flawlessly since 30 years ago. Peter Alfke, no longer at Fairchild (but it was an interesting 10 years) ==================== Mike Treseler wrote: > > Paul Leventis wrote: > > Hi Jason, > > > > First off, that's a pretty cool little algorithm... had to prove to myself > > that it worked. ... > > > > I'm not sure that I've found the problem with your code, ... > > The best and quickest way to do both is to write a testbench an run a sim. > This quickly resolves all questions about how the langage works > and how the logic functions. > > > (0) I think the first problem is a lack of comments... uncommented code is > > always wrong :-) > > My favorite comments are a plain text description at the top of each > process about function and handshake protocols. > These can be collected at the top of the architecture after the > sim is working. > > Detail comments at the end of line, can often be replaced by > by well-named statement labels, constants and variables. > > > (1) Process #3. I hate variables. Especially variables mixed with > > signals... > > Signals are the only way in and out of a process. > > > you must be very disciplined when using variables (I only use > > them in for loops...). So I honestly don't know what the code will > > translate into, as you are assigning a value to variable, then assigning to > > the variable to a signal, then changing the value of the variable. > > In the case referenced, the first value is exported to the signal at > the next clk and the second value is held by the variable until the next clk, if > it is needed. > > This is not as complex as you think. Variables are stuck inside the process. > They only reach the entity ports if you make a signal assignment inside > the process. Synthesis will use a register to save the variable's *final* value. > only if this value is needed at the next clk. > > Run a sim sometime, and watch the variables as you trace code. > > -- Mike TreselerArticle: 58738
Is ther a specification for the Spartan 3 overshoot on the I?o pin that is given in terms of energy rather than just voltage limit? An example might be a given voltage for a given lingth of time, of a given current for a given length of time. This is more an "area under the curve" kind of thing. Any takers? Thanks for your help. SteveArticle: 58739
Peter Alfke <peter@xilinx.com> wrote: >Your first question should be the allowable peak-to-peak jitter of the >21.48 MHz output. >Using a 40 MHz-clocked DDS would give you max +/-12 ns jitter in a >purely digital design, no sinuoids at all. 12.5ns jitter on 21.48MHz means complete cycles will be missed so it is fundamentally not allowable.Article: 58740
Has anyone used Content Addressable Memory to perform string matching? I don't know much of anything about CAM, but I can imagine it would be much more flexible than hard-coding the strings I want to search for. However, will there be a huge hit in speed? I realize they can be read in 1 clk, but will the max speed of the FPGA take a hit? I don't suppose there are coded examples out there?Article: 58741
For CAM designs in Xilinx FPGAs, see: www.xilinx.com/xapp/xapp201.pdf and www.xilinx.com/xapp/xapp204.pdf Peter Alfke, Xilinx Seth wrote: > > Has anyone used Content Addressable Memory to perform string matching? > > I don't know much of anything about CAM, but I can imagine it would be > much more flexible than hard-coding the strings I want to search for. > However, will there be a huge hit in speed? I realize they can be > read in 1 clk, but will the max speed of the FPGA take a hit? > > I don't suppose there are coded examples out there?Article: 58742
Clever, clever... But a few lines further down I suggested ways to reduce it to 0.3 ns.... Peter Alfke nospam wrote: > > Peter Alfke <peter@xilinx.com> wrote: > > >Your first question should be the allowable peak-to-peak jitter of the > >21.48 MHz output. > >Using a 40 MHz-clocked DDS would give you max +/-12 ns jitter in a > >purely digital design, no sinuoids at all. > > 12.5ns jitter on 21.48MHz means complete cycles will be missed so it is > fundamentally not allowable.Article: 58743
Steve, Contact me directly (by email). It is not that easy, but I would like to discuss it with you. Austin insight@highwayman.tv wrote: > Is ther a specification for the Spartan 3 overshoot on the I?o pin that is given in terms of energy rather than just voltage limit? An example might be a given voltage for a given lingth of time, > of a given current for a given length of time. This is more an "area under the curve" kind of thing. Any takers? > > Thanks for your help. > > SteveArticle: 58744
Hi Jason,
I found your algorithm in C (see source after the vhdl code) on the net.
It's cool.
I rewrited your code like this (see bellow) and it works fine (I tested):
(bin and bcd width (20 and 24) could be replaced by constants (C_BIN_WIDTH,
C_BCD_WIDTH)).
Hope this will help.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bin2bcd is
port(
i_clk : in std_logic;
i_rst_an : in std_logic;
i_load_data : in std_logic;
i_data : in std_logic_vector(20-1 downto 0);
o_data_rdy_q : out std_logic;
o_data_q : out std_logic_vector(24-1 downto 0)
);
end bin2bcd;
architecture rtl of bin2bcd is
begin
--------------------------------------------------------------------------
----
-- register mapping:
--
-- ------------------------
-- | v_bcd_bin_q |
-- ------------------------
-- | av_bcd_q | |
-- ------------------------
-- | | av_bin_q |
-- ------------------------
-- |xxx| 3 bits overlaps to save 3 clk cycle processing and 3
dff
--
--------------------------------------------------------------------------
----
ps_bin2bcd : process (i_rst_an, i_clk)
variable v_cnt_q : integer range 0 to 17;
variable v_en_shift_q : std_logic;
variable v_data_rdy_q : std_logic;
variable v_bcd_bin_q : unsigned(20+24-3-1 downto 0);
alias av_bin_q : unsigned(20-1 downto 0) is v_bcd_bin_q(20-1 downto 0);
alias av_bcd_q : unsigned(24-1 downto 0) is v_bcd_bin_q(20+24-3-1 downto
20-3);
begin
if i_rst_an = '0' then
v_cnt_q := 0;
v_en_shift_q := '0';
v_bcd_bin_q := (others => '0');
v_data_rdy_q := '0';
elsif rising_edge(i_clk) then
if i_load_data = '1' then
av_bcd_q := (others => '0');
av_bin_q := unsigned(i_data);
v_cnt_q := 0;
v_en_shift_q := '1';
v_data_rdy_q := '0';
elsif v_cnt_q = 17 then
v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
v_cnt_q := v_cnt_q; -- optional assignment
v_en_shift_q := '0';
v_data_rdy_q := '1';
elsif v_en_shift_q = '1' then
for i in 0 to 5 loop
if av_bcd_q(4*i+3 downto 4*i) >= 5 then
av_bcd_q(4*i+3 downto 4*i) := av_bcd_q(4*i+3 downto 4*i) + 3;
end if;
end loop;
v_bcd_bin_q := v_bcd_bin_q sll 1;
v_cnt_q := v_cnt_q + 1;
v_en_shift_q := v_en_shift_q; -- optional assignment
v_data_rdy_q := v_data_rdy_q; -- optional assignment
else
v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
v_cnt_q := v_cnt_q; -- optional assignment
v_en_shift_q := v_en_shift_q; -- optional assignment
v_data_rdy_q := v_data_rdy_q; -- optional assignment
end if;
end if;
o_data_q <= std_logic_vector(av_bcd_q);
o_data_rdy_q <= v_data_rdy_q;
end process;
end rtl;
**********C source code************
#include <stdio.h>
#include <stdlib.h>
#include <conio.h>
#define BIN_SIZE 4
#define MSB_MASK 0x80000000L
#define BCD_SIZE 13
typedef unsigned long BIN;
typedef unsigned char BCD[BCD_SIZE];
main()
{
BIN bin1,bin;
BCD bcd;
int i,j,k,carry;
char temp[9];
printf("enter number:");
scanf("%lu", &bin1);
bin=bin1;
for (i=0; i<= BCD_SIZE; i++) bcd[i]=0;
printf("\n BCD BIN\n");
for (i=0; i<8*BIN_SIZE; i++) {
/* check for overflow */
for (j=0; j<BCD_SIZE; j++) {
if (bcd[j] >= 5) {
bcd[j] += 3;
/* printout for checking */
for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
printf(" %x\n", bin);
}
}
/* shift right */
carry = (bin & MSB_MASK) == MSB_MASK;
bin = bin << 1;
for (j=0; j<BCD_SIZE; j++) {
bcd[j] = (bcd[j] << 1) | carry;
carry = (bcd[j] & 0x10) == 0x10;
bcd[j] = bcd[j] & 0xF;
}
/* printout for checking */
for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
printf(" %x\n", bin);
}
printf("BIN = %lu\n", bin1);
printf("BCD = ");
for (k=BCD_SIZE; k--; ) printf("%d", bcd[k]);
}
regards
FE
"Jason Berringer" <look_at_bottom_of@email.com> wrote in message
news:IlGVa.3393$mv6.617644@news20.bellglobal.com...
> Here is the code (after my text) instead of an attachment in case others
> cannot read it.
>
> It takes (or should take) 20 to 21 clock cycles to get the data from the
> input to the output. I put a few numbers through the simulation the only
> correct values are 0 and 1, all other tested were incorrect. I'm pretty
sure
> it's a simple error that I'm not catching, I just can't see it at present.
> Most of the stuff that I have done has been a bit more simple than this.
The
> algorithm works from a sample I've seen (no code just an explanation).
Start
> by shifting the most significant bit of your binary number into the least
> significant bit of your "units" bcd value, when the number in the "units"
> value is 5 or greater add 3 to it. Shift again, if the value is 5 or
greater
> add 3 to it, the values will continue to spill over to the "tens",
> "hundreds", "thousands", etc. You must add 3 to each of the bcd digits if
> any is five or greater, by the last shift (same number of shifts as your
> input binary value (in my case 20 bits)) you'll have the bcd
representation.
> The example I mentioned above was for a microcontroller.
>
> Code
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity bin2bcd is
> port(
> clk : in std_logic;
> reset : in std_logic;
> load_data : in std_logic;
> data_in : in std_logic_vector(19 downto 0);
> data_ready : out std_logic;
> data_out : out std_logic_vector(23 downto 0)
> );
> end bin2bcd;
>
> architecture behaviour of bin2bcd is
>
> signal ser_out_s : std_logic;
> signal shift_en_s : std_logic;
> signal data_ready_s : std_logic;
> signal count_s : std_logic_vector(4 downto 0);
> signal bin_in_s : std_logic_vector(19 downto 0);
> signal bcd_out_s : std_logic_vector(23 downto 0);
>
> begin
>
> process (reset, clk) begin
> if reset = '1' then
> count_s <= (others => '0');
> shift_en_s <= '0';
> data_ready_s <= '0';
> elsif rising_edge(clk) then
> if load_data = '1' then
> count_s <= (others => '0');
> shift_en_s <= '1';
> elsif count_s = "10011" then
> count_s <= (others => '0');
> shift_en_s <= '0';
> data_ready_s <= '1';
> else
> count_s <= count_s +1;
> data_ready_s <= '0';
> end if;
> end if;
> end process;
>
> process (reset, clk) begin
> if reset = '1' then
> bin_in_s <= (others => '0');
> elsif rising_edge(clk) then
> if load_data = '1' then
> bin_in_s <= data_in;
> end if;
> if shift_en_s = '1' then
> bin_in_s <= bin_in_s(18 downto 0) & '0';
> end if;
> end if;
> end process;
>
> ser_out_s <= bin_in_s(19);
>
> process (reset, clk, load_data)
>
> variable bcd_value : std_logic_vector(23 downto 0);
>
> begin
>
> if reset = '1' or load_data = '1' then
> bcd_value := (others => '0');
> elsif rising_edge(clk) then
> if shift_en_s = '1' then
> bcd_value := bcd_value(22 downto 0) & ser_out_s;
> bcd_out_s <= bcd_value;
> if bcd_value(3 downto 0) >= "0101" then
> bcd_value(3 downto 0) := bcd_value(3 downto 0) + "0011";
> end if;
> if bcd_value(7 downto 4) >= "0101" then
> bcd_value(7 downto 4) := bcd_value(7 downto 4) + "0011";
> end if;
> if bcd_value(11 downto 8) >= "0101" then
> bcd_value(11 downto 8) := bcd_value(11 downto 8) + "0011";
> end if;
> if bcd_value(15 downto 12) >= "0101" then
> bcd_value(15 downto 12) := bcd_value(15 downto 12) + "0011";
> end if;
> if bcd_value(19 downto 16) >= "0101" then
> bcd_value(19 downto 16) := bcd_value(19 downto 16) + "0011";
> end if;
> if bcd_value(23 downto 20) >= "0101" then
> bcd_value(23 downto 20) := bcd_value(23 downto 20) + "0011";
> end if;
> end if;
> end if;
> end process;
>
> process (reset, clk) begin
> if reset = '1' then
> data_out <= (others => '0');
> data_ready <= '0';
> elsif rising_edge(clk) then
> if data_ready_s = '1' then
> data_out <= bcd_out_s;
> end if;
> data_ready <= data_ready_s;
> end if;
> end process;
>
> end behaviour;
> "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
> news:GLFVa.9117$cF.3056@rwcrnsc53...
> >
> > "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
> > news:MzFVa.9078$cF.2637@rwcrnsc53...
> > >
> > > "Jason Berringer" <look_at_bottom_of@email.com> wrote in message
> > > news:kJCVa.3413$Cx4.543634@news20.bellglobal.com...
> > > > Hello, I have attached a portion of code for a binary to bcd
counter,
> 20
> > > > bits parallel input, and a 24 bit BCD output parallel. Although
> > internally
> > > > it converts it to serial to go through the conversion. I'm
attempting
> > the
> > > > shift and add three (if greater than or equal to 5) method, but I am
> > > having
> > > > some problems. It works great on the simulator (Aldec Active HDL)
and
> I
> > > can
> > > > synthesize it but when I put it on the chip I'm getting some odd
> things.
> > I
> > > > am using 16 input toggle switches and i debounced pb switch as a
load
> > > > switch, and my outputs are LEDs. When I set this up on the board my
> > > outputs
> > > > go as follows:
> > >
> > > The attachment didn't come through. Can you just include some of the
> code
> > > in the body, instead of an attachment?
> >
> > OK, it did come through but I was looking in the wrong place. Still, it
> is
> > often easier just to include it.
> >
> > I am much better at reading verilog than VHDL, but it doesn't look right
> to
> > me. Though I think I don't understand the algorithm, I think it needs
to
> be
> > more complicated than that, though if you do an iterative algorithm it
> might
> > not be so hard. How many clock cycles does it take to get the data
from
> > input to output? How many different values did you put through the
> > simulator in testing?
> >
> > -- glen
> >
> >
>
>
Article: 58745
Thanks for all of the responses, I appreciate it very much, and sorry about
the uncommented code, I usually go back when it is working and comment it
for others to understand since I know what I'm trying to do. I just forgot
that others would be reading it at this point and would require commenting.
I went back with some of the comments and put together somthing that worked
(based on the Xilinx App note by Peter) but I am going to still try and get
the add 3 method to work since I have had so much help with it. My big
problem was that I could run the simulator and get the value I was looking
for, it was just in the hardware that it was going silly.
Thanks again
Jason
"FE" <magicfe2002@yahoo.ca> wrote in message
news:AphWa.10733$s_6.88219@weber.videotron.net...
> Hi Jason,
> I found your algorithm in C (see source after the vhdl code) on the net.
> It's cool.
> I rewrited your code like this (see bellow) and it works fine (I tested):
> (bin and bcd width (20 and 24) could be replaced by constants
(C_BIN_WIDTH,
> C_BCD_WIDTH)).
> Hope this will help.
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> entity bin2bcd is
> port(
> i_clk : in std_logic;
> i_rst_an : in std_logic;
> i_load_data : in std_logic;
> i_data : in std_logic_vector(20-1 downto 0);
>
> o_data_rdy_q : out std_logic;
> o_data_q : out std_logic_vector(24-1 downto 0)
> );
> end bin2bcd;
>
> architecture rtl of bin2bcd is
> begin
> ------------------------------------------------------------------------
--
> ----
> -- register mapping:
> --
> -- ------------------------
> -- | v_bcd_bin_q |
> -- ------------------------
> -- | av_bcd_q | |
> -- ------------------------
> -- | | av_bin_q |
> -- ------------------------
> -- |xxx| 3 bits overlaps to save 3 clk cycle processing and 3
> dff
> --
> ------------------------------------------------------------------------
--
> ----
> ps_bin2bcd : process (i_rst_an, i_clk)
> variable v_cnt_q : integer range 0 to 17;
> variable v_en_shift_q : std_logic;
> variable v_data_rdy_q : std_logic;
> variable v_bcd_bin_q : unsigned(20+24-3-1 downto 0);
> alias av_bin_q : unsigned(20-1 downto 0) is v_bcd_bin_q(20-1 downto
0);
> alias av_bcd_q : unsigned(24-1 downto 0) is v_bcd_bin_q(20+24-3-1
downto
> 20-3);
> begin
> if i_rst_an = '0' then
> v_cnt_q := 0;
> v_en_shift_q := '0';
> v_bcd_bin_q := (others => '0');
> v_data_rdy_q := '0';
> elsif rising_edge(i_clk) then
> if i_load_data = '1' then
> av_bcd_q := (others => '0');
> av_bin_q := unsigned(i_data);
> v_cnt_q := 0;
> v_en_shift_q := '1';
> v_data_rdy_q := '0';
> elsif v_cnt_q = 17 then
> v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
> v_cnt_q := v_cnt_q; -- optional assignment
> v_en_shift_q := '0';
> v_data_rdy_q := '1';
> elsif v_en_shift_q = '1' then
> for i in 0 to 5 loop
> if av_bcd_q(4*i+3 downto 4*i) >= 5 then
> av_bcd_q(4*i+3 downto 4*i) := av_bcd_q(4*i+3 downto 4*i) + 3;
> end if;
> end loop;
> v_bcd_bin_q := v_bcd_bin_q sll 1;
> v_cnt_q := v_cnt_q + 1;
> v_en_shift_q := v_en_shift_q; -- optional assignment
> v_data_rdy_q := v_data_rdy_q; -- optional assignment
> else
> v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
> v_cnt_q := v_cnt_q; -- optional assignment
> v_en_shift_q := v_en_shift_q; -- optional assignment
> v_data_rdy_q := v_data_rdy_q; -- optional assignment
> end if;
> end if;
> o_data_q <= std_logic_vector(av_bcd_q);
> o_data_rdy_q <= v_data_rdy_q;
> end process;
>
> end rtl;
>
>
> **********C source code************
>
> #include <stdio.h>
> #include <stdlib.h>
> #include <conio.h>
>
> #define BIN_SIZE 4
> #define MSB_MASK 0x80000000L
> #define BCD_SIZE 13
>
> typedef unsigned long BIN;
> typedef unsigned char BCD[BCD_SIZE];
>
> main()
> {
> BIN bin1,bin;
> BCD bcd;
> int i,j,k,carry;
> char temp[9];
>
>
> printf("enter number:");
> scanf("%lu", &bin1);
> bin=bin1;
>
> for (i=0; i<= BCD_SIZE; i++) bcd[i]=0;
> printf("\n BCD BIN\n");
> for (i=0; i<8*BIN_SIZE; i++) {
> /* check for overflow */
> for (j=0; j<BCD_SIZE; j++) {
> if (bcd[j] >= 5) {
> bcd[j] += 3;
> /* printout for checking */
> for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
> printf(" %x\n", bin);
> }
> }
> /* shift right */
> carry = (bin & MSB_MASK) == MSB_MASK;
> bin = bin << 1;
> for (j=0; j<BCD_SIZE; j++) {
> bcd[j] = (bcd[j] << 1) | carry;
> carry = (bcd[j] & 0x10) == 0x10;
> bcd[j] = bcd[j] & 0xF;
> }
> /* printout for checking */
> for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
> printf(" %x\n", bin);
> }
> printf("BIN = %lu\n", bin1);
> printf("BCD = ");
> for (k=BCD_SIZE; k--; ) printf("%d", bcd[k]);
> }
>
> regards
> FE
>
>
> "Jason Berringer" <look_at_bottom_of@email.com> wrote in message
> news:IlGVa.3393$mv6.617644@news20.bellglobal.com...
> > Here is the code (after my text) instead of an attachment in case others
> > cannot read it.
> >
> > It takes (or should take) 20 to 21 clock cycles to get the data from the
> > input to the output. I put a few numbers through the simulation the only
> > correct values are 0 and 1, all other tested were incorrect. I'm pretty
> sure
> > it's a simple error that I'm not catching, I just can't see it at
present.
> > Most of the stuff that I have done has been a bit more simple than this.
> The
> > algorithm works from a sample I've seen (no code just an explanation).
> Start
> > by shifting the most significant bit of your binary number into the
least
> > significant bit of your "units" bcd value, when the number in the
"units"
> > value is 5 or greater add 3 to it. Shift again, if the value is 5 or
> greater
> > add 3 to it, the values will continue to spill over to the "tens",
> > "hundreds", "thousands", etc. You must add 3 to each of the bcd digits
if
> > any is five or greater, by the last shift (same number of shifts as your
> > input binary value (in my case 20 bits)) you'll have the bcd
> representation.
> > The example I mentioned above was for a microcontroller.
> >
> > Code
> >
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_unsigned.all;
> >
> > entity bin2bcd is
> > port(
> > clk : in std_logic;
> > reset : in std_logic;
> > load_data : in std_logic;
> > data_in : in std_logic_vector(19 downto 0);
> > data_ready : out std_logic;
> > data_out : out std_logic_vector(23 downto 0)
> > );
> > end bin2bcd;
> >
> > architecture behaviour of bin2bcd is
> >
> > signal ser_out_s : std_logic;
> > signal shift_en_s : std_logic;
> > signal data_ready_s : std_logic;
> > signal count_s : std_logic_vector(4 downto 0);
> > signal bin_in_s : std_logic_vector(19 downto 0);
> > signal bcd_out_s : std_logic_vector(23 downto 0);
> >
> > begin
> >
> > process (reset, clk) begin
> > if reset = '1' then
> > count_s <= (others => '0');
> > shift_en_s <= '0';
> > data_ready_s <= '0';
> > elsif rising_edge(clk) then
> > if load_data = '1' then
> > count_s <= (others => '0');
> > shift_en_s <= '1';
> > elsif count_s = "10011" then
> > count_s <= (others => '0');
> > shift_en_s <= '0';
> > data_ready_s <= '1';
> > else
> > count_s <= count_s +1;
> > data_ready_s <= '0';
> > end if;
> > end if;
> > end process;
> >
> > process (reset, clk) begin
> > if reset = '1' then
> > bin_in_s <= (others => '0');
> > elsif rising_edge(clk) then
> > if load_data = '1' then
> > bin_in_s <= data_in;
> > end if;
> > if shift_en_s = '1' then
> > bin_in_s <= bin_in_s(18 downto 0) & '0';
> > end if;
> > end if;
> > end process;
> >
> > ser_out_s <= bin_in_s(19);
> >
> > process (reset, clk, load_data)
> >
> > variable bcd_value : std_logic_vector(23 downto 0);
> >
> > begin
> >
> > if reset = '1' or load_data = '1' then
> > bcd_value := (others => '0');
> > elsif rising_edge(clk) then
> > if shift_en_s = '1' then
> > bcd_value := bcd_value(22 downto 0) & ser_out_s;
> > bcd_out_s <= bcd_value;
> > if bcd_value(3 downto 0) >= "0101" then
> > bcd_value(3 downto 0) := bcd_value(3 downto 0) + "0011";
> > end if;
> > if bcd_value(7 downto 4) >= "0101" then
> > bcd_value(7 downto 4) := bcd_value(7 downto 4) + "0011";
> > end if;
> > if bcd_value(11 downto 8) >= "0101" then
> > bcd_value(11 downto 8) := bcd_value(11 downto 8) + "0011";
> > end if;
> > if bcd_value(15 downto 12) >= "0101" then
> > bcd_value(15 downto 12) := bcd_value(15 downto 12) + "0011";
> > end if;
> > if bcd_value(19 downto 16) >= "0101" then
> > bcd_value(19 downto 16) := bcd_value(19 downto 16) + "0011";
> > end if;
> > if bcd_value(23 downto 20) >= "0101" then
> > bcd_value(23 downto 20) := bcd_value(23 downto 20) + "0011";
> > end if;
> > end if;
> > end if;
> > end process;
> >
> > process (reset, clk) begin
> > if reset = '1' then
> > data_out <= (others => '0');
> > data_ready <= '0';
> > elsif rising_edge(clk) then
> > if data_ready_s = '1' then
> > data_out <= bcd_out_s;
> > end if;
> > data_ready <= data_ready_s;
> > end if;
> > end process;
> >
> > end behaviour;
> > "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
> > news:GLFVa.9117$cF.3056@rwcrnsc53...
> > >
> > > "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
> > > news:MzFVa.9078$cF.2637@rwcrnsc53...
> > > >
> > > > "Jason Berringer" <look_at_bottom_of@email.com> wrote in message
> > > > news:kJCVa.3413$Cx4.543634@news20.bellglobal.com...
> > > > > Hello, I have attached a portion of code for a binary to bcd
> counter,
> > 20
> > > > > bits parallel input, and a 24 bit BCD output parallel. Although
> > > internally
> > > > > it converts it to serial to go through the conversion. I'm
> attempting
> > > the
> > > > > shift and add three (if greater than or equal to 5) method, but I
am
> > > > having
> > > > > some problems. It works great on the simulator (Aldec Active HDL)
> and
> > I
> > > > can
> > > > > synthesize it but when I put it on the chip I'm getting some odd
> > things.
> > > I
> > > > > am using 16 input toggle switches and i debounced pb switch as a
> load
> > > > > switch, and my outputs are LEDs. When I set this up on the board
my
> > > > outputs
> > > > > go as follows:
> > > >
> > > > The attachment didn't come through. Can you just include some of
the
> > code
> > > > in the body, instead of an attachment?
> > >
> > > OK, it did come through but I was looking in the wrong place. Still,
it
> > is
> > > often easier just to include it.
> > >
> > > I am much better at reading verilog than VHDL, but it doesn't look
right
> > to
> > > me. Though I think I don't understand the algorithm, I think it needs
> to
> > be
> > > more complicated than that, though if you do an iterative algorithm it
> > might
> > > not be so hard. How many clock cycles does it take to get the data
> from
> > > input to output? How many different values did you put through the
> > > simulator in testing?
> > >
> > > -- glen
> > >
> > >
> >
> >
>
>
Article: 58746I have inherited a project developed with Handle-C. My initial impressions of the language are good. Handle-C has a well thought out development environment which includes a debugger that supports parallel execution of statements (the debugger identifies all statements that will execute each clock cycle). Previous threads on this subject have raised doubts about turning programmers into engineers (I am an engineer), but I think this misses the point. Developers aren't likely to pay $25K for Handle-C to design a UART, although you could. Most likely they are interested in a problem that is much more complex. In our case it involves real-time image processing of two cameras attached to FRET confocal microscope. A Xilinx XC2V6000 does image coadding, distortion correction and registration. The code runs for a couple hundred pages. Have you looked at VHDL code for a simple counter? The best (short) response I found in favor of this kind of tool is that it manages complexity. I don't have enough experience to judge how much more logic would be required to implement an algorithm in Handle-C versus VHDL, if any. I do believe that you can significantly reduce development time.Article: 58747
Peter Alfke <peter@xilinx.com> wrote: >> 12.5ns jitter on 21.48MHz means complete cycles will be missed so it is >> fundamentally not allowable. >Clever, clever... I just thought it worth emphasising a fundamental flaw in the OPs thinking. You cant generate a signal higher than half the DDS clock - nyquist or whatever. >But a few lines further down I suggested ways to reduce it to 0.3 ns.... So you take an 8 phase clock and run a DDS from each phase. Each DDS is initialised with 1/8th more of the phase increment than the last. You sum the MSB of each phase accumulator (with carefully matched delays) and the MSB of the sum is the generated clock. Is that how it works? I would have to think about that to convince myself it works. Sounds a bit tricky to implement also.Article: 58748
Kolja Sulimma wrote: > > Peter Alfke <peter@xilinx.com> wrote in message news:<3F1F1F1A.C5C50F9E@xilinx.com>... > > Your question can best be answered by a Xilinx salesperson, or most > > likely a Sales Representative. If they cannot get you the answer > > dirctly, they contact the factory. > > They will love to talk to you and give you a quote with "budgetary > > figures". They really are your friend, because they have a vested > > interest to make you succeed. That is the only way they will get paid. > > Peter, > unfortunately this is not entirely correct. > You are right if you talk about small companies talking to small > distributors or large companies talking to large distributors. > But if you are a small company talking to a large distributor - and > xilinx uses only the largest distributors - than the distributor is > your enemy. > At least I had the feeling during my last couple of calls to > distributors. > > A few weeks ago I send out a request for quotes for 100 pieves XC2S200 > to all european xilinx distributors and got a single response! > > When XC2S was really new I asked Xilinx UK for samples. They did a > search in some stock database an pointed me to Insight Munich who had > a few parts in stock. But Insight simply denied that. "No Stock" was > their answer. After calling three people at Xilinx in three countries > and calling insight again and again finally sample stock magically > apeared in munich exactly in the quantity that Xilinx hat told me. > > Please Xilinx: > Hire some small, independant distributor in europe that is willing to > talk to people who place orders that are worth just a few thousand > dollars. > > To answer the original question: > For quantities below 100 the prices never dropped in the past by more > than a few percent. But there appeared new parts that are cheaper. > > Kolja Sulimma I can't say anything about distribution in Europe. But here in Maryland, I can not complain at all about the level of support and cooperation I am getting on both pricing and technical issues. I do find however, that it often requires meeting the sales people face to face and letting them in on your hopes, plans and fears. You don't have to give away the company jewels in terms of detail. But the vendors need a certain amount of information from you to be able to go back to the manufacturers and get the pricing you want. I just made a decision to use the Spartan 3 in my current design because my Nuhorizons sales person did not give up on me and brought in the local sales rep who had enough pull with Xilinx to get me the price I needed. I understand that engineers are loath to "play the game", but it is not really a hard game to play. Basically you need to give up your expectations of getting an immediate answer to pricing requests and keep working it until they give you what you need (assuming it is reasonable). It also does not hurt to have competitive bids on similar parts :). BTW, my pricing is at 100 pieces (or maybe 250). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58749
> > Once you go through that book, a more thorough reference on the VHDL itself > > would be useful to flush out your knowledge of the complete language. > > I am quite sure I will play on your good nature further and ask for > advice at that point! I'll suggest something now -- someone at work pointed me to the book "HDL Chip Design" by Douglas J. Smith. I don't think its a good introductory text toHDLs or digital design, but a great second book/cookbook/reference. Every example in it gives VHDL *and* Verilog code side-by-side, and explains as it goes along the differernces between the two. This is very handy if you know one and not the other. It also discusses many of the features of both languages with very good examples. After looking at it today, I understand variables mixed with signals in a process as best as I ever will until I find the time to get intimate with a simulator... Regards, Paul Leventis Altera Corp.
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