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hi , I have 2 major doubts. The first one is whether Spartan 2 or Spartan 2E support partial reconfiguration. The second one is about the S/W support for partial reconfiguration.Is there any support from XIlinx's Impact software to implement and verify the same. If not how would I go about implementing one. Your answers to the above would be immensely helpful. Thanks, Sriram AnandArticle: 58601
Does anyone have any experience with this board, with or without Linux? Thank you.Article: 58602
Hi im unable to comprehend this error inspite of the help given inthe solution board.....im using ISE 5.2 version ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: BUF symbol "iobuf_6/IBUF" (Output Signal = dip_i<2>) TBUF symbol "iobuf_6/OBUFT" (Control Signal = dip_t<2>) PAD symbol "dip<2>" (Pad Signal = dip<2>) PULL symbol "dip<2>_PULLUP" (Output Signal = dip<2>) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "dip<2>" (LOC=AB9) Please correct the constraints accordingly. ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: BUF symbol "iobuf_7/IBUF" (Output Signal = dip_i<3>) TBUF symbol "iobuf_7/OBUFT" (Control Signal = dip_t<3>) PAD symbol "dip<3>" (Pad Signal = dip<3>) PULL symbol "dip<3>_PULLUP" (Output Signal = dip<3>) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "dip<3>" (LOC=AB8) Please correct the constraints accordingly. Problem encountered during the packing phase. can anyone help me on this. ParaagArticle: 58603
I have never encountered these messages before, but from them, it looks like you are trying to pack an input buffer (IBUF) and a tristateable output buffer (OBUFT) into the same IOB; specifying the same LOC constraint on the IBUF and the OBUFT. If this is the case, then you should be using an IOBUF instead of the IBUF and OBUFT. Avrum "paraag" <paraagv@hotmail.com> wrote in message news:39fdcd07.0307281130.1d418106@posting.google.com... > Hi > im unable to comprehend this error inspite of the help given inthe > solution board.....im using ISE 5.2 version > > ERROR:Pack:1107 - Unable to combine the following symbols into a > single IOB > component: > BUF symbol "iobuf_6/IBUF" (Output Signal = dip_i<2>) > TBUF symbol "iobuf_6/OBUFT" (Control Signal = dip_t<2>) > PAD symbol "dip<2>" (Pad Signal = dip<2>) > PULL symbol "dip<2>_PULLUP" (Output Signal = dip<2>) > Each of the following constraints specifies an illegal physical > site for a > component of type IOB: > Symbol "dip<2>" (LOC=AB9) > Please correct the constraints accordingly. > ERROR:Pack:1107 - Unable to combine the following symbols into a > single IOB > component: > BUF symbol "iobuf_7/IBUF" (Output Signal = dip_i<3>) > TBUF symbol "iobuf_7/OBUFT" (Control Signal = dip_t<3>) > PAD symbol "dip<3>" (Pad Signal = dip<3>) > PULL symbol "dip<3>_PULLUP" (Output Signal = dip<3>) > Each of the following constraints specifies an illegal physical > site for a > component of type IOB: > Symbol "dip<3>" (LOC=AB8) > Please correct the constraints accordingly. > Problem encountered during the packing phase. > > can anyone help me on this. > ParaagArticle: 58604
"Marc Randolph" <mrand@my-deja.com> wrote in message news:15881dde.0307280821.fba8a71@posting.google.com... (snip) > > I am not sure why it is that way, but it is. I don't completely understand > > the process for generating primitive polynomials. My understanding is that > > it gets harder as they get bigger. It might be that someone found some > > relatively simple large ones that work well enough. > > I suspect that is the case. > > http://www.cs.ucl.ac.uk/staff/d.jones/crcnote.pdf > > discusses how the "sparse" 64-bit polynomial produced an abnormally > high rate of collisions when used as a simple hash. Yes, I know it > even a "good" CRC isn't really a good hash function, but that seem to > be what they were using it as. Some years ago I was using it for a DNA hash function. Since EMBL had already used it, I decided to use it, too. Though even with the results they have, it is significantly better than CRC32. Because of the sparse ones it was very easy to implement using 32 bit arithmetic, which I considered an advantage. -- glenArticle: 58605
Hi, I checked the "Pin Compatibility tool" of xilinx for the spartan IIE http://www.xilinx.com/applications/web_ds_sp2e/pin_comp/ When I compare the 300E with the 600E in FG456 package then I got a few mismatches. Pins that are "NC" for 300E and should be either GND or VCCINT for the 600E type. The design did not anticipate for the 600E so the "NC's" are really not connected. Can someone tell me if this will be a problem? Thanks, R_edArticle: 58606
Hi Peter, Speaking of configuration, can I bug you about data sheets? I really want to design in an XCF16P, but I can't find the data sheet. The link provided gets you a PDF that stops at XCF04P. (Different package and everything. ;) Or is the part not "real" yet? Thanks, Gary g w helbig -at- yahoo -dot- com On Mon, 28 Jul 2003 09:17:28 -0700, Peter Alfke <peter@xilinx.com> wrote: >Michael, what do you mean by interface? Read the data sheet, and it >tells you that you have to input a serial bitstream, and you can store >this in many ways. The "interface" is the simplest possible, a data line >and a clock. >Peter Alfke, Xilinx > >Michael Petry wrote: >> >> Hello, >> I'm looking for a programing interface (cheap, selfmade)for a xilinx FPGA >> (e.g. XCS10-3). Does anybody know some links for a interface? >> Thanks >> MichaelArticle: 58607
Two options I can think of: I see JTAG programmers on eBay for $15. Search for Xilinx or Altera; the JTAG interfaces are compatable. I program my spartan with I/O bits on the CPU (that just happens to be on the card). It's not that tough. 20 lines of PERL to convert the bit file, and another 20 lines of assembler to move it out to the chip. Gary. g w helbig -at- yahoo -dot- com On Mon, 28 Jul 2003 14:13:39 +0200, Michael Petry <micpetry@web.de> wrote: > >Hello, > I'm looking for a programing interface (cheap, selfmade)for a xilinx FPGA >(e.g. XCS10-3). Does anybody know some links for a interface? > Thanks > Michael >Article: 58608
Also make sure that the specified pin is legal. For example, you can't define an output on a global clock input pin. Avrum wrote: > I have never encountered these messages before, but from them, it looks like > you are trying to pack an input buffer (IBUF) and a tristateable output > buffer (OBUFT) into the same IOB; specifying the same LOC constraint on the > IBUF and the OBUFT. If this is the case, then you should be using an IOBUF > instead of the IBUF and OBUFT. > > Avrum > > "paraag" <paraagv@hotmail.com> wrote in message > news:39fdcd07.0307281130.1d418106@posting.google.com... > >>Hi >>im unable to comprehend this error inspite of the help given inthe >>solution board.....im using ISE 5.2 version >> >>ERROR:Pack:1107 - Unable to combine the following symbols into a >>single IOB >> component: >> BUF symbol "iobuf_6/IBUF" (Output Signal = dip_i<2>) >> TBUF symbol "iobuf_6/OBUFT" (Control Signal = dip_t<2>) >> PAD symbol "dip<2>" (Pad Signal = dip<2>) >> PULL symbol "dip<2>_PULLUP" (Output Signal = dip<2>) >> Each of the following constraints specifies an illegal physical >>site for a >> component of type IOB: >> Symbol "dip<2>" (LOC=AB9) >> Please correct the constraints accordingly. >>ERROR:Pack:1107 - Unable to combine the following symbols into a >>single IOB >> component: >> BUF symbol "iobuf_7/IBUF" (Output Signal = dip_i<3>) >> TBUF symbol "iobuf_7/OBUFT" (Control Signal = dip_t<3>) >> PAD symbol "dip<3>" (Pad Signal = dip<3>) >> PULL symbol "dip<3>_PULLUP" (Output Signal = dip<3>) >> Each of the following constraints specifies an illegal physical >>site for a >> component of type IOB: >> Symbol "dip<3>" (LOC=AB8) >> Please correct the constraints accordingly. >>Problem encountered during the packing phase. >> >>can anyone help me on this. >>Paraag > > > -- Marc Guardiani To reply directly to me, use the address given below. The domain name is phonetic. fpgaee81-at-eff-why-eye-dot-netArticle: 58609
Hi,
I've been unable to determine looking in the datasheet what is the
fastest an output pin can switch on a Xilinx Spartan IIE. Info appreciated.
thx
Article: 58610> How specific to Altera is this book? Not at all. It ships with MaxPlus II (or maybe Quartus in the newer editions?) and occasionally gives tutorials or examples that can be done in the CAD tool. But the vast majority of the text and VHDL examples use only the IEEE libraries. One place where an Altera-specific reference would be made (for example) is when describing the capabilities of CAD tools, such as parameterized modules (in this case, Altera's LPMs such as lpm_add_sub, etc). The concepts are portable to other tools. Looking through the book again for the first time in a few years, my take on it is that it is first a book about digital design (intro to digitial logic, arithmetic techniques, FSMs, etc.) and only an intro to VHDL, with the most useful/basic subset of the language introduced. Once you go through that book, a more thorough reference on the VHDL itself would be useful to flush out your knowledge of the complete language. And a more advanced textbook on particular areas of digital design (such as arithmetic) may be needed. Regards, Paul Leventis Altera Corp.Article: 58611
Hi Roel: in my experience, this will be a problem - if it's not in a bga, you should be able to pull acceptable rework with good results until you can spin the board. Andrew Roel wrote: >Hi, > >I checked the "Pin Compatibility tool" of xilinx for the spartan IIE >http://www.xilinx.com/applications/web_ds_sp2e/pin_comp/ > >When I compare the 300E with the 600E in FG456 package then I got >a few mismatches. Pins that are "NC" for 300E and should be either GND >or VCCINT for the 600E type. The design did not anticipate for the >600E so the "NC's" are really not connected. Can someone tell me if >this will be a problem? > >Thanks, >R_ed > >Article: 58612
Jon Masters wrote: > > Hi, > > I am after a book with a title something along the lines of > > ``VHDL for Software Engineers'' > > Finding a suitable book seems pretty challenging as most assume either > the reader is an experienced electrical engineer or that they are a > complete novice coming in. I have years of Computer Science background > and am trying to become more aquainted with the actual hardware design. > > FWIW the Linux port I mentioned before has now progressed further and I > am in the process of adding support for various Xilinx devices. > > Jon. I see you have gotten a lot of recomendations that don't really address your question. If you are a software engineer and are not familiar with hardware design, I recommend that you start with some good books on hardware before you try to master a hardware desciption language. My observations have been that you will not do well with hardware desciption languages if you don't understand the hardware you want to describe. I personally think that too many engineers try to write in HDL in similar ways to writing software. The two are very different and have little in common. You can write an HDL program in a similar manner to software, but you will often get a very inefficient implementation and it is very likely that the design will not work well if you do not observe many rules of hardware design that have nothing to do with the HDL. I can't recommend a good starter book in hardware design since all of the books I read are quite old and most were not very good as a beginner's book. Perhaps someone else can recommend a good book for teaching hardware design to a software person? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58613
"Gaby Jay" <gabsterblue@hotmail.com> wrote in message news:<ECkVa.12678$vB6.409940@weber.videotron.net>... > Hi, > > I've been unable to determine looking in the datasheet what is the > fastest an output pin can switch on a Xilinx Spartan IIE. Info appreciated. > > thx The reason you where not able to determine this is probably because it is a function of the pin loading and output duffer size. You have to look a bit closer through the tables in the data sheet, select an output buffer type, strength and then calculate the max delay for a given load. Regards, rudi -------------------------------------------------------- www.asics.ws --- Solutions for your ASIC/FPGA needs --- ----------------- FPGAs * Full Custom ICs * IP Cores --- FREE IP Cores --> http://www.asics.ws/ <-- FREE IP CoresArticle: 58614
I am designing QAM chip.
I want know hardware for 2's complement parallel multiplier(12bit by 12 bit).
can any body know plz help me.
Thank you and best regards.
prasad
Article: 58615"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F25F197.818731BA@yahoo.com... > Jon Masters wrote: > > I am after a book with a title something along the lines of > > ``VHDL for Software Engineers'' > > Finding a suitable book seems pretty challenging [...] > I see you have gotten a lot of recomendations that don't really address > your question. If you are a software engineer and are not familiar with > hardware design, I recommend that you start with some good books on > hardware before you try to master a hardware desciption language. My > observations have been that you will not do well with hardware > desciption languages if you don't understand the hardware you want to > describe. Too true. > I personally think that too many engineers try to write in HDL in > similar ways to writing software. The two are very different and have > little in common. This I'm less sure about. It is certainly true that some people try to slide straight from software into designing hardware, and spectacularly miss the point. But it is also true that many hardware engineers miss the opportunity to learn from software techniques when writing VHDL. This is especially true when creating non-synthesisable code, for test benches or component modelling. > You can write an HDL program in a similar manner to > software, but you will often get a very inefficient implementation and > it is very likely that the design will not work well if you do not > observe many rules of hardware design that have nothing to do with the > HDL. Again, if you are trying to create synthesisable hardware, this is entirely true. And to return to the question... I quite like Mark Zwolinski's book "Digital System Design with VHDL" (Prentice-Hall). It's aimed at undergraduates but it's very clear and good to read, and quite focused about what does and doesn't make sensible hardware. If you are really interested in creating hardware, you may also care to look at Andrew Rushton's "VHDL for Logic Synthesis" (Wiley); personally I like the style, and it's particularly good on design for synthesis. If you are a real software person, with a good background in computer science, then you probably need to know a few things that they don't usually tell you in beginners' VHDL books. - Never, never forget that hardware is a STATICALLY DETERMINED network of heterogeneous, fine-grained processing elements which typically fall into two categories: combinational (output is a pure function of the inputs, delay is short(ish) compared with the system clock period) and register (output captures a new value on the active edge of the system clock, then holds it until the next active edge). If you try to do anything that implies a dynamically varying network of processes, synthesis will need to map it on to a specific static network which is likely to be very inefficient. - VHDL is built around a discrete-event simulation model. However, it's commonly used to create cycle-based, clock-synchronous systems. Getting from one paradigm to the other requires the application of some discipline so that all the hardware you create matches the synchronous model. Find out about "synthesis templates". - You can write ordinary procedural software in VHDL if you wish, but you only get real value out of VHDL if you use it to create a network of interacting processes. - VHDL is strongly typed, and obsessive about static compile-time checks. This often leads to what many perceive to be excessive verbosity. - VHDL uses a library-based mechanism of compilation that follows Ada's model. This is really important if you are using a simulator; it's less troublesome for synthesis, because most synthesis tools recompile everything from source every time they run. Enjoy, -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 58616
Virtex-E highest speed is capable of 622MB/s data transfer in LVDS DDR mode those clock is running at 311MHz if the S2E speed grade -7 has similar AC characteristics as VirtexE -7 then the answer to your question would be 'just above 300MHz' but sure it all depends on the load and standard selected. antti russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0307282157.47edf1a6@posting.google.com>... > "Gaby Jay" <gabsterblue@hotmail.com> wrote in message news:<ECkVa.12678$vB6.409940@weber.videotron.net>... > > Hi, > > > > I've been unable to determine looking in the datasheet what is the > > fastest an output pin can switch on a Xilinx Spartan IIE. Info appreciated. > > > > thx > > > The reason you where not able to determine this is > probably because it is a function of the pin loading > and output duffer size. You have to look a bit closer > through the tables in the data sheet, select an output > buffer type, strength and then calculate the max delay > for a given load. > > Regards, > rudi > -------------------------------------------------------- > www.asics.ws --- Solutions for your ASIC/FPGA needs --- > ----------------- FPGAs * Full Custom ICs * IP Cores --- > FREE IP Cores --> http://www.asics.ws/ <-- FREE IP CoresArticle: 58617
We got a ball park cost for our timeframe and volume. I should have said this up front. Yeah- I knew it would be a wild guess- the drop in the price of processor is probably a safe model to follow. Thanks to everyone- including the vendors---- MSArticle: 58618
All, Please take advantage of the fact that we have IBIS models, and there are IBIS simulators out there! Any such question can be easily answered by simulating the IO standard, the pcb traces, and the loading at the end of the traces. If you need a "what if" answer, you may open a case with our hotline, but you need to state: - the io standard - the pcb trace lengths/impedances/topology - the load (IBIS models of the load - where are they if they are not Xilinx models) - SDR or DDR Austin Antti Lukats wrote: > Virtex-E highest speed is capable of 622MB/s data transfer in LVDS DDR mode > those clock is running at 311MHz > if the S2E speed grade -7 has similar AC characteristics as VirtexE -7 > then the answer to your question would be 'just above 300MHz' > > but sure it all depends on the load and standard selected. > > antti > > russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0307282157.47edf1a6@posting.google.com>... > > "Gaby Jay" <gabsterblue@hotmail.com> wrote in message news:<ECkVa.12678$vB6.409940@weber.videotron.net>... > > > Hi, > > > > > > I've been unable to determine looking in the datasheet what is the > > > fastest an output pin can switch on a Xilinx Spartan IIE. Info appreciated. > > > > > > thx > > > > > > The reason you where not able to determine this is > > probably because it is a function of the pin loading > > and output duffer size. You have to look a bit closer > > through the tables in the data sheet, select an output > > buffer type, strength and then calculate the max delay > > for a given load. > > > > Regards, > > rudi > > -------------------------------------------------------- > > www.asics.ws --- Solutions for your ASIC/FPGA needs --- > > ----------------- FPGAs * Full Custom ICs * IP Cores --- > > FREE IP Cores --> http://www.asics.ws/ <-- FREE IP CoresArticle: 58619
Jonathan Bromley wrote:
> This I'm less sure about. It is certainly true that some people try to
> slide straight from software into designing hardware, and spectacularly
> miss the point. But it is also true that many hardware engineers miss
> the opportunity to learn from software techniques when writing VHDL.
> This is especially true when creating non-synthesisable code, for
> test benches or component modelling.
Well said.
Some of that computer science stuff
can be applied to synthesis as well.
References to constant data structures or
well named functions can replace
"magic numbers" in synth code.
Recurring sets of sequential statements
can be replaced with a procedure.
-- Mike Treseler
Article: 58620> BTW, what is the difference between academic and industrial research ? > About $75K/year. If you just want to see what the hot research topics are go to http://fccm.org and http://fpl.org . Also http://fpga.org has lots of info as well as http://www.optimagic.com SteveArticle: 58621
Steve, Good one. I always thought the difference was between generating degrees, and generating $$$ (both useful and necessary). Austin Steve Casselman wrote: > > BTW, what is the difference between academic and industrial research ? > > > About $75K/year. > > If you just want to see what the hot research topics are go to > http://fccm.org and http://fpl.org . > Also http://fpga.org has lots of info as well as http://www.optimagic.com > > SteveArticle: 58623
Hi, I entirely agree. The way you teach hardware design to a software person should be the same way you teach it to an EE undergraduate. I would think any introductory digital design text would be a good start, there is one by M. Morris Mano, and another by John F. Wakerly. There are, no doubt, countless others. Amazon might be a good place to start looking. Eric rickman wrote: > > Jon Masters wrote: > > > > Hi, > > > > I am after a book with a title something along the lines of > > > > ``VHDL for Software Engineers'' > > > > Finding a suitable book seems pretty challenging as most assume either > > the reader is an experienced electrical engineer or that they are a > > complete novice coming in. I have years of Computer Science background > > and am trying to become more aquainted with the actual hardware design. > > > > FWIW the Linux port I mentioned before has now progressed further and I > > am in the process of adding support for various Xilinx devices. > > > > Jon. > > I see you have gotten a lot of recomendations that don't really address > your question. If you are a software engineer and are not familiar with > hardware design, I recommend that you start with some good books on > hardware before you try to master a hardware desciption language. My > observations have been that you will not do well with hardware > desciption languages if you don't understand the hardware you want to > describe. > > I personally think that too many engineers try to write in HDL in > similar ways to writing software. The two are very different and have > little in common. You can write an HDL program in a similar manner to > software, but you will often get a very inefficient implementation and > it is very likely that the design will not work well if you do not > observe many rules of hardware design that have nothing to do with the > HDL. > > I can't recommend a good starter book in hardware design since all of > the books I read are quite old and most were not very good as a > beginner's book. Perhaps someone else can recommend a good book for > teaching hardware design to a software person? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58624
Hi, Can I decide the address of some variables in the SRAM of Altera Cyclone Development board? In which way I can reserve an area for them, from my Nios C code? Tanks Salvo
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