Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"ykagarwal" <yog_aga@yahoo.co.in> wrote in message news:4d05e2c6.0309090919.261490a1@posting.google.com... > would like to know which is the best algorithm to > make a pipelined divider in hardware. newton raphson, > goldshmit .. srt(is it possible?) > if i have space as much as to have as much as 5 radix-4 > srt dividers in a xilinx v2 fpga.. Pipelined dividers have been used on machines like the IBM 360/91 and the Cray-1, and are well described in pipelined computer architecture books for many years after those machines were built. Though in both cases they are used for floating point, where the requirements are different. The 360/91, for example, rounds the low bit instead of truncating as the architecture specifies, and would be usual in fixed point. I don't know how hard that would be to change. -- glenArticle: 60276
Austin Lesea wrote: > So what is wrong with telling folks that fixing metastability is a > myth and waste of time? > > It is similar to the patent office not considering perpetual motion > machines. > > The basic physics of it is well understood, and that is that..... > > Austin > > Tim wrote: > >> Luiz Carlos wrote: >>>> Peter Alfke, just back from Lisbon. >>>> I gladly missed all the discussions on how to "eliminate" >>>> metastability. What a waste of engineering effort and internet >>>> bandwidth... >>> >>> Peter, se você quiser, nós podemos rediscutir o assunto. Que tal >>> começarmos pelas figuras enviadas pelo Philip? >>> >>> Luiz Carlos >> >> Le mot juste... Whoops. Just playing with words. I have no real idea what Luiz said. Faux pas, hein? Nil desperandum. C'est la vie. Che sera sera. (quoted from an old Stoppard play)Article: 60277
Hi Whenever I try to map an EDK simulation after exporting it to Project Navigator ISE 5.2 version, i get this error for a microblaze system. Can someone help me with this thanx Paraag ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=mblaze, RLOC=R-15C10.S1) which require the combination of the following symbols into a single SLICE component: FLOP symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/i_abus_dff" (Output Signal = _n0099<30>) MUXCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/muxcy_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/muxcy_i/O) LUT symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/i_alu_lut" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/alu_addsub) XORCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/xor_i" (Output Signal = d_lmb_lmb_abus<1>) MULTAND symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/mult_and_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/di) MUXCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/pre_muxcy_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/pre_muxcy_i/O) The settings of the two configuration muxes CY0F and CY0G don't agree. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=mblaze, RLOC=R-16C10.S1) which require the combination of the following symbols into a single SLICE component: FLOP symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/i_abus_dff" (Output Signal = _n0099<31>) MUXCY symbol "mblaze/microblaze_0_i/decode_i/new_carry_muxcy" (Output Signal = mblaze/microblaze_0_i/decode_i/new_carry_muxcy/O) XORCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/xor_i" (Output Signal = d_lmb_lmb_abus<0>) LUT symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/i_alu_lut_2" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/alu_addsub) MULTAND symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/mult_and_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/di) MUXCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/muxcy_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/muxcy_i/O) The settings of the two configuration muxes CY0F and CY0G don't agree. Please correct the design constraints accordingly. Problem encountered during the packing phase.Article: 60278
Sorry, Luiz. I can handle German, French, Italian and Scandinavian. But Spanish and Portuguese are not my forte... What is it you want to discuss? Peter Luiz Carlos wrote: > > > Peter Alfke, just back from Lisbon. > > I gladly missed all the discussions on how to "eliminate" metastability. > > What a waste of engineering effort and internet bandwidth... > > Peter, se você quiser, nós podemos rediscutir o assunto. Que tal > começarmos pelas figuras enviadas pelo Philip? > > Luiz CarlosArticle: 60279
In article <3F5E22C2.78DCFDF0@xilinx.com>, Austin Lesea <Austin.Lesea@xilinx.com> wrote: >So what is wrong with telling folks that fixing metastability is a myth >and waste of time? I see why metastability can't be detected or corrected within the digital domain, but I still don't quite understand why metasability can't be detected in the ANALOG domain and then corrected after a FIXED (rather than exponentially decaying probability) time-window after the clock cycle to be forced into one of the stable states. Someone care to explain in simple words for an idiot like me? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 60280
James wrote: > Hi all, > I have managed to get the Xilinx command line tools running on linux > under wine, however last night while trying to program my device I hit > a bit of a wall. After reading the archives of this group, I see that > that the iMPACT tool won't run under linux. > > I have a home made parallel III cable and am trying to program an > XC9536 CPLD. > > How are other people doing this? > > Thanks so much for any help/advice you can provide, > regards, > James Fitzsimons We wrote a SVF player for our Chameleon POD. We have ported this SVF Player on Linux two weeks ago, and it works well. (SVF Player is a script placed in our Chameleon Programmer software www.amontec.com/chameleon.shtml) I need to check with my Team if we can play with XC9536 CPLD. So, if you really need a Linux solution, we can have a SVF solution. Contact me directly for more on this issue. Larry www.amontec.com ------------ And now a word from our sponsor ------------------ Want to have instant messaging, and chat rooms, and discussion groups for your local users or business, you need dbabble! -- See http://netwinsite.com/sponsor/sponsor_dbabble.htm ----Article: 60282
If I register all my signals in the IOB and use the global clock, why is the clock to out different on different outputs? Why does my clock to out vary from compile to compile? clock to out ranges 4.664ns to 5.355ns Is this just skew in the global clock? Can it be controlled with constraints? I am using Synplify 7.2, XST 5.2.03, Win2K SP4, XCV1000E-6FG860C Alan Nishioka alann@accom.comArticle: 60283
Does anybody have experience/knowledge of the real consequences of powering up: 1) The 1.8V supply faster than 5ms 2) and after the 3.3V I/O has been powered. i.e. do they have to be ramped together? We have a board redesign in process and would like to get it right, but controlled ramping will expand the board size beyond our presently acceptable limits.Article: 60284
JP On a sunny day (08 Sep 2003 22:26:38 +0200) it happened Petter Gustad <newsmailcomp5@gustad.com> wrote in <87smn79gch.fsf@zener.home.gustad.com>: You have to learn >A: Because it messes up the order in which people normally read text. >Q: Why is top-posting such a bad thing? >A: Top-posting. and to read all lines at the same time. >Q: What is the most annoying thing on usenet and in e-mail? to think in parallel,Article: 60286
You can read the answer on the Xilinx website in TechXclusives of Jan 2003:
Here are the relevant line:
Introduction
We receive many questions about I/O behavior under special
circumstances, such as before and during configuration, after
configuration if one Vcc is removed, or if the pin is pulled lower than
ground or higher than Vcco.
The cases of interest are:
1.Powering up
2.Before and during configuration
3.Normal operation after configuration has been completed.
4.Losing Vcco
The answer to these questions is made more complicated by the subtle
differences between the following
Virtex‚ and Spartan-II‚ sub-families:
Virtex‚ and Spartan-II‚
Virtex-E‚ and Spartan-IIE‚ (with small differences for Virtex-E between
8-inch and 12-inch foundries)
Virtex-II‚ and Virtex-II‚ ES
Virtex-II Pro‚ and Virtex-II Pro‚ ES
In the very beginning (V, V-E, S-II, and S-IIE devices)
While power is first applied, all I/Os are put into a 3-state condition
for any sequence of Vccint, and Vcco. There are no power-sequencing
requirements.
There is a special case only for Virtex-E devices that are marked with
0707 after the speed/temperature designation: On these Virtex-E devices
the supply voltages should be sequenced such that Vccint comes up first.
Vccint must have reached 90% of nominal before Vcco reaches 10% of
nominal, or else the I/O pins may drive High, Low, or even both
simultaneously (!). This unpredictable behavior cannot harm the device
short-term, and it always ends as soon as Vccint has reached about 0.8
V.
If this behavior is unacceptable, append 0773 to the order code. (Note
that XCV1600-E and XCV2600-E aswell as XCV405-EM and XCV812-EM always
come with the voltage sequencing requirement.)
and so on.....
Peter Alfke
=============================
Ray wrote:
>
> Does anybody have experience/knowledge of the real consequences of
> powering up:
> 1) The 1.8V supply faster than 5ms
> 2) and after the 3.3V I/O has been powered. i.e. do they have to be
> ramped together?
> We have a board redesign in process and would like to get it right,
> but controlled ramping will expand the board size beyond our presently
> acceptable limits.
Article: 60287Followup to: <oAe7b.2784$ef4.20589@news.chello.at> By author: "Martin Schoeberl" <martin.schoeberl@chello.at> In newsgroup: comp.arch.fpga > > Jean, > > there is still a problem. If you use a point to point connection (with a > cross over cabel) it can be possible that both stations transmit without a > contention. However, Ethernet is still a bus. > Full-duplex Ethernet is *not* a bus and does *not* use CSMA/CD. It's a point-to-point self-clocking serial connection. All interconnections have to be done at layer 2 (i.e. by bridges/switches) or higher. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60288
Austin Lesea wrote: > > So what is wrong with telling folks that fixing > metastability is a myth and waste of time? Nothing. > It is similar to the patent office not considering perpetual motion > machines. > > The basic physics of it is well understood, and that is that..... Perhaps not a ideal choice of words :) The practical reality and impact of metastability are (hopefully) well understood. As to basic physics, or even models, well - that seemed to be pretty much up in the air :) From all of this, I think there emerges a case for a 'Metastable Block' or cell, which can be used in the tools, and that the tools can model, and sdvise-the-use-of. This could have variants of Fall/Rise edge dual Flip Flips, or a Latch+FF ( effectively the same thing, but may be a better hardware fit on some target devices ) ( Tsu = half clock), or Rise/Rise dual Flip Flop ( Tsu = full clock, but longer metastable settling time ) This would help those who have yet to encounter WHY they need to address metastable events. - jgArticle: 60289
Let me try to repair the damage I did with my impatience: When capturing data that is asynchronous with the clock, the flip-flop will inevitably go metastable sooner or later. Metastability manifests itself in unpredictable additional clock-to-out delay. The user knows the clock frequency, probably knows the data freqiuency at least roughly, and should know the amount of tolerable extra delay, or the acceptable Mean-Time-Between-Failure. Then one can consult the app note and table and see the connection. MTBF is always inverse proportional to the product of the clock and data frequencies. Last October I published a XilinxTechXclusives paper which shows that at a 300 MHz clock rate and 50 MHz data rate, the MTBF is one microsecond for a total clock-to-Q plus set-up time of 1.0 ns. MTBF then increases a million times for every additional half nanosecond available as extra delay. At 3 ns, the MTBF is over a billion years. All MTBF values must be scaled by the product of the two frequencies: At 100 MHz clock and ~10 MHz data, the MTBF is, therefore, 15 times longer. So, in short: Metastability is unavoidable. All attempts to avoid it are inherently doomed, but the quantitative impact of metastability is quite tolerable. That's it. Peter Alfke, Xilinx Applications =================== Jim Granville wrote: > > Austin Lesea wrote: > > > > So what is wrong with telling folks that fixing > > metastability is a myth and waste of time? > > Nothing. > > > It is similar to the patent office not considering perpetual motion > > machines. > > > > The basic physics of it is well understood, and that is that..... > > Perhaps not a ideal choice of words :) > > The practical reality and impact of metastability are (hopefully) > well understood. > As to basic physics, or even models, well - that seemed to be pretty > much up in the air :) > > From all of this, I think there emerges a case for > a 'Metastable Block' or cell, which can be used in the tools, > and that the tools can model, and sdvise-the-use-of. > > This could have variants of Fall/Rise edge dual Flip Flips, or > a Latch+FF ( effectively the same thing, but may be a better hardware > fit on some target devices ) > ( Tsu = half clock), > or > Rise/Rise dual Flip Flop > ( Tsu = full clock, but longer metastable settling time ) > > This would help those who have yet to encounter WHY they > need to address metastable events. > > - jgArticle: 60290
Hello, The fact that nSTATUS drives low indicates that the device is reporting an error in the data that it is receiving. There are many possible causes to investigate, both software and hardware: 1. Ensure that you are using the appropriate data file. In most cases you will use a RBF (raw binary file). But if programming a standard EPROM, you would use HEX. If reading as an ASCII representation of hex (like an include file for a C program) you would use TTF. If using an Altera configuration device, you would use POF. You would never directly use SOF - this is the root file made by Quartus or MAX+PLUS II from which the other files are made. 2. Check the signal integrity on the board, specifically at the APEX 20K device pins. In most configuration schemes the most important signal for signal integrity is the DCLK pin, but in PPA the nWS pin acts as a strobe, so noise on that pin can be a problem. 3. Check the timing of the signals. The configuration information on www.altera.com includes timing specifications that your system must meet for the FPGA to successfully receive the data. This is a start, but there are other possibilities as well. In order to help designers debug configuration issues, Altera has just released an "FPGA Configuration Troubleshooter" on our web site, at the following URL: http://www.altera.com/cgi-bin/ts.pl?fn=configuration This troubleshooter will ask you various questions about what your setup is and what you are seeing on the board, and lead you to possible solutions. I encourage you to try it if the suggestions I have shown above do not solve the problem. Sincerely, Greg Steinke Altera Corporation gregs@altera.com anfm@ele.pku.edu.cn (pkuanfm) wrote in message news:<15ecef93.0309040408.2dd1e644@posting.google.com>... > we configue apex20k with ppa scheme,the signal nSTATUS came to low > when we have sent about 300bytes data,how this phenomena come out? the > problem of software or hardware?Article: 60291
can I suggest taking a look to this tutorial? http://www.fpga4fun.com/PongGame.html Jean "Abby" <abhigayl@hotmail.com> wrote in message news:Tdn6b.34567$R32.1081585@news2.tin.it... > Hi! > I' m working to a project a little difficult for me, 'cause for the first > time I have to simulate a chess game using Fpga and verilog language. > I need your advices! :-) > Most of the project is realized. > Final parts concern VGA display. > I know I must work using HS and VS signals, but I don't know rightly how to > simulate all that into verilog. > I will be very happy if there's someone who can help me or suggest some > books about VGA display. > Thanx a lot! ^___^ > > > > >Article: 60292
On Tue, 09 Sep 2003 11:58:10 -0700, Austin Lesea <Austin.Lesea@xilinx.com> wrote: >So what is wrong with telling folks that fixing metastability is a myth >and waste of time? > >It is similar to the patent office not considering perpetual motion >machines. > >The basic physics of it is well understood, and that is that..... > >Austin When I was at Agilent I analysed the causes of failures in some FPGA developments. About half of all FPGA design related bugs (weighted by the time spent finding them) were associated with asynchronous logic and clock domain crossings. I guess that's not too surprising. What you may find surprising is that 0% of the clock domain crossing bugs had anything to do with metastability. Glitches and races were the cause. My interpretation: I think that most designers have heard of metastability, so they put retiming flip flops everywhere. Consequently, metastability related problems don't occur often. YMMV. Regards, Allan.Article: 60293
I downloaded Xilinx free Web ISE 5.2i, and toying with different design to get
the feeling of this Spartan-3 thingy. The only Spartan-3 device supposed to be
supported by the free verison is 3S50. I am saying "supposed", because I cannot
make it instantiate neither multipliers nor block RAMs. According to the data
sheet, there are enough of them in the device, but mapper thinks there are none.
Why is that?
- My error (so I hope!)
- Bug in ISE
- Limitation of the free version
- Typo in the datasheet, and there are no multipliers really.
Code follows. In this test (one of so many!) I let ISE infer a multiplier:
<<<
module mult (input clk, input [7:0] x, input [7:0] y, output reg [15:0] q);
always @(posedge clk)
q <= { 8'h0, x } * { 8'h0, y };
endmodule
>>>
Synthesizer infers one:
<<<
Synthesizing Unit <mult>.
Related source file is mult.v.
WARNING:Xst:643 - Multiplier result width is 16 bits.
Found 16x16-bit registered multiplier for signal <$n0000> created at line 4.
Summary:
inferred 1 Multiplier(s).
Unit <mult> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multipliers : 1
16x16-bit registered multiplier : 1
>>>
but then, in the final report, says *something* is overmapped. Note it does not
mark overused resource with an asterisk like '(*)':
<<<
=========================================================================
* Final Report *
----snip----
# MULTs : 1
# MULT18X18S : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s50pq208-4
Number of bonded IOBs: 32 out of 124 25%
Number of GCLKs: 1 out of 8 12%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
>>>
There supposed to be 4 of MULT18X18S in this part, but then maper fails with a
more detailed, but not more explainable diagnostics:
<<<
Design Summary
---snip---
Number of bonded IOBs: 33 out of 124 26%
Number of MULT18X18s: 1 out of 0 0% (OVERMAPPED)
Number of GCLKs: 1 out of 8 12%
>>>
-kkm
Article: 60294
Hi,
Sometimes back I had posted the same query on Random Number
Generator(RNG).I am reproducing one of the responses that I received ,
courtesy, Michael Chan.Hope this helps.
"
General linear feedback shift register based RNGs are probably the
easiest to implement on an FPGA. Below is some code I wrote the other
day that generates 32-bit random numbers(based on TT800 RNG).
************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LFSR is
port(
Clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
F : out STD_LOGIC
);
end LFSR;
architecture LFSR of LFSR is
signal SR : STD_LOGIC_VECTOR (25 downto 1);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
SR <= D & SR(25 downto 2);
end if;
end process;
Q <= SR(1);
F <= SR(8);
end LFSR;
************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RNG is
port(
Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
InputEnable : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR(32 downto 1);
Output : out STD_LOGIC_VECTOR(32 downto 1)
);
end RNG;
architecture RNG of RNG is
component LFSR
port(
Clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
F : out STD_LOGIC
);
end component;
-- magic vectors
constant MAG_FEEDBACK : STD_LOGIC_VECTOR := X"8EBFD028";
constant MAG_OUTA : STD_LOGIC_VECTOR := X"2B5B2500";
constant MAG_OUTB : STD_LOGIC_VECTOR := X"DB8B0000";
signal D, F, Q, shifted, feedback : STD_LOGIC_VECTOR(32 downto 1);
-- output processing signals
signal outa, outb : STD_LOGIC_VECTOR(32 downto 1);
begin
LFSRs : for i in 32 downto 1 generate
ShiftRegister : LFSR port map (Clock, D(i), Q(i), F(i));
end generate;
-- twist and feedback
shifted <= '0' & Q(32 downto 2);
feedback <= (F xor shifted) when (Q(1) = '0') else
(F xor shifted xor MAG_FEEDBACK);
D <= feedback when InputEnable = '0' else Input;
-- produce output
outa <= Q xor ((Q(25 downto 1) & B"0000_000") and MAG_OUTA);
outb <= outa xor ((outa(17 downto 1) & B"0000_0000_0000_000") and
MAG_OUTB);
Output <= outb xor (X"0000" & outb(32 downto 17));
end RNG;
************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Testbench is
end Testbench;
architecture Testbench of Testbench is
component RNG
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
InputEnable : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR;
Output : out STD_LOGIC_VECTOR
);
end component;
signal Reset : STD_LOGIC;
signal Clock : STD_LOGIC;
signal InputEnable : STD_LOGIC;
signal Input, Output : STD_LOGIC_VECTOR (32 downto 1);
begin
RNG1 : RNG port map (Reset, Clock, InputEnable, Input, Output);
-- clock
process
begin
Clock <= '0';
wait for 5 ns;
Clock <= '1';
wait for 5 ns;
end process;
-- reset RNG
process
begin
Reset <= '0';
wait for 2 ns;
Reset <= '1';
wait for 10 ns;
Reset <= '0';
wait for 10000 ns;
end process;
-- seed RNG
process
begin
Input <= (others => '0');
InputEnable <= '1';
wait until Clock'Event and Clock = '1' and Reset = '0';
wait for 1 ns;
-- seed RNG with any old stuff
Input <= X"95f24dab"; wait for 10 ns;
Input <= X"0b685215"; wait for 10 ns;
Input <= X"e76ccae7"; wait for 10 ns;
Input <= X"af3ec239"; wait for 10 ns;
Input <= X"715fad23"; wait for 10 ns;
Input <= X"24a590ad"; wait for 10 ns;
Input <= X"69e4b5ef"; wait for 10 ns;
Input <= X"bf456141"; wait for 10 ns;
Input <= X"96bc1b7b"; wait for 10 ns;
Input <= X"a7bdf825"; wait for 10 ns;
Input <= X"c1de75b7"; wait for 10 ns;
Input <= X"8858a9c9"; wait for 10 ns;
Input <= X"2da87693"; wait for 10 ns;
Input <= X"b657f9dd"; wait for 10 ns;
Input <= X"ffdc8a9f"; wait for 10 ns;
Input <= X"8121da71"; wait for 10 ns;
Input <= X"8b823ecb"; wait for 10 ns;
Input <= X"885d05f5"; wait for 10 ns;
Input <= X"4e20cd47"; wait for 10 ns;
Input <= X"5a9ad5d9"; wait for 10 ns;
Input <= X"512c0c03"; wait for 10 ns;
Input <= X"ea857ccd"; wait for 10 ns;
Input <= X"4cc1d30f"; wait for 10 ns;
Input <= X"8891a8a1"; wait for 10 ns;
Input <= X"a6b7aadb"; wait for 10 ns;
InputEnable <= '0';
wait for 10000 ns;
-- numbers are generated with Clk
end process;
end Testbench;
************************************************************************
"
Regards,
Jaideep
> >
> > Also how to generate Random Number's in VHDL?
> >
> >
> > Thanks
> >
> > Rgds
> >
> > Macie
>
> For random numbers try this package:
>
> http://www.janick.bergeron.com/wtb/packages/random1.vhd
>
> MPJB
Article: 60295"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:<F7q7b.408266$uu5.74285@sccrnsc04>... > "ykagarwal" <yog_aga@yahoo.co.in> wrote in message > news:4d05e2c6.0309090919.261490a1@posting.google.com... > > would like to know which is the best algorithm to > > make a pipelined divider in hardware. newton raphson, > > goldshmit .. srt(is it possible?) > > if i have space as much as to have as much as 5 radix-4 > > srt dividers in a xilinx v2 fpga.. > > Pipelined dividers have been used on machines like the IBM 360/91 and the > Cray-1, and are well described in pipelined computer architecture books for > many years after those machines were built. > > Though in both cases they are used for floating point, where the > requirements are different. The 360/91, for example, rounds the low bit > instead of truncating as the architecture specifies, and would be usual in > fixed point. I don't know how hard that would be to change. > > -- glen well my requirement is too for double precision .. would u like to suggest me a pipelined comp arch book for this purpose.. anyway what is the best way, that's what i want to explore first. Xilinx coregen divider core doesn't offer that much width in its pipelined divider .. don't know why may be xilinx gurus can justify .. anybody knows which algorithm they are using ? regards --ykaArticle: 60296
I have tried using the console uart instead of debug uart, it still can't work. I have connected the mouse to the board by a serial cable.Any one have any document that I can refer to? Thank you very much. San "H. Peter Anvin" <hpa@zytor.com> ??? news:bjj3di$j57$1@cesium.transmeta.com ???... > Followup to: <bjhgdo$1li7$1@justice.itsc.cuhk.edu.hk> > By author: "clsan" <clsan@cuhk.edu.hkk> > In newsgroup: comp.arch.fpga > > > > Hi all, > > > > I am doing a project and using Altera Nios Development kit with Stratix > > Edition. I need to connect a serial/PS/2 mouse to that board . But the board > > can't get any signal from the mouse, anyone has this experience can share > > with me?I have already set the UART 2 to 1200 baud rate. > > Thank you very much. > > > > Most mice need a particular combination of the control signals in > order to enter serial mode (as opposed to PS/2 mode.) This probably > means you need to use the CONSOLE port as opposed to the DEBUG port, > and drive the proper signals. > > You'd also need a null modem cable in between, since the NDK board is > wired as a DCE instead of a DTE (a mistake in my opinion.) > > -hpa > -- > <hpa@transmeta.com> at work, <hpa@zytor.com> in private! > If you send me mail in HTML format I will assume it's spam. > "Unix gives you enough rope to shoot yourself in the foot." > Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60297
Kirill 'Big K' Katsnelson <kkm@dtmx.com> wrote: : I downloaded Xilinx free Web ISE 5.2i, and toying with different design to : get the feeling of this Spartan-3 thingy. The only Spartan-3 device : supposed to be supported by the free verison is 3S50. I am saying : "supposed", because I cannot make it instantiate neither multipliers nor : block RAMs. According to the data sheet, there are enough of them in the : device, but mapper thinks there are none. Why is that? - My error (so : I hope!) : - Bug in ISE : - Limitation of the free version - Typo in the : datasheet, and there are no multipliers really. The first batch of XC3S50 (labeled XC3S50J) has no block ram and no multipliers. Later batches will have those things as stated in the datasheet. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 60298
fpga_uk@yahoo.co.uk (Isaac) wrote in message news:<889eb3fb.0309090632.54bb1472@posting.google.com>... > TechnologyConsultant@gmx.ch (Technology Consultant) wrote in message news:<a307051a.0309090243.75974cb8@posting.google.com>... > > How are you connecting your FPGA to your PC ? fpga_uk@yahoo.co.uk (Isaac) wrote in message news:<889eb3fb.0309090632.54bb1472@posting.google.com>... > I am fine . Thankyou . > I am glad [that] you are fine. I could not find any documentation about the board you are using. Would you EMail some of it? Regards, TechCon.Article: 60299
"jjl" ha scritto nel messaggio You may want to check out www.opencores.org for vga IP in verilog. > > Also, a very goodprimer of vga HS/VS at: > http://www.xess.com/appnotes/vga.pdf > > Finally, a non-free (for cost) comple VGA core with DMA engine and > SDRAM controller (32bit data path) in multi-clock domain at: > http://www.cmosexod.com/fnd.htm > > hope this helps, Second link you suggest to me is very interesting! Thanx a lot! :-)
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z