Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Altera have told me it is not possible to perform a multiple device configuration (typically done by hooking up the nCE/nCEO pins of the individual FPGAs) when using local update mode (update over ethernet). Does anyone know why it isn't possible? It is not reasonable for a board with 10 FPGAs to have 10 separate ethernet connections, and having to update a set of these boards in the field using a programming cable would be most tedious.Article: 58951
Wilhelm Klink <kommandantklink@hotmail.com> wrote in message 6011e208.0308042011.5bdae5e1@posting.google.com... > Altera have told me it is not possible to perform a multiple device > configuration (typically done by hooking up the nCE/nCEO pins of the > individual FPGAs) when using local update mode (update over ethernet). > Does anyone know why it isn't possible? It is not reasonable for a > board with 10 FPGAs to have 10 separate ethernet connections, and > having to update a set of these boards in the field using a > programming cable would be most tedious. Regardless of ethernet, at least for the passive serial configuration mode in SRAM devices, it is possible. I did it.Article: 58952
When both of them were installed on my pc, I found: 1.ModelSim can't compile Xilinx library 2.ISE will give a fatal error when ActiveHDL try generate post-PAR timing simulation model and they both can work well separately.Article: 58953
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F2EFF97.9072E30A@yahoo.com...
> I added a variable to calculate a time for a wait statement in a
> testbench and am not getting this error from ModelSim...
^^^ now??
>
> Signal arm_command is read by the VITAL process but is NOT in the
> sensitivity list
>
> This is the line of code producing the error...
>
> WaitTime := (ARM_command.RelTime - (now - CurrentTime));
>
> I follow this up with a check for negative values before using in
the
> wait. ARM_command is a signal and WaitTime and CurrentTime are
> variables. And of course all these objects are of type time. This
same
> calculation done directly in the wait statement gives no error.
>
It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?
If it's a warning, just ignore it.
If it's an error, it sounds like a bug.
regards
Alan
p.s. I know it's nothing to do with this error, but I'd check for
negative values before assigning, just because I am paranoid (!). In
particular I wonder what happens if you assign a negative time value
to a variable of type time?
e.g.
assert ( (ARM_command.RelTime - (now - CurrentTime)) >= 0 ns )
report "negative time value";
waittime := ...
p.p.s.
Reading the LRM shows I really am being paranoid, as type TIME is
guaranteed to include the range -2**9+1 to 2^9-1, so negative
time values in variables of type TIME are ok.
--
Alan Fitch
Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
Article: 58954Hi y'all, Right, we're making some progress on parts sourcing, thanks in no small way to some of you out there who shall remain nameless to avoid embarrassment. (Thanks!) What has come up next is the requirement for a JTAG programmer. I've found one here: http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm but wonder whether using it on devices only capable of 3v3 or lower may kill them. I'm also wondering whether some of the chips I'm considering (Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs that make a generic JTAG pod unworkable. If it merely requires level translation, I'm golden. Comments? RobArticle: 58955
John Williams wrote: <snip hardware alignment issues> > Yeah I had a few tough moments figuring out the alignment and dealing > with pointer aliasing and stuff - seems to be mostly figured out now. I figured why the decided to do that was mostly down to making the hardware simpler vs. having a full featured 16550 replacement for free. At the moment my low level debug driver used by ppc_md.progress has some inline ppc assembly to get things right which does need fixing. I found doing a straight word read/write followed by an appropriate mb() for syncronisation did not work and had to do a manual stw with eieio as an inline function was is quite clearly not the way to do this in the longer term at all. > The uartlite is a funny thing, on the surface it looks like a fully > featured uart, but when I delved a bit deeper there are some > idiosyncracies that make it just that bit more tricky - like the > interrupt generation, for example. I am about to take a look at that which will be fun because I cannot be sure the hardware definition is not completely wrong either. The other thing is that I believe my Xuartlite is on IRQ 1 but how do I explicitly bind it to a particular IRQ in the EDK? System.MHS? > OK cool. What is the status of V2Pro/PPC linux these days from a user > perspective? As I said privately there is a bunch of patches but not a single source of a port yet. I am mostly using the public Mind patches with some of my own code and firmware to tie things together. The kernel is a stock 2.4.20 as I do not want to use the Mvista tree. <snip Microblaze UART blah> > Yeah I'll avoid the 16550 for as long as possible, for simple console > stuff the uartlite should be fine. We only need the UART for debugging which makes the 16550 IP a little expensive in addition to gdb and the time old favourite flashing leds. Jon.Article: 58956
Hi, I contacted Insight Memec about obtaining a Virtex II 1000 development board for home use. I trust this is the board you are using? Cheers, Jon.Article: 58957
Arthur <arthuryang42spam@yahoo.com> wrote: : Your design should fit going from the 9500 to the 9500xl. The 9500xl : actually has more function block fanin (36 to 54!) so I would think : that there should be no fitting issues. That's what I hoped, but no luck (so far). : The loss of wire-anding would cause your PTerm requirements to : increase. Perhaps if you were near the maximum utilization for this it : would not fit. I suspect that is it. The report I get from the failed XC9536XL fit is: "Mapping a total of 36 equations into 2 function blocks...... ERROR:Cpld:935 - Cannot place signal P<3>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions". When successfully put into an XC9536 the report says: Macrocells used: 36/36 (100%) Product terms used: 146/180 (81%) Registers used: 36/36 (100%) Pins used: 34/34 (100%) Function block inputs used: 56/72 (77%) There are lots of signals shown as "wire-AND input". : You may want to try contacting the Xilinx hotline. They are willing to : try fitting close designs. I'll try that. Richard. http://www.rtrussell.co.uk/Article: 58958
The HC part on the schematic is supplied with VCC from your board - you can also get parts with dual voltage supply that allow this type of interface, (CB3T ti parts one example). Check Altera's web site for the byteblaster MV, there are schematics for the thing up there too, and you could wire through the RESET line so that all TAP controllers would work. Andrew. Rob Judd wrote: >Hi y'all, > >Right, we're making some progress on parts sourcing, thanks in no small >way to some of you out there who shall remain nameless to avoid >embarrassment. (Thanks!) > >What has come up next is the requirement for a JTAG programmer. I've >found one here: > >http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm > >but wonder whether using it on devices only capable of 3v3 or lower may >kill them. I'm also wondering whether some of the chips I'm considering >(Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx >XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs >that make a generic JTAG pod unworkable. If it merely requires level >translation, I'm golden. > >Comments? > >Rob > >Article: 58959
I am having problems gtting the retiming feature in Synplify to work. I am coding in a style that utilizes the behavioural retiming(BRT) of synopsys. I code a mac as simple ((a*b) + c) + bulk delay. Synopsys then retimes the code by pipelining the mac. When I try to test this code in an fpga, Synplify does not retime the registers properly. Has anyone else tried this? thanks JohnArticle: 58960
ypw, I, too, have my doubts on this one. Even though you may have used this prior to the patent, that would only allow you to continue using the technique without paying royalties. If no one published or "disclosed" the technique, then the patent could be valid. Hopefully you have a public published document prior to their "discovery"? That would kill it immediately. Since we have been using unidirectional interconnect since Virtex (about 5 years ago now), with soft processor cores, and peripherals, I also believe that we (Xilinx) have a prior use claim. Since we also published that we implemented our "tri-state" buses with unidirectional interconnect in Virtex (as tristates were too slow), it makes this patent pretty dubious for any FPGA application. As well, any combination of cores uses single direction buses in Virtex and all subsequent families (for speed). But, if you can not point to a published article describing the technique in an ASIC/ASSP, then they just might "own it." Austin y_p_w wrote: > The URL would be too long. It's patent 6,601,126, and > is available at <http://patft.uspto.gov/netahtml/srchnum.htm> > > There was an EE Times (and other CMP websites) article about > this story. > > <http://www.eet.com/semi/news/OEG20030801S0043> > > This sounds fishy to me. I've personally worked on SoC designs > using only uni-directional busses with various asynchronous > peripherals - well before the time this patent was filed. I'd > like to see PalmChip try to enforce this patent. The EET article > also mentions that FPGAs have been using this kind of technology > for a while. > > Here are some of the "claims" of the patent: > > "1. An on-chip interconnection system, comprising: > > a single semiconductor integrated circuit (IC); > > a plurality of uni-directional buses disposed in the IC; > > a peripheral-bus (p-bus) included in the plurality of uni-directional > buses and that uses a simple non-pipelined protocol and supports both > synchronous and asynchronous slave peripherals; > > a p-bus controller connected to the p-bus and constituting an only > bus-master, and including a centralized address decoder for generating > a dedicated peripheral select signal, and providing for a connection > to synchronous and asynchronous slave peripherals, and further > providing for an input/output (I/O) backplane that allows a processor > to configure and control any of its slave peripherals; and > > an m-bus included in the plurality of uni-directional buses, and for > providing a direct memory access (DMA) connection from any said slave > peripherals to a main memory and permits peripherals to transfer data > directly without processor intervention. > > 2. The on-chip interconnection system of claim 1, wherein, there are > included no tri-stated-buses, and no bi-directional buses. > > 3. The on-chip interconnection system of claim 1, wherein, each signal > has only a single buffer driver. > > 4. The on-chip interconnection system of claim 1, wherein, any > broadcast signals are re-driven by simple buffers with no extra > control logic."Article: 58961
Rob, Even the 2.5V Vccaux parts are 3.3V JTAG compatible (ie Virtex II Pro, Spartan 3). The JTAG inputs are designed to be 3.3V tolerant (special cells), and the JTAG outputs are open drain, and use external pullup resistors to 3.3V. The outputs are also special cells (not regular IOBs). Austin Rob Judd wrote: > Hi y'all, > > Right, we're making some progress on parts sourcing, thanks in no small > way to some of you out there who shall remain nameless to avoid > embarrassment. (Thanks!) > > What has come up next is the requirement for a JTAG programmer. I've > found one here: > > http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm > > but wonder whether using it on devices only capable of 3v3 or lower may > kill them. I'm also wondering whether some of the chips I'm considering > (Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx > XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs > that make a generic JTAG pod unworkable. If it merely requires level > translation, I'm golden. > > Comments? > > RobArticle: 58962
Hal, Vcc bounce is hardly an issue with most designs. That is why it is not often considered. Ground bounce affects everything: slicing level, jitter, timing, function of the device (etc). Vcc bounce my affect IO output timing, jitter, but is generally a second order effect. You can use "virtual Vcco" pins as well, but it is rare that it is done (and ends up being useful). Austin Hal Murray wrote: > >Not "all", just one extra per Vcco power/ground pin pair is all that is required > >to reduce ground bounce by another 20% (roughly). The IO is set to a strong > >standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is > >connected to the ground plane just like a ground pin. Adding pins past the > >first leads to a very small improvement (not worth it). > > Does it do any good to use a similar setup for power? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 58963
Hi - I am trying to run a very simple simulation to verify the functionality of the "block ram" component in my spartan ii fpga. I am using modelsim tools that I downloaded from the xilinx website, and I'm using the "ramb4_s8" primitive. The simulation appears to work properly except that there appears to be a delay of one clock cycle when reading from the memory. In other words, if I enable the ram, deassert the write enable, and select the read address, I need TWO rising clock edges to get the correct data to appear at the data_out port. I am doing a simple behavioral simulation so there shouldn't be any delay issues involved. The data sheet clearly shows that I should only need one rising clock edge to execute the read. Any ideas? Thanks very much!!! --Iyad ------------------------------- Iyad Obeid Dept. of Biomedical Engineering Duke University io@duke.edu (919)660-5104 www.duke.edu/~ioArticle: 58964
Jay wrote: > Hi all, > > I'm doing prototyping for ASICs. Before I start my work, I have to estimate > the gates the FPGA or CPLD would use. > I know it's hard to get a precise result. I just want some common answer, > 1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just > logic) > Please tell me your experience. > > Thanks, > Jay > > > Hi Jay, When defining an ASIC gate as a standard 2-port nand gate, the typical relation between ASIC and FPGA would be 1:10. Kind regards, YvesArticle: 58965
y_p_w@hotmail.com (y_p_w) wrote in message news:<591da479.0308041524.4ac35381@posting.google.com>... > The URL would be too long. It's patent 6,601,126, and > is available at <http://patft.uspto.gov/netahtml/srchnum.htm> Congratulations for USPTO: good work, boys! I've heard that the next patent in line is: "round device that minimizes friction while moving vehicles, a.k.a. wheel", granted for GM, of course...Article: 58966
"y_p_w" <y_p_w@hotmail.com> wrote in message news:591da479.0308041524.4ac35381@posting.google.com... > The URL would be too long. It's patent 6,601,126, and > is available at <http://patft.uspto.gov/netahtml/srchnum.htm> > > This sounds fishy to me [...] > > Here are some of the "claims" of the patent: [...] Sounds an awful lot like the ARM-originated AMBA interconnect spec, which has been in the public domain for years. Nice reinforcement of my prejudices about patent examiners. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 58967
Alan Fitch wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F2EFF97.9072E30A@yahoo.com... > > I added a variable to calculate a time for a wait statement in a > > testbench and am not getting this error from ModelSim... > ^^^ now?? Yes, now, not "not". > > > > Signal arm_command is read by the VITAL process but is NOT in the > > sensitivity list > > > > This is the line of code producing the error... > > > > WaitTime := (ARM_command.RelTime - (now - CurrentTime)); > > > > I follow this up with a check for negative values before using in > the > > wait. ARM_command is a signal and WaitTime and CurrentTime are > > variables. And of course all these objects are of type time. This > same > > calculation done directly in the wait statement gives no error. > > > > It sounds like Modelsim is confused. Is it actually an error, or just > a warning? Having a signal read that is not in the sensitivity list > is not an error. Can you disable Modelsim's synthesis checks? > > If it's a warning, just ignore it. > > If it's an error, it sounds like a bug. > > regards > > Alan > > p.s. I know it's nothing to do with this error, but I'd check for > negative values before assigning, just because I am paranoid (!). In > particular I wonder what happens if you assign a negative time value > to a variable of type time? > e.g. > > assert ( (ARM_command.RelTime - (now - CurrentTime)) >= 0 ns ) > report "negative time value"; > > waittime := ... > > p.p.s. > Reading the LRM shows I really am being paranoid, as type TIME is > guaranteed to include the range -2**9+1 to 2^9-1, so negative > time values in variables of type TIME are ok. The possibility of being negative was why I was using a variable instead of just sticking it in the wait statement. I thought it would be better to calculate it once and then test it and set to zero if negative. So now I have to do the calculation twice. I am getting the same error from a different assignment now. The common point is that a signal is on the right hand side of the assignment and a variable is on the left. I am using the variable assignment operator, ":=". This is reported as an error, not a warning. Last_Bus_Action := Bus_Command.Bus_Action; In both cases, part of the right hand expression is an element in a record. The error reports the record "Bus_Command" as missing from the sensitivity list, not the element! Could the VITAL process have a bug in regards to dealing with record elements? This doesn't sound likely to me. But then I don't even know what the VITAL process is. Maybe I need to contact Mentor about ModelSim. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58968
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F2FC028.85C217A@xilinx.com>... > ypw, > > I, too, have my doubts on this one. > > Even though you may have used this prior to the patent, that would only > allow you to continue using the technique without paying royalties. If no > one published or "disclosed" the technique, then the patent could be > valid. Hopefully you have a public published document prior to their > "discovery"? That would kill it immediately. It was fairly obvious. I was working at a processor company that integrated an existing core with several external peripherals to emulate another processor. We used a lot of unidirectional communications with address decoders. > Since we have been using unidirectional interconnect since Virtex (about 5 > years ago now), with soft processor cores, and peripherals, I also believe > that we (Xilinx) have a prior use claim. Since we also published that we > implemented our "tri-state" buses with unidirectional interconnect in > Virtex (as tristates were too slow), it makes this patent pretty dubious > for any FPGA application. I'm just curious as to whether a soft core implemented in an FPGA would be close enough to an SoC to make this patent's claims dubious regardless its use in any ASICs. > As well, any combination of cores uses single direction buses in Virtex > and all subsequent families (for speed). > > But, if you can not point to a published article describing the technique > in an ASIC/ASSP, then they just might "own it." The AMBA 2.0 spec was published by ARM in May 1999. There are probably several white papers, academic papers, and published web sites that outline similar SoC frameworks.Article: 58969
Hi Lan, you should not need to do any of this. After opening a V2PDK shell (Windows) or sourcing v2pro_setup (Solaris) change into your project directory. After editing flow.cfg (if necessary) type "make synth". Synplify will open (if you didn't chose to add -batch in flow.cfg) and you can synthesize the design. After leaving synplify type "make fpga" to start the implementation followed by "make bit" to generate the bitstream. - Peter Lan Nguyen wrote: > Hi, > > I did the synthesis with Synplify 7.3 and got the output "top.edif". > Then I used "edif2ngd" to convert "top.edif" to "top.ngo". This is > where I got the problem. The "top.ngo" was not properly produced, so > the program stopped and popped up the error: > > "ERROR:XdmHelpers:828: File "top.ngo" is not in NGD or XDB format". > > I could not figure out what the problem is. > > Any help would be very appreciated. > > Lan > > Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F276433.EFFC08BE@xilinx.com>... > > Lan, > > > > while XST is not supported for the ml300_embedded_* design shipping with ML300/V2PDK 1.5 it > > will work with the Verilog version but not work with VHDL. However, you will have to remove > > some peripherals from the system by modifying flow.cfg and changing the yes/no table at the > > end of the file. > > > > The default setup for the ml300_embedded_verilog design is the one that is part of the > > ML300 ACE files, ie. Linux will boot even if there are devices like AC97 and others that > > are not directly supported by Linux. > > > > flow.cfg is the central file for all configurations, tools, SW, peripherals, etc. > > > > - Peter > > > > > > Lan Nguyen wrote: > > > > > Hi Peter, > > > > > > I've got the Developer's Kit V2PDK VP4. I wanted to run the reference > > > designs and test the results via the serial port. I tried and got > > > nothing in the HyperTerminal. > > > > > > Does XST work for the synthesis ? If so, what modifications do I have > > > to make ? > > > > > > (I was told that the only way is to get Synplify synthesis tool) > > > > > > Thanks > > > > > > Lan > > > > > > Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F1F1FE4.B2A8FCB1@xilinx.com>... > > > > Yes, it does. The reference design actually comes with the MLD (Microprocessor > > > > Library Definition) technology that allows you to automatically generate a BSP > > > > for Linux consisting of Xilinx layer 0 and 1 drivers according to the hardware > > > > definition (MHS). When you generate the libraries from the system_linux.xmp > > > > project file you will get this BSP. > > > > > > > > The BSP will also contain necessary patches to the Linux kernel to make the > > > > design work with MontaVista Linux 3.0 (FYI: the only thing that needs to be > > > > patched is the code for the Xilinx interrupt driver since the interrupt > > > > controller from V2PDK and EDK are different) > > > > > > > > - Peter > > > > > > > > > > > > tk wrote: > > > > > > > > > Hi Peter, > > > > > > > > > > I would like to ask if the reference design support > > > > > MontaVista Linux Pro 3.0 ? > > > > > > > > > > Thanks very much! > > > > > > > > > > tk > > > > > > > > > > Peter Ryser wrote: > > > > > > > > > > > Antti, > > > > > > > > > > > > the EDK reference design for ML300 contains > > > > > > - 1 PPC 405 > > > > > > - 1 PLB DDR > > > > > > - 1 PLB bus with arbiter > > > > > > - 1 PLB2OPB bridge > > > > > > - 1 PLB BRAM controller with 32 KB BRAM attached > > > > > > - 1 OPB Uart > > > > > > - 2 OPB GPIO > > > > > > - 1 OPB 10/100 Ethernet (interrupt driven) > > > > > > - 1 OPB IIC > > > > > > - 1 OPB System ACE CF > > > > > > > > > > > > There is no touchscreen, PS/2, TFT, parallel port and AC97. Adding these > > > > > > peripherals to the design is planned for a later release that will most > > > > > > likely happen towards the end of the year. > > > > > > > > > > > > There is some documentation in the zip file that lists the peripherals and > > > > > > explains the design. > > > > > > Again, please contact your Xilinx FAE if you would like to get access to > > > > > > this design. > > > > > > > > > > > > Thanks, > > > > > > - Peter > > > > > > > > > > > > > > > > > > > > > > > > Antti Lukats wrote: > > > > > > > > > > > >> Peter Ryser <ryserp@xilinx.com> wrote in message > > > > > >> news:<3F1846C0.776CD1F5@xilinx.com>... > > > > > >> > > > > > > >> > If you want to work with EDK please contact your FAE and ask him to get > > > > > >> > you access to the EDK reference design for ML300. He will be able to > > > > > >> > get you access to the design. > > > > > >> > > > > > >> Hi Peter, > > > > > >> > > > > > >> when we received the EDK + DDR project, I also asked to be notified > > > > > >> when a better EDK ref. design will be available, and so far have not > > > > > >> got any more info, could you please enlight us what additional cores > > > > > >> are available in the EDK ref. design you mentioned? > > > > > >> > > > > > >> ASFAIK TFT and Touchscreen are not implemented (or hopefully are now?) > > > > > >> I have still having trouble to get EDK to work correctly using the > > > > > >> obsoleted TFT ref. design - eg. display is looking in stripes 8 pixels > > > > > >> missing after 8 ok pixels - if the problem is fixed and ref design > > > > > >> availabl would be greate. > > > > > >> > > > > > >> anttiArticle: 58970
john_p_graham@hotmail.com (jgraham) wrote in message news:<ea24bbb8.0308050632.2907332@posting.google.com>... > I am having problems gtting the retiming feature in Synplify to work. > I am coding in a style that utilizes the behavioural retiming(BRT) of > synopsys. > I code a mac as simple ((a*b) + c) + bulk delay. Synopsys then retimes > the code by pipelining the mac. > > When I try to test this code in an fpga, Synplify does not retime the > registers properly. > Has anyone else tried this? Yes, I tried it when Synplify first introduced retiming. It had some effect, but no, it didn't work as I wanted it to, so I didn't buy Synplify Pro. However, I am still a happy user of Synplify Amateur. Alan Nishioka alann@accom.comArticle: 58971
Hi Jon, > > OK cool. What is the status of V2Pro/PPC linux these days from a user > > perspective? > > As I said privately there is a bunch of patches but not a single source > of a port yet. I am mostly using the public Mind patches with some of my > own code and firmware to tie things together. > The kernel is a stock 2.4.20 as I do not want to use the Mvista tree. Linux support for Virtex-II Pro is available as part of the LinuxPPC kernel tree. Access to this tree which is synchronized with the main kernel tree in regular intervals is available from http://www.penguinppc.org/kernel.shtml. MontaVista is just one host for the tree. Unfortunately, the code available in the LinuxPPC repository has not yet been moved into the main kernel tree. The available port supports Uarts, Ethernet, IIC, interrupt controller, PCI, GPIO, TFT, touchscreen, PS/2, and System ACE CF. Xilinx is working with MontaVista to add support for UartLite, SPI, RTC, and Gbit Ethernet. - PeterArticle: 58972
Jon, besides what John has produced for uCLinux, Xilinx is working with MontaVista to integrate UartLite support into the Linux kernel tree for PowerPC. - Peter Jon Masters wrote: > Hi, > > Can someone tell me if there is a Xuart Lite driver for Linux already > and where I might find the patches before I continue with writing one? > > Cheers, > > Jon.Article: 58973
I have the same problem as Rgr and I already did what you said. I imported the updated files back to XPS and used "update bitstream". I tried downloading the program onto the board and it doesn't work. By the way I'm using EDK 5.1i and the ML300 evaluation board. Please help.Article: 58974
I guess an FPGA would count as "a single semiconductor integrated circuit". Kolja Sulimma Austin Lesea <Austin.Lesea@xilinx.com> wrote in message > But, if you can not point to a published article describing the technique > in an ASIC/ASSP, then they just might "own it." > > The EET article > > also mentions that FPGAs have been using this kind of technology > > for a while. > > > > Here are some of the "claims" of the patent: > > > > "1. An on-chip interconnection system, comprising: > > > > a single semiconductor integrated circuit (IC); > > > > a plurality of uni-directional buses disposed in the IC;
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z