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Go to google.com, it has 170 hits... http://www.google.com/search?hl=en&lr=&ie=ISO-8859-1&q=PAL20L10&btnG=Google+Search Peter Alfke ===================== Colin Jackson wrote: > > Anyone have a datasheet for a National PAL20L10? > > Thanks, > Colin Jackson > cjackson@regulatedeng.comArticle: 59226
I have the standard sort of circuit from the Xilinx App note driving an off chip clock:- Main clock comes onto chip through an IBUFG to CLKIN of the DLL CLK0 from the DLL is fed off the chip through an OBUFT. The output of the OBUFT, which is on a global clock pin, is fed back in via an IBUFG to form CLKFB of the DLL. This seems to work fine. Main clock to output clock delay is constrained to <5 ns and this constraint is achieved. Next I wanted to have 4 off chip clock outputs, timed as close as possible to the first one.. I buffered the CLK0 from the DLL with a BUFG before the OBUFT to try to ensure that there was low skew between the 4 off chip clock outputs. The main clock to external clock delay increased to 10nS and failed the constraint. It seemed that the router had used a mixture of global and other routing to get the CLK0 to the various OBUFT, and that the other routing was slow. I removed the BUFG and the delay then passed my <5ns constraint without probs, despite using non-global routing. I am puzzled? Am I overlooking something? (Target device is a Virtex II 6000) Many Thanks, Ken.Article: 59227
Hi, I have integrated various patches and the Xuartlite driver from John Williams to get kernel 2.4.20 up and running on the development board. Although I have now done this I am interested to hear official board support status from others. I have yet to hear back from Mind. Jon.Article: 59228
Hi Ken, > We're about to start a Nios on Cyclone project and I'm expecting to get at > least 50MHz operation. Now I'm really curious! > > I'm troubled that Altera posts little or no performance information on Nios > whereas Xilinx posts 85MHz (Spartan3) and even gives benchmark scores for > its MicroBlaze offering. It's fairly easy to reach 50MHz with a NIOS core on a Cyclone. The standard 32-bit design, which is pretty dressed-up, easily meets this requirement. I've had fairly minimal systems run way over 75MHz (actually, 98MHz) on an EP1C6T144C7 (medium speed grade). Of course, if you have a big nonpipelined multiplier or some other long combinatorial path in the rest of the FPGA, this is going to affect ytour clock speed as well. Best regards, BenArticle: 59229
Hi Maxlim, > I'm trying to operate the nios processor with my > crypto-processor . > The default clock frequency (33.33 MHz) is too slow for fast > cryptosystem performance. I'd tried to get another clock with 50 MHz > frequency through PLL and generate the nios processor with 50 MHz in > the clock setting. The system still can operate correctly with some > simple application on it's own. But when I tried to run some > application involved the hash processor, sometime it'll automatically > jump into Nios peripheral test menu after display message of (return > address is 0x000000) when it try to display the result. (The > appication runs well in system with 33.33 Mhz clock). > The hardware platform I'm using now is Nios development board > populated by an APEX?20KE device (EP20K200EFC484). Is there anyway > that I can solve this problem? Sounds like a memory timing problem or somesuch. I suggest you contact your local disti or Altera FAE on how to check for I/O timing problems. Best regards, BenArticle: 59230
Hi Don, > The device is an EP20K, 1500EBC652-1X, the user said that he > is using <20% in logic and <60% in memory. We've discussed your > info and have decided that the first step is, as you recommend, > upgrading to 3.0. > > The reason for the P&R is that we do not have any real lab > equipment and the user is bringing signals out to the 3 on-board > LEDs. I take it that this requires a new P&R everytime. There's two delightful tools in Quartus, called SignalTap and SignalProbe. I suggest you have your user look into the Quartus help system to learn about these subjects. SignalTap is a way to synchronously capture internal signals into memory blocks (there's still 40% left) and view them using the ByteBlaster JTAG interface, and SignalProbe is a way to route selected signals to output pins. Both support incremental P&R quite well - provided you don't have a bloody virus scanner running in full file-scan mode on the user's workstation. I found that the additional scanning will negate all of Altera's efforts to speed up P&R. Best regards, BenArticle: 59231
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bhb0pd$c2i$1@agate.berkeley.edu... > In article <bhampo$eu0$1$8300dec7@news.demon.co.uk>, > Jonathan Bromley <jonathan.bromley@doulos.com> wrote: > >Not all prior art originates in the USA, despite what some > >USPTO patent examiners seem to think :-) > > Come on, the USPTO patent examiners wouldn't know prior art if it came > up and bit them on the ass, mostly because the system largely relies > on what the patent filer cites! > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu It is not up to the examiner to know all the prior art in a field it is up to the inventor. The inventor is supposed to be such an expert in his field that he's gone and invented something. The inventor is obliged to collect all the prior art and present it to the examiner. The examiner also has prior art at his disposal but is only presumed to know enough of the art to determine if this is a new and useful invention. SteveArticle: 59232
rickman wrote: >"B. Joshua Rosen" wrote: > > >>On Fri, 08 Aug 2003 11:35:05 +0200, Aart van Beuzekom wrote: >> >> >> >>>Hei, >>> >>>I will start developing FPGA applications with WebPack. My problem is that >>>my OS is WinNT, which is not supported by WebPack 5.2i. I've got a CD >>>laying round here with WebPack version 4.2WP0.0. >>> >>>Can anybody tell me if the advantages of v. 5.2i are so much that >>>upgrading to Win2000 really is necessary? >>> >>>My application will run on a Spartan-II device. Clock speed wil not be an >>>issue, but efficient use of logic cells might be. >>> >>>Thanks, >>> >>>Aart >>> >>> >>Upgrade to a real operating system, Linux. The 5.2 tools work fine using >>wine on Linux. Next month the 6.1 release will run natively on Linux. >> >> > >Correct me if I am wrong, but this is not Linux exactly. It is Redhat >and only one specific version of Redhat if I am not mistaken. > Redhat 7.3 and 8.0 will be officially supported. > If you >are running anything else, the tools are not supported. I am not trying >to knock Xilinx, I just want it to be clear that there are supported >version limitations under *any* OS. > >I have been told by email that Win2K is supported after SP2, it is just >the documentation that says SP2 only. The problems with using the >download cable has been worked out and the new version 6.0 or 6.1, which >ever it is, will document the wider version support. > Yes, 6.1i will be officially support on SP2, 3, and 4. Steve > > >Article: 59233
> > I'm a newbie myself, but I think you might want to take the ale_n out of the > process parentheses. > > Jim > The items in the parentheses are what is know as a sensitivity list, this means that anything listed (in the parentheses) will trigger the execution of the process. Removing ale_n from the sensitivity list will mean that this process will only execute when reset changes state, and will ignore ale_n. This is not the desired result. Ian's suggestion is probably the best way to get around this problem.Article: 59234
In article <Bhf_a.212$Ub5.29202718@newssvr21.news.prodigy.com>, Steve Casselman <sc_nospam@vcc.com> wrote: >> Come on, the USPTO patent examiners wouldn't know prior art if it came >> up and bit them on the ass, mostly because the system largely relies >> on what the patent filer cites! >> -- >> Nicholas C. Weaver nweaver@cs.berkeley.edu > >It is not up to the examiner to know all the prior art in a field it is up >to the inventor. The inventor is supposed to be such an expert in his field >that he's gone and invented something. The inventor is obliged to collect >all the prior art and present it to the examiner. The examiner also has >prior art at his disposal but is only presumed to know enough of the art to >determine if this is a new and useful invention. Which is, of course, a BIG &@#$2#$)(ing problem, as the inventor may lie, gloss over, or just through ignorance, neglect huge hunks of prior art. And without a cost-effective way of interested third parties to attack the patent after being granted, one gets this huge minefield of garbage. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59235
I've seen weirdness when using gates with a large number of inputs. Try breaking the 8 input gates into cascaded 4 input and 5 input gates. The synthesizer should turn this into a single 8 input gate. Jon Elson wrote: > > Hello, > > I have Xilinx ise 4.1.03i, and ran into a wierd problem I haven't seen > before. > > I have a multi-page schematic that I'm trying to compile to an XC95xx > CPLD. It has > 2 8-input or gates on one sheet, and another one on a different sheet. I > get the following > message when doing the synthesize process : > > ERROR:HDLParsers:3340 - Project file master.prj names two source files, > D:/nchem/mothbrd/Motherboard/mb2.vhf and D:/nchem/mo > thbrd/Motherboard/mb1.vhf, that both define the same primary unit, > work/OR8_MXILINX > ERROR:HDLParsers:3340 - Project file master.prj names two source files, > D:/nchem/mothbrd/Motherboard/mb2.vhf and D:/nchem/mo > thbrd/Motherboard/mb1.vhf, that both define the same primary unit, > work/OR8_MXILINX/SCHEMATIC > > Looking into the .vhf files, I see the OR8_MXILINX is defined as an > entity, and later as a component, in > both of these files. This doesn't seem to be out of the ordinary, it > looks just like the other standard library > definitions. > > Does anyone have any suggestions? > > Thanks, > > Jon > -- Marc Guardiani To reply directly to me, use the address given below. The domain name is phonetic. fpgaee81-at-eff-why-eye-dot-netArticle: 59236
> Which is, of course, a BIG &@#$2#$)(ing problem, as the inventor may > lie, gloss over, or just through ignorance, neglect huge hunks of > prior art. > > And without a cost-effective way of interested third parties to attack > the patent after being granted, one gets this huge minefield of > garbage. > -- Yes big problem. An inventor should think "if my patent is worth anything someone will find all the prior art." There is a point after the patent is accepted and when it is issued that would be a good time for that some kind of public flogging of the patent. SteveArticle: 59237
Hi, I'd first suggest taking a look at your Quartus compilation results - does the design meet your 50MHz requirement? The actual f-max you'll see with Nios targeting Apex varies greatly with the peripherals you choose. For example, a 'minimal' system (see the 80_mhz_32 example design) with 32-bit Nios CPU, on-chip memory, and UART, runs at over 80MHz. By contrast (again, targeting Apex silicon), adding cache, SDRAM controller, DMA controller, and a suite of other peripherals will push the f-max down below 33MHz. Additionally, if you have instantiated user-defined peripherals or custom instructions into your SOPC Builder system, the critical path may be located there - so check out your Quartus report! Second, (if you are running an older version of the Nios kit): Originally, off-chip peripherals for Nios were designed with static wait-state, setup, and hold time values for the off-chip peripherals (SRAM, Flash, Ethernet MAC, etc.). In Nios 3.0 (and higher), we changed the way these peripherals are defined to specify setup/hold/wait states in terms of time (e.g. "hold_time=5ns"), just as you'd see on a datasheet. SOPC Builder will then calculate the appropriate number of setup/hold/wait clocks based on this, and your desired F-max -- so unless you wish to edit your system .ptf file to specify the correct setup/hold/wait clocks for your clock speed to each off-chip peripheral, I suggest updating to Nios 3.0. Also, someone else posted inquiring about Cyclone performance. Cyclone (and Stratix) are entirely different architectures from Apex, in terms of memory, logic element architecture, interconnects, and silicon process. As a result, you'll see noted performance improvements with all logic - including that generated by SOPC Builder. As an example, a similar "minimal" system that runs at 80MHz on Apex will achieve over 125MHz targeting Stratix. "Minimal" designs suitable for control applications aside, the question arises about more complex ones (aka "real world" processor systems) ... I went ahead and compiled a few the "standard_32" example designs that ship with our kit (features listed below) to give anyone out there a better idea of performance: Apex (-2X speed grade): Includes 32-bit Nios with hardware multiply, two UARTs, on-chip boot ROM, external Flash & SRAM interfaces, timer, PIO interfaces for pushbuttons, LCD display, and two different LED displays. Requested f-max=33.3Mhz, actual f-max: 57.3Mhz. Cyclone (-7 "ES" speed grade since that's whats on my desk): Includes 32-bit Nios with 4K iCache & dCache, hardware multiply, JTAG-based "OCI" comm/debug port, boot ROM, SDRAM controller, SRAM/Flash/Ethernet MAC interfaces, UART, two timers, PIO for the buttons, LEDs, remote reconfiguration, etc., Compact flash interface, "ASMI" configuration interface (to the new low-cost serial flash ROMs). Requested f-max=50Mhz, actual f-max: 63.8Mhz. Stratix (-6 speed grade): Includes most of the same peripherals as the Cyclone design, but without ASMI memory, and with the addition of 64K of on-chip "M-RAM" memory). Requested f-max=50Mhz, compiled for "speed" in Quartus, actual f-max: 69.3Mhz All of these designs could probably be pushed several % higher if they were constrained properly... the above were just pushbutton compilations. I hope this clarifies any clock speed questions about the Nios kits -- also remember, at the end of the day f-max is indeed a small amount of the performance equation. Because we are in FPGAs, the real power is in how you can augment a CPU with your custom hardware -- that usually beats the pants off of SW performance any day. Jesse Kempa Altera Corp. jkempa at altera dot com maxlim79@hotmail.com (Maxlim) wrote in message news:<a6140565.0308120522.86a33ec@posting.google.com>... > Hello, > I'm trying to operate the nios processor with my > crypto-processor . > The default clock frequency (33.33 MHz) is too slow for fast > cryptosystem performance. I'd tried to get another clock with 50 MHz > frequency through PLL and generate the nios processor with 50 MHz in > the clock setting. The system still can operate correctly with some > simple application on it's own. But when I tried to run some > application involved the hash processor, sometime it'll automatically > jump into Nios peripheral test menu after display message of (return > address is 0x000000) when it try to display the result. (The > appication runs well in system with 33.33 Mhz clock). > The hardware platform I'm using now is Nios development board > populated by an APEX?20KE device (EP20K200EFC484). Is there anyway > that I can solve this problem?Article: 59238
In article <y6g_a.231$sH5.30106886@newssvr21.news.prodigy.com>, Steve Casselman <sc_nospam@vcc.com> wrote: >Yes big problem. An inventor should think "if my patent is worth anything >someone will find all the prior art." There is a point after the patent is >accepted and when it is issued that would be a good time for that some kind >of public flogging of the patent. I agree. What I think is necessary is an "offensive" mechanism: A legal challange to the patent-holder, where the challanger has to put up a bond (so it is forfeit if failed). This way, there is a limited downside for someone who wants to infringe on the patent, by shooting it down in advance. This probably shouldn't have a limited window, as a patent may not be worth infringing for a few years, even if it was questionably granted in the first place. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59239
Dear all I am using Xilinx Foundation 3.1i to implement my design into XSV board and debug using hardware debugger. I am trying to instantiate readback symbol in my design using this file : library IEEE; use IEEE.std_logic_1164.all; library virtex; use virtex.components.all; entity rdbk is port ( rt, clk : in STD_LOGIC; rd, rip_p : out STD_LOGIC ); end rdbk; architecture xilinx of rdbk is begin U0: RDBK port map (TRIG => rt, DATA => rd, RIP => rip_p); U1: RDCLK port map (I => clk); end xilinx; But I found these errors at implementation steps : Error L-3/C0 : #0 Error: :/Xilinx/active/projects/and3_gat/readback.vhd line -3 Library logical name VIRTEX is not mapped to a host directory. (VSS-1071) (FPGA-hci-hdlc-unknown) Error L4/C0 : #0 Error: E:/Xilinx/active/projects/and3_gat/readback.vhd line 4 No selected element named COMPONENTS is defined for this prefix. (VSS-573) Error L13/C0 : #0 Error: E:/Xilinx/active/projects/and3_gat/readback.vhd line 13 The intermediate file for entity RDBK is not in the library bound to WORK. (VSS-1084) What do they mean ? I really apreciate the feedback from all of you. Regards Nyoman YaniArticle: 59240
"Avrum" <avrum@REMOVEsympatico.ca> wrote in message news:<ZwSZa.4445$Z03.243334@news20.bellglobal.com>... > Have you ever said something when you mean the exact opposite? That's what I > did here... > > Please change the sentence to read "The ASYNC reset of a flip-flop is LEVEL > sensitive" (the rest of the description makes more sense when this error is > corrected). > > Sorry, all. > > Avrum > > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3F37EC42.BF4752C1@xilinx.com... > > Avrum, I agree 99%, but please do not call the asynchr. reset edge > > sensitive. It is really the level that resets (and holds reset) the > > flip-flop. I suppose it was a typo of yours... > > > > Peter Alfke, Xilinx > > =========== > > Avrum wrote: > > > > > > There certainly is a potential for failure here. > > > > > > The ASYNC reset of a flip-flop is edge sensitive - as long as the signal > is > > > asserted, the flop ignores the D and CLK input.......,: I agree, the RESET is Level Sensitive but, why our coding style is like this for asyn-reset flip flop always @(posedge clk or negedge rst_n) begin end Does it mean, the reset is negative edge sensed???? And more over, for recovery should we synchronize the reset as such else, we need to ensure only the releasing time of reset is not happening very close to clock edge. Regards, MuthuArticle: 59241
Quartus compilation results - does the design meet your 50MHz
requirement?
Wait-state, setup, and hold time values for the off-chip peripherals
Hello,
Thanks for fast response.
The message in the Quartus compilation report is all timing
requirement is met.
The version of Quartus and SOPC Builder I'm using now is 2.2 SP2
and 3.02. I'm not adding interface to the user defined peripheral or
adding the peripheral into the SOPC library. It's difficult to
communicate or access the peripheral through the memory map allocated
by SOPC Builder due to unknown arrangement of the I/O port.
I'm using the primitive way by adding PIO interface to the
system for communication between the nios and user processor. It seem
like the error will occur while the system try to transfer data to the
host pc through UART. Is it the wrong setting in the UART that cause
this problem?
Article: 59242"Steve Lass" <lass@xilinx.com> wrote in message news:3F39816B.2060200@xilinx.com... > rickman wrote: > > > >Correct me if I am wrong, but this is not Linux exactly. It is Redhat > >and only one specific version of Redhat if I am not mistaken. > > > Redhat 7.3 and 8.0 will be officially supported. > Exactly - it will not officially support Linux, but only two particular versions of one distribution. Redhat is one of the more popular distros in the US, but it is not the most popular (at least, for desktops/workstations) in many other parts of the world, and you are not even looking at the most recent versions. Before you can really say you official support Linux, rather than just a couple of specific versions, you should be happy to support installation on at least Redhat, Suse, Mandrake, Debian for several versions, including the latest ones. This will also mean you can be confident of it working on almost all systems, except perhaps very old or obscurely configured ones, although no one would expect a supplier to test their softare on every combination! However, even support for just a couple of distro versions is a big step forward, and we can hope it is the start of an on-going commitment to linux support for the tools. Perhaps once the webpack is available for linux, you'll provide information and guidelines on installation on other distros that are not officially supported by xilinx - you can be sure there will be users willing to test it for you.Article: 59243
mbmsv@yahoo.com (Mike M) writes: > Thanks to everyone who contributed to this discussion. I am currently > having technical difficulties posting to the Usenet, so please forgive > me for the delay. BTW, does anyone knows of a good free news server > that would allow posting? Google is very slow to reflect even the > messages that have been posted through it and all too frequently > doesn't show some of the posts at all (it happened to Avrum's posts > this time). I am using newssvr20-ext.news.prodigy.com for reading, but > it doesn't allow posting... > > /Mikhail I've been using "News.CIS.DFN.DE" since our corporate server went away. Seems reliable, allows posting, carries the groups I'm interested in... Sign up at by pointing a web browser at that address IIRC. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 59244
I remember 30 years ago a mate of mine ran a fine white elephant** simulation on a mainframe ... he always ran it overnight so he left the limits so fine he knew it would take 4 or 5 hours to run. Certain days it would seem to crash and certain days it would run... Turns out one of the sysadmins would throw it off the machine because "it didn't seem to be doing anything" I once simulated a digital circuit for over 30 days... on a PC that no-one was using so an hour or so is fine... there are approaches the chip designer can take to improve that but why should he since computer time is cheap? Cheers Ian Mccrum ** finite element On 8 Aug 2003 12:17:33 -0700, dshesnicky@yahoo.com (Don S) wrote: >I'm a sysadmin looking at a problem that a designer is having with >slow turn around times in Altera Quartus. The turn around time on a >compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus >version is 2.1 running on Win2K SP2. > >The bulk of the time is spent in Logic Synthesis and the Fitter. >If we just bring up the task manager it shows that we have not tapped >the memory but the cpu is pegged. > >There is apparently a way to lock down the layout of certain blocks >and/or do an incremental compile so that everything would not have to >be re-synthesised but the designer says that it doesn't seem to work >correctly. > >Any pointers would be greatly appreciated. > >DonArticle: 59245
Hi guys, I'm trying to simulate a block-based design with Altera's Quartus II V3.0 Web version, however I cannot seem to simulate beyond 100ns irrespective of what end points I set for the default and for the current project. I've also tried editing the vector waveform file timing parameters after generation and Quartus disregards these and ends the simualtion at 100ns. It seems far too controlled to be a bug so I can only assume its a limitation of the free version. Can anyone confirm this? If it is a limitation of the free version are there any *reliable* third party simulators for reasonable money? I'm sitting on my hands as far as this project goes until I resolve this. Kindest regards, Chris Bailes (Design Engineer, Studio Systems Electronics LTD).Article: 59246
"Chris" <chris.bailes@myrealbox.com> ha scritto nel messaggio news:bc923adb.0308130056.50b1f5b@posting.google.com... > Hi guys, > > I'm trying to simulate a block-based design with Altera's Quartus II > V3.0 Web version, however I cannot seem to simulate beyond 100ns > irrespective of what end points I set for the default and for the > current project. I not yet tried version 3, but the past free version does'nt have such restrictions. However 100 ns is the default limit, but I can change it as I want.Article: 59247
I also use News.CIS.DFN.DE and am happy. However, a month or so ago, on this server I was unable to get comp.arch.fpga which forced me to look for other free servers and I found couple of them (one of them was 203.99.143.60, I do not recall their name)...but as pointed by Mike, it doesn't show all posts sometimes. I'm glad News.CIS.DFN.DE has this group back now... "Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:ulltyezgw.fsf_-_@trw.com... > mbmsv@yahoo.com (Mike M) writes: > > > Thanks to everyone who contributed to this discussion. I am currently > > having technical difficulties posting to the Usenet, so please forgive > > me for the delay. BTW, does anyone knows of a good free news server > > that would allow posting? Google is very slow to reflect even the > > messages that have been posted through it and all too frequently > > doesn't show some of the posts at all (it happened to Avrum's posts > > this time). I am using newssvr20-ext.news.prodigy.com for reading, but > > it doesn't allow posting... > > > > /Mikhail > > I've been using "News.CIS.DFN.DE" since our corporate server went > away. Seems reliable, allows posting, carries the groups I'm > interested in... > > Sign up at by pointing a web browser at that address IIRC. > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 59248
"Ken Morrow" <junk@not_morro.co.uk> wrote in message news:Hod_a.2853$z7.464671@wards.force9.net... > I have the standard sort of circuit from the Xilinx App note driving an off > chip clock:- > > Main clock comes onto chip through an IBUFG to CLKIN of the DLL > > CLK0 from the DLL is fed off the chip through an OBUFT. > > The output of the OBUFT, which is on a global clock pin, is fed back in via > an IBUFG to form CLKFB of the DLL. > > This seems to work fine. > > Main clock to output clock delay is constrained to <5 ns and this constraint > is achieved. > > > > Next I wanted to have 4 off chip clock outputs, timed as close as possible > to the first one.. > > I buffered the CLK0 from the DLL with a BUFG before the OBUFT to try to > ensure that there was low skew between the 4 off chip clock outputs. > > The main clock to external clock delay increased to 10nS and failed the > constraint. > It seemed that the router had used a mixture of global and other routing to > get the CLK0 to the various OBUFT, > and that the other routing was slow. > > I removed the BUFG and the delay then passed my <5ns constraint without > probs, despite using non-global routing. > > I am puzzled? Am I overlooking something? > > (Target device is a Virtex II 6000) > > Many Thanks, > > Ken. > Thinking about it further, even if the delay was 10ns, the DLL should have removed it. I would have expected very little delay from the main clock to the output of the OBUFTs, wether or not I have the BUFG in the way. Seems OK without the BUFG, but not with.Article: 59249
Hi Mates I am getting following errors when I start simulating my design. Delta count overflow - stopped. Try to increase the iterations limit in simulator preferences. # Fatal error occurred during simulation. How to remove this error ? Thanking you in advance . Isaac
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