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> Martin Schoeberl wrote: > > > > OK, I'll try it here: For sale: > > > > 6 pcs Altera EP1K50TC144-3 > > 7 pcs Altera MAX7032AETC44-10 > > ca. 130 pcs async RAM 128kBx8 > > ca. 15 boards with ACEX 1K50 + 128 kB RAM + 512 kB Flash + MAX for > > config from Flash > > I might be interested in one or two of the ACEX boards. Is there any > way to connect this board to external signals? In particular I would > want to interface it to an ARM IO bus and a PC/104 (ISA) bus. This > would be a nice test jig for some FPGA code I am doing. It might help > me save a board spin on my board. > It's this board: http://www.jopdesign.com/board.jsp There you can find a picture and schmatics. MartinArticle: 59426
Jay, XPLD and XPGA have the same technology called ispXP, that has the EECMOS and the SRAM in the same die. However, the architecture of these two parts is different: the XPLD part has a CPLD architecture, whereas the XPGA has an FPGA architecture. In the XPLD that basic block is the MFB (multi function block) that used to be called GLB that were based on macrocells. Now, since the former macrocell can be also memory thay are called MFB. Paul "Jay" <yuhaiwen@hotmail.com> wrote in message news:<bhs27r$2ju3j$1@ID-195883.news.uni-berlin.de>... > Hi Paul, > > Thanks. > It seems XPLD is something like the XPGA, which is also based on SRAM and > EECMOS. > > Jay > "Paul Sereno" <paul_sereno@hotmail.com> > ??????:3d7510b4.0308181129.2ce2f33f@posting.google.com... > > Jay, > > > > Basically, the XPLD is a CPLD with the option of using the MFB (former > > GLB) as memory (Dual Port RAM, Single Port RAM, FIFO, CAM, etc). This > > is due to the fact that the logic is actually implemented in SRAM > > cells (like FPGAs). The part has the EE memory integrated in the same > > die. After programming the EE, the SRAM is configured in less than > > 200us (like almost any CPLD), what is called instant-on. > > Another good point is that the software is free from the Lattice > > website. > > > > Hope this helps, > > > > Paul > > > > "Jay" <yuhaiwen@hotmail.com> wrote in message > news:<bhesmv$sdl$1@ID-195883.news.uni-berlin.de>... > > > Hi all, > > > > > > I only have used xc9500 and coolrunnerII before, and we all know such > CPLDs > > > has so little FF resources. > > > For my current applications I need to map some memorys and I think > ispXPLD > > > is what I'm looking for. > > > But before I start my work on it, I'd like make something clear: > > > 1.It sounds great that ispXPLD has plennty of memory resources, and > that's > > > what I want most. So what's the payoff compared with common CPLDs, cost? > > > performance? > > > 2.ispXPLD has a new architecture MFB which I'm not familiar with. From a > > > designer's point of view, is there any difference between XPLD and CPLD? > Do > > > I need extra knowledges or skills? > > > > > > Thanks.Article: 59427
To generate a random number, you need a random number generator. Duh :-)
Try searching for RNGs on google. General linear feedback shift register
based RNGs are probably the easiest to implement on an FPGA. Below is some
code I wrote the other day that generates 32-bit random numbers.
Cheers
Michael.
--**************************************************************************
***
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LFSR is
port(
Clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
F : out STD_LOGIC
);
end LFSR;
architecture LFSR of LFSR is
signal SR : STD_LOGIC_VECTOR (25 downto 1);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
SR <= D & SR(25 downto 2);
end if;
end process;
Q <= SR(1);
F <= SR(8);
end LFSR;
--**************************************************************************
***
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RNG is
port(
Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
InputEnable : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR(32 downto 1);
Output : out STD_LOGIC_VECTOR(32 downto 1)
);
end RNG;
architecture RNG of RNG is
component LFSR
port(
Clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
F : out STD_LOGIC
);
end component;
-- magic vectors
constant MAG_FEEDBACK : STD_LOGIC_VECTOR := X"8EBFD028";
constant MAG_OUTA : STD_LOGIC_VECTOR := X"2B5B2500";
constant MAG_OUTB : STD_LOGIC_VECTOR := X"DB8B0000";
signal D, F, Q, shifted, feedback : STD_LOGIC_VECTOR(32 downto 1);
-- output processing signals
signal outa, outb : STD_LOGIC_VECTOR(32 downto 1);
begin
LFSRs : for i in 32 downto 1 generate
ShiftRegister : LFSR port map (Clock, D(i), Q(i), F(i));
end generate;
-- twist and feedback
shifted <= '0' & Q(32 downto 2);
feedback <= (F xor shifted) when (Q(1) = '0') else
(F xor shifted xor MAG_FEEDBACK);
D <= feedback when InputEnable = '0' else Input;
-- produce output
outa <= Q xor ((Q(25 downto 1) & B"0000_000") and MAG_OUTA);
outb <= outa xor ((outa(17 downto 1) & B"0000_0000_0000_000") and
MAG_OUTB);
Output <= outb xor (X"0000" & outb(32 downto 17));
end RNG;
--**************************************************************************
***
library IEEE;
use IEEE.std_logic_1164.all;
entity Testbench is
end Testbench;
architecture Testbench of Testbench is
component RNG
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
InputEnable : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR;
Output : out STD_LOGIC_VECTOR
);
end component;
signal Reset : STD_LOGIC;
signal Clock : STD_LOGIC;
signal InputEnable : STD_LOGIC;
signal Input, Output : STD_LOGIC_VECTOR (32 downto 1);
begin
RNG1 : RNG port map (Reset, Clock, InputEnable, Input, Output);
-- clock
process
begin
Clock <= '0';
wait for 5 ns;
Clock <= '1';
wait for 5 ns;
end process;
-- reset RNG
process
begin
Reset <= '0';
wait for 2 ns;
Reset <= '1';
wait for 10 ns;
Reset <= '0';
wait for 10000 ns;
end process;
-- seed RNG
process
begin
Input <= (others => '0');
InputEnable <= '1';
wait until Clock'Event and Clock = '1' and Reset = '0';
wait for 1 ns;
-- seed RNG with any old stuff
Input <= X"95f24dab"; wait for 10 ns;
Input <= X"0b685215"; wait for 10 ns;
Input <= X"e76ccae7"; wait for 10 ns;
Input <= X"af3ec239"; wait for 10 ns;
Input <= X"715fad23"; wait for 10 ns;
Input <= X"24a590ad"; wait for 10 ns;
Input <= X"69e4b5ef"; wait for 10 ns;
Input <= X"bf456141"; wait for 10 ns;
Input <= X"96bc1b7b"; wait for 10 ns;
Input <= X"a7bdf825"; wait for 10 ns;
Input <= X"c1de75b7"; wait for 10 ns;
Input <= X"8858a9c9"; wait for 10 ns;
Input <= X"2da87693"; wait for 10 ns;
Input <= X"b657f9dd"; wait for 10 ns;
Input <= X"ffdc8a9f"; wait for 10 ns;
Input <= X"8121da71"; wait for 10 ns;
Input <= X"8b823ecb"; wait for 10 ns;
Input <= X"885d05f5"; wait for 10 ns;
Input <= X"4e20cd47"; wait for 10 ns;
Input <= X"5a9ad5d9"; wait for 10 ns;
Input <= X"512c0c03"; wait for 10 ns;
Input <= X"ea857ccd"; wait for 10 ns;
Input <= X"4cc1d30f"; wait for 10 ns;
Input <= X"8891a8a1"; wait for 10 ns;
Input <= X"a6b7aadb"; wait for 10 ns;
InputEnable <= '0';
wait for 10000 ns;
-- numbers are generated with Clk
end process;
end Testbench;
--**************************************************************************
***
"jaideep" <jaideep@sasken.com> wrote in message
news:c4312ee4.0308192008.7967ee5d@posting.google.com...
> Hi All,
>
> I have a very elementary question? How do we generate a random
> address( in VHDL) using a integer variable say, i from 0 to 4095(say)?
> Can we read/write from/to a random address of a memory?
>
> TIA
>
> Jaideep
Article: 59428John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bhrpmp$hda$1@bunyip.cc.uq.edu.au>... > Hi folks, > > In Xilinx FPGA editor it is possible to assign probes to signals - a > very useful feature. However as far as I'm aware it is only possible > for probes to take a given signal and bring it out to an IOB. > > I'm interested in a more general capability to take an arbitrary > internal signal and bring it to the top level of a design without having > to modify the original vhdl (which may not even bve available), where it > would be available to other modules in the design. just use ChipScope very useful ! optionally you can write your own embedded logic analyzer core and connect your signals to it. but xilinx tools optimize things away sometimes, as example if you connect a long shift register to BSCAN then if the max fanout is exceeded than XST connects part of the shiftregister clk pins to GND as it doesnt know that BSCAN has 'hidden' inputs and clk sources (coming from JTAG pins and JTAG TAP) antti anttiArticle: 59429
rickman <spamgoeshere4@yahoo.com> writes: > After reading a post by Jonathan Bromley on the VME interface, I thought > I would see if anyone had any comments on a design I am doing. I have > to interface to the PC104 bus which is just the PC ISA interface on a > small board. After beating my head against the wall for a couple of > trys, I decided to dump the BCLK since it is not really part of the spec > and treat the command stobes as async lines. My design is further > complicated by the fact that my system clock ranges from 2 MHz to 50 MHz > to allow power conservation. > > I finally decided that the only way to get the job done was to treat the > command strobes as clock lines. Read cycles are done normally by muxing > the data from various registers based on the address lines and the > tristate outputs are controlled with the strobes. Writes to simple > registers are done on the trailing edge of the write strobe. For reads > that need to update or clear bits, a strobe is generated that is sync'ed > to the system clock using a circuit to remove the metastable problem. > The same circuit works with writes that need to set flags or control > FIFOs. > That sounds about what we did for a PC/104 interface (some years ago, so the memory is a bit woolly - sorry!) I couldn't see a sensible way to use the BCLK line. We did it in a MAX7064 IIRC - everything worked fine once we dumped the Max plus II VHDL compiler and did it in schematics and AHDL! <snip> Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 59430
i am about to create a parallel cable to download to a CPLD. i've read that many people have had problems. could someone please send me a schematic of the cable that he uses and actually works? thank youArticle: 59431
Paul, I tried to build a FIFO using HDL myself. It was synthesized and mapped into FFs. It seems that if I want it to be implemented by MFB, I must instantiate the macros Lattice provided. Jay "Paul Sereno" <paul_sereno@hotmail.com> ??????:3d7510b4.0308182144.6d52afa2@posting.google.com... > Jay, > > XPLD and XPGA have the same technology called ispXP, that has the > EECMOS and the SRAM in the same die. However, the architecture of > these two parts is different: the XPLD part has a CPLD architecture, > whereas the XPGA has an FPGA architecture. > In the XPLD that basic block is the MFB (multi function block) that > used to be called GLB that were based on macrocells. Now, since the > former macrocell can be also memory thay are called MFB. > > Paul > > "Jay" <yuhaiwen@hotmail.com> wrote in message news:<bhs27r$2ju3j$1@ID-195883.news.uni-berlin.de>... > > Hi Paul, > > > > Thanks. > > It seems XPLD is something like the XPGA, which is also based on SRAM and > > EECMOS. > > > > Jay > > "Paul Sereno" <paul_sereno@hotmail.com> > > ??????:3d7510b4.0308181129.2ce2f33f@posting.google.com... > > > Jay, > > > > > > Basically, the XPLD is a CPLD with the option of using the MFB (former > > > GLB) as memory (Dual Port RAM, Single Port RAM, FIFO, CAM, etc). This > > > is due to the fact that the logic is actually implemented in SRAM > > > cells (like FPGAs). The part has the EE memory integrated in the same > > > die. After programming the EE, the SRAM is configured in less than > > > 200us (like almost any CPLD), what is called instant-on. > > > Another good point is that the software is free from the Lattice > > > website. > > > > > > Hope this helps, > > > > > > Paul > > > > > > "Jay" <yuhaiwen@hotmail.com> wrote in message > > news:<bhesmv$sdl$1@ID-195883.news.uni-berlin.de>... > > > > Hi all, > > > > > > > > I only have used xc9500 and coolrunnerII before, and we all know such > > CPLDs > > > > has so little FF resources. > > > > For my current applications I need to map some memorys and I think > > ispXPLD > > > > is what I'm looking for. > > > > But before I start my work on it, I'd like make something clear: > > > > 1.It sounds great that ispXPLD has plennty of memory resources, and > > that's > > > > what I want most. So what's the payoff compared with common CPLDs, cost? > > > > performance? > > > > 2.ispXPLD has a new architecture MFB which I'm not familiar with. From a > > > > designer's point of view, is there any difference between XPLD and CPLD? > > Do > > > > I need extra knowledges or skills? > > > > > > > > Thanks.Article: 59432
http://toolbox.xilinx.com/docsan/3_1i/data/common/hug/chap01/hug01007.htm Thanassis Roubies wrote: > i am about to create a parallel cable to download to a CPLD. i've read > that many people have had problems. could someone please send me a > schematic of the cable that he uses and actually works? thank you >Article: 59433
It makes sense. I guess if I use the Quartus simulator for the whole model (FPGA+SRAM) it will try first to fit the SRAM into the Stratix. Thanks a lot, Chris "Subroto Datta" <sdatta@altera.com> wrote in message news:ca4d800d.0308181025.2643ba76@posting.google.com... > "Chris Saturn" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bhqmi9$r8k$1@sunnews.cern.ch>... > > Hi to all, > > > > > > > > I am really new to FPGA's so I am a little confused over a lot of stuff yet. > > > > > > > > In Quartus II, when you use the dcfifo from the Megawizard the ram can be > > only internal or could be an external module? > > > > For example if i want to use an external SRAM module to read and write data > > with a Stratix? > > > > Will the complete design be in Quartus or just the inputs and the outputs > > going to the SRAM? > > > > > > > > If not, how can I simulate if they are working together? > > > > > > > > Thanks a lot for your time.. > > > > > > > > Chris > > Hi Chris, > > If you use the DCFIFO or for that matter any of the megawizards, the > logic will be implemented inside the FPGA. There is a single VHDL > output file (vho) or Verilog output file (vo), written out by Quartus > that you can simulate, using a VHDL/Verilog simulator like Modelsim. > If you do not want to use a VHDL/Verilog simulator you may also use > the simulator built into Quartus. > > If you want to simulate an external memory, you will need to bring out > the interface pins to the external memory, as primary inputs/outputs > of the FPGA model. You will then need another simulation model for the > memory, from the memory vendor, which should be hooked up to the FPGA > model. This composite model (FPGA+external memory) can then be > simulated using a VHDL/Verilog simulator. > > - Subroto Datta > Altera Corp.Article: 59434
Greg, Thank you for your thoughtful and knowledgeable reply. Does the device enter user mode immediately after it is configured, or only after the entire chain is configured ? FYI, I did post a service request at Altera's mySupport website, the request number is 10334600 (more general questions than a specific instance). The reason I'm here is that I was not able to get my questions answered, and the service request was unceremoniously closed on Aug 7. Thanks! -rajeev-Article: 59435
I have a user defined logic with a 36 bit data width. How can I connect it to the NIOS processor using SOPC builder? How can I interface the 32 bit NIOS processor with a 36 bit SRAM too? please advice.Article: 59436
"Michael Chan" <s354025@student.uq.edu.au> wrote in message news:<bht008$oeu$2@bunyip.cc.uq.edu.au>... > Hi, I'm designing a board that contains a VirtexEM amongst other stuff, and > I want to interface a PC parallel port to the FPGA so I can do some simple > I/O from the pc to the board and vice versa (I want to use this link to > debug hardware I program the fpga with). I'm wondering if anyone has done > something simmilar, and are there any issues I should be aware of? Can the > parallel port strobe signal strobe data into the FPGA? Would a serial > interface be easier for my purposes (given I would also have to implement a > UART on the FPGA)? Parallel Port (ie PC Printer port) seems "easy" but to get it correct is actually not so simple. and cable is heavy :) use FT245 ! www.ftdichip.com looks like serial port from usb side ad like strobed parallel from the other side. cheaper than implementing correct LPT support at the end. of course you can do uart in FPGA and only add level converters anttiArticle: 59437
"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:3f416e93@dnews.tpgi.com.au... <snip> > The jitter generated by this particular divider is actually 38ns, which > is *half* of one period of the input clock. 77ns (one period) is the > upper limit for an arbitrary frequency division, but often the jitter is > much less. </snip> The periods are 62.462 us and 62.538 us which, when you account for rounding, is a 77 ns difference. The values I'm used to are either "peak-to-peak" jitter which would encompass the entire 77 ns value and "rms jitter" which is a good value for judging random jitter when the observation times for jitter peak-to-peak values are too long. Did I miss something? If you're talking "deviation from ideal" then it's +/- 38 ns which is still 77 ns peak to peak. In some sawtooth jitter values you get from arbitrary DDS, the "deviation from ideal" would step slightly from cycle to cycle for many cycles until - wham - you get a full correction of nealy 77 ns for a 13MHz clock. In the 16 kHz case the massive correction of 77 ns is *every* cycle.Article: 59438
Hey Austin,
Such are the perils of posting on Google! The extended time
delay before posts appear makes me look daft(er) sometimes!
cheers, Syms.
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F415CC8.E3D76449@xilinx.com>...
> Symon,
>
> Actually the "Xilinx Guy" (Peter) suggested using a simple clock doubler.....
>
> The DCM will not operate in DLL mode below 24 MHz, so one has to use the DFS CLKFX output with M=2,
> and D=1 if you want to double that way (and it works fine if you have a DCM to spare in the V2, V2P,
> or the S3).
>
> Austin
>
> Symon wrote:
>
> > Hi David,
> > If your 13 MHz (I assume you mean MHz not mHz!!) clock has a
> > 50% duty cycle, you could use both edges of it to get 16kHz spot on.
> > Might be simpler than the DDFS.
> > The Xilinx guys will suggest using a DCM to double the clock
> > frequency. You need to use the CLKFX output as the clock in is less
> > than 25MHz IIRC. Or, Peter Alfke as has some dodgy circuit ;-) to
> > double clocks, check out Xilinx's Tech Exclusives page.
> > All the best, Syms.
> >
> > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:<bhr7jv$dl7$1@home.itg.ti.com>...
> > > Hi everyone,
> > > I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
> > > post on DDFS but I still don't understand how precise is the output clock.
> > > Fout = Fclock * N / 2^k
> > > If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
> > > However, I read that there is jitter on the output clock up to the input
> > > clock period. I thus wonder if this <complicated> clock divider would really
> > > yield better result than generating a pulse at every 812/813 (alternating)
> > > input clock pulse. On average, this is a 16khz clock, and it jitters by one
> > > input clock period. Am I missing something here?
> > > Thanks
> > > David
Article: 59439Michael Chan <s354025@student.uq.edu.au> wrote in message news:bht008$oeu$2@bunyip.cc.uq.edu.au... > Hi, I'm designing a board that contains a VirtexEM amongst other stuff, and > I want to interface a PC parallel port to the FPGA so I can do some simple > I/O from the pc to the board and vice versa (I want to use this link to > debug hardware I program the fpga with). I'm wondering if anyone has done > something simmilar, and are there any issues I should be aware of? Can the > parallel port strobe signal strobe data into the FPGA? Would a serial > interface be easier for my purposes (given I would also have to implement a > UART on the FPGA)? > Thanks. > Michael. Michael, If you just want to communicate with registers in your design as opposed to serially clocking the config data in the FT245 is what you want (as Antti says above/below). I sell a small USB interface board designed for interfacing with the BurchED FPGA development board which may be of interest, unit price is £30. The only limiting factor might be that it needs 5V. See the downloads page of my web-site for details. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 59440
Hi John,
Just a thought, but I wonder if there's a way to use the probe
feature to take the signal to the output side of an IOB, and to have
your magic sniffer circuit connected to the input side of the IOB. I
have a nasty feeling that the tool only lets you use ununsed IOBs for
probes. One way round this is, you could connect spare IOBs together
external to the device in pairs. One of the pair would be the probe
output, the other the sniffer input.
Not especially elegant, uses IOBs => lower bandwidth, but
thought I'd suggest it anyway. Solves the optimised away problem.
Another idea is that ChipScope works fairly well, as Antti
suggests, but you need a P&R each time you change things using the
Xilinx tool flow. Maybe you could write a script generator in perl to
make scripts for swapping signals on the chipscope stuff in FPGA
editor? Along the lines of :-
UNROUTE OLD_PROBE_SIGNAL
ROUTE NEW_PROBE_SIGNAL
If you have success, however you do this, please post! It'd be
v. useful!
Thanks, Syms.
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bhrpmp$hda$1@bunyip.cc.uq.edu.au>...
> Hi folks,
>
> In Xilinx FPGA editor it is possible to assign probes to signals - a
> very useful feature. However as far as I'm aware it is only possible
> for probes to take a given signal and bring it out to an IOB.
>
> I'm interested in a more general capability to take an arbitrary
> internal signal and bring it to the top level of a design without having
> to modify the original vhdl (which may not even bve available), where it
> would be available to other modules in the design.
>
> For example, say I want to create a hardware core that monitors the
> internals of a microblaze system, e.g. I want to "listen" on the
> instruction fetch. In FPGA editor I can determine the full signal names
> that are necessary - can I then somehow get those signals to my
> "sniffer" module and proceed like that?
>
> Thanks,
>
> John
Article: 59441I do not understand the continuing discussion about 30 or more ns of jitter. I gave you a circuit that gets the worst-case jitter down to <10 ns, and if you use the DCM frequency doubler, the jitter will be measured in picoseconds. So what's the 30-ns masochism about? Peter Alfke ======================= Peter Alfke wrote: > > If you really care about nanosecond jitter, here is the best solution: > Double your 13 MHz input frequency and then divide the result by 1625. > If you use "my" frequency doubler (TechXclusives, 6 easy pieces), you > end up with the perfect frequency and a jitter equal to the duty-cycle > error of the 13 MHz, probably less than 10 ns. The whole circuit costs > you a dozen flip-flops. > Peter Alfke, Xilinx Applications. > ======================== > David Lamb wrote: > > > > Hi everyone, > > I need to generate a 16khz clock from a 13mhz input clock. I read a lot of > > post on DDFS but I still don't understand how precise is the output clock. > > Fout = Fclock * N / 2^k > > If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock. > > However, I read that there is jitter on the output clock up to the input > > clock period. I thus wonder if this <complicated> clock divider would really > > yield better result than generating a pulse at every 812/813 (alternating) > > input clock pulse. On average, this is a 16khz clock, and it jitters by one > > input clock period. Am I missing something here? > > Thanks > > DavidArticle: 59442
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F41A4F6.E37A7BA3@yahoo.com>...
>
> Anyone had big problems with similar async circuits?
Hey Rick,
I guess loads of us have had a BIG problem with this type of
circuit! Half the time the async circuit works fine, but it always
gets the blame for some other design deficiency! Anyway, one circuit
I've used for crossing between clock domains that works well is the
Self Addressing FIFO. See Xilinx APP note XAPP291. The incoming (or
outgoing depending on topology) clock only feeds one clock pin, so no
clock skew problems and no global clock net resource used. Maybe a
little over the top for most designs, but (fairly) safe!
HTH, Syms.
Article: 59443
Hi Jonathan,
I thought about doing this in perl a while back but didn't get
round to it. Sounds like Tcl could be promising, I like 'easy'! Do you
have any recommendations of where a hardware engineer could start to
learn about Tcl? Any books you like?
thanks, Syms.
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bhqocr$bvk$1$8300dec7@news.demon.co.uk>...
>
> Consider using Tcl instead. Driving Windows serial ports from
> C/C++ is extremely tiresome, but Tcl makes it easy.
> --
>
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
> Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573 Web: http://www.doulos.com
>
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Article: 59444I have Windows XP at home so I can only install Xilinx Webpack 5.2i. My University has the ISE Foundation 4.1i edition and i want to know if I can simulate designs done from home on Webpack 5.2i on the University's ISE 4.1i edition so I can confirm my designs on the Digilab XLA5 board there. (using spartan XCS10 fpga). As we are beginners I think most of our designs will be schematic based and not VDHL. Obviously ISE 4.1i designs will not run on WebPACK 5.2i but that is not a problem as most of my design will be done from home. If I did not have XP I would just buy the Xilinx University Student 4.2i edition but then again I dont know if that simpler version is directly compatible with ISE 4.1i. Any suggestions? Regards DaveArticle: 59445
Jay, You are right you have to use the macro from Lattice. There is a good technical note describing the memory usage of the XPLD devices: http://www.latticesemi.com/lit/docs/technotes/tn1030.pdf Use the macro to instantiate the memory module in your top level code. In case you are working with VHDL you have to add a ""no optimization" attribtue to the memory module (otherwise it will be removed by the synthesis tool) Depending on the synthesis tool you will use different attribtues. For Exemplar use the following after the component declaration: attribute noopt: boolean; attribute noopt of <memory_module>: component is true; Regards, paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0308182144.6d52afa2@posting.google.com>... > Jay, > > XPLD and XPGA have the same technology called ispXP, that has the > EECMOS and the SRAM in the same die. However, the architecture of > these two parts is different: the XPLD part has a CPLD architecture, > whereas the XPGA has an FPGA architecture. > In the XPLD that basic block is the MFB (multi function block) that > used to be called GLB that were based on macrocells. Now, since the > former macrocell can be also memory thay are called MFB. > > Paul > > "Jay" <yuhaiwen@hotmail.com> wrote in message news:<bhs27r$2ju3j$1@ID-195883.news.uni-berlin.de>... > > Hi Paul, > > > > Thanks. > > It seems XPLD is something like the XPGA, which is also based on SRAM and > > EECMOS. > > > > Jay > > "Paul Sereno" <paul_sereno@hotmail.com> > > ??????:3d7510b4.0308181129.2ce2f33f@posting.google.com... > > > Jay, > > > > > > Basically, the XPLD is a CPLD with the option of using the MFB (former > > > GLB) as memory (Dual Port RAM, Single Port RAM, FIFO, CAM, etc). This > > > is due to the fact that the logic is actually implemented in SRAM > > > cells (like FPGAs). The part has the EE memory integrated in the same > > > die. After programming the EE, the SRAM is configured in less than > > > 200us (like almost any CPLD), what is called instant-on. > > > Another good point is that the software is free from the Lattice > > > website. > > > > > > Hope this helps, > > > > > > Paul > > > > > > "Jay" <yuhaiwen@hotmail.com> wrote in message > news:<bhesmv$sdl$1@ID-195883.news.uni-berlin.de>... > > > > Hi all, > > > > > > > > I only have used xc9500 and coolrunnerII before, and we all know such > CPLDs > > > > has so little FF resources. > > > > For my current applications I need to map some memorys and I think > ispXPLD > > > > is what I'm looking for. > > > > But before I start my work on it, I'd like make something clear: > > > > 1.It sounds great that ispXPLD has plennty of memory resources, and > that's > > > > what I want most. So what's the payoff compared with common CPLDs, cost? > > > > performance? > > > > 2.ispXPLD has a new architecture MFB which I'm not familiar with. From a > > > > designer's point of view, is there any difference between XPLD and CPLD? > Do > > > > I need extra knowledges or skills? > > > > > > > > Thanks.Article: 59446
My apologies if my own continuing discussion of jitter was annoying. I tried to underscore that at 16kHz, the jitter from the dual modulus divider is pretty insignificant. But, to be complete.... While DDS does a good job of giving us our outputs from the MSbit, remember that dividers give us edges, not square waves. The DCM approach is great - quadruple the frequency to 52 MHz and divide by 1625 to get the toggle control for an output flop. No real jitter. 50% duty cycle. Great. Taking a 13 MHz clock and doubling it by using the edges will produce rising edges with 26 MHz timing. Dividing by 1625 gives an event every 16 kHz. Now, doesn't this event want to be a clock? If only a clock-enable is needed, it works great. If jitter on the falling edge doesn't matter, but 50% duty cycle does, having a clock high for 812 cycles and low for 813 works great. If falling edge jitter and duty cycle don't matter, using the MSbit of the divider gives a nice 37% duty cycle square wave with no jitter on the rising edge. With all the qualifications, the 13 MHz doubler isn't a slam-dunk but is a great solution for most requirements. I still think the jitter is insignificant at 0.0012 unit intervals, peak-to-peak. Masochistically yours, - John_H "Peter Alfke" <peter@xilinx.com> wrote in message news:3F425BDF.D28FF25E@xilinx.com... > I do not understand the continuing discussion about 30 or more ns of jitter. > I gave you a circuit that gets the worst-case jitter down to <10 ns, and > if you use the DCM frequency doubler, the jitter will be measured in picoseconds. > So what's the 30-ns masochism about? > > Peter Alfke > ======================= > Peter Alfke wrote: > > > > If you really care about nanosecond jitter, here is the best solution: > > Double your 13 MHz input frequency and then divide the result by 1625. > > If you use "my" frequency doubler (TechXclusives, 6 easy pieces), you > > end up with the perfect frequency and a jitter equal to the duty-cycle > > error of the 13 MHz, probably less than 10 ns. The whole circuit costs > > you a dozen flip-flops. > > Peter Alfke, Xilinx Applications. > > ======================== > > David Lamb wrote: > > > > > > Hi everyone, > > > I need to generate a 16khz clock from a 13mhz input clock. I read a lot of > > > post on DDFS but I still don't understand how precise is the output clock. > > > Fout = Fclock * N / 2^k > > > If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock. > > > However, I read that there is jitter on the output clock up to the input > > > clock period. I thus wonder if this <complicated> clock divider would really > > > yield better result than generating a pulse at every 812/813 (alternating) > > > input clock pulse. On average, this is a 16khz clock, and it jitters by one > > > input clock period. Am I missing something here? > > > Thanks > > > DavidArticle: 59447
>
> MFC is Microsoft Foundation Classes.
> You can also access to the serial port by serial driver API
> function calls. (API = Application Programming Interface)
It's quite easy, if you know the library functions. Use the code sample
below.
Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
#include <windows.h>
#include <stdio.h>
#include <string.h>
unsigned char c;
DCB dcb;
HANDLE hCom;
DWORD dwError;
BOOL fSuccess;
//
// open serial line after
//
hCom = CreateFile("COM1",
GENERIC_READ | GENERIC_WRITE,
0, /* comm devices must be opened w/exclusive-access */
NULL, /* no security attrs */
OPEN_EXISTING, /* comm devices must use OPEN_EXISTING */
0, /* not overlapped I/O */
NULL /* hTemplate must be NULL for comm devices */
);
if (hCom == INVALID_HANDLE_VALUE) {
dwError = GetLastError();
printf("shit CreateFile\n");
exit(-1);
}
/*
* Omit the call to SetupComm to use the default queue sizes.
* Get the current configuration.
*/
fSuccess = GetCommState(hCom, &dcb);
if (!fSuccess) {
printf("shit GetCommState\n");
exit(-1);
}
dcb.BaudRate = 115200;
dcb.ByteSize = 8;
dcb.Parity = NOPARITY;
dcb.StopBits = ONESTOPBIT;
/* use RTS/CTS handshake */
dcb.fOutxCtsFlow = TRUE;
dcb.fRtsControl = RTS_CONTROL_ENABLE;
dcb.fOutxDsrFlow = FALSE;
dcb.fDtrControl = DTR_CONTROL_DISABLE;
dcb.fDsrSensitivity = FALSE;
fSuccess = SetCommState(hCom, &dcb);
if (!fSuccess) {
printf("shit SetCommState\n");
exit(-1);
}
//
// write one byte:
//
WriteFile(hCom, &c, 1, &cnt, NULL);
//
// read one byte:
//
ReadFile(hCom, &c, 1, &cnt, NULL);
Article: 59448Who has current design tools that will maintain legacy 22V10 design using ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before Xilinx swallowed them). Thanks in advance JoeGArticle: 59449
> > Hi, I'm designing a board that contains a VirtexEM amongst other stuff, and > > I want to interface a PC parallel port to the FPGA so I can do some simple > > I/O from the pc to the board and vice versa (I want to use this link to > > debug hardware I program the fpga with). I'm wondering if anyone has done > > something simmilar, and are there any issues I should be aware of? Can the > > parallel port strobe signal strobe data into the FPGA? Would a serial > > interface be easier for my purposes (given I would also have to implement a > > UART on the FPGA)? > > Parallel Port (ie PC Printer port) seems "easy" but to get it correct > is actually not so simple. and cable is heavy :) > > use FT245 ! www.ftdichip.com looks like serial port from usb side > ad like strobed parallel from the other side. cheaper than implementing > correct LPT support at the end. > > of course you can do uart in FPGA and only add level converters > This device looks really promising. One question though: where can I buy it (in low quantities) in the US? Or in Europe? Thanks, Andras Tantos
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