Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 59175

Article: 59175
Subject: Re: a quick searching problem
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Mon, 11 Aug 2003 16:55:36 GMT
Links: << >>  << T >>  << A >>
You are thinking in terms of feeding the vectors into an FPGA in parallel.
That is hardly necessary (unless you generate entire new vectors every
10ns).

Questions you need to answer:

-How quickly are new vectors generated?
-Where will the vectors come from (or be stored)?
-How quickly do you need an answer?
-What is the maximum value of M and N?
-Is it guaranteed that there will be only one matching value for all
possible vector combinations?
-How many different 20 bit values can a vector element have?  Is it a
straight unsigned binary value or some sort of a code that would limit the
number of distinct values to less than 2**20?

Just as an example, if M = N = 512, with the FPGA running at 100MHz, you
could do a brute force comparison of two vectors in 2.6 ms.  Your M = N = 60
example would take 36 microseconds.  Keep in mind, these are worst-case
figures.

For the above use two SelectRAM memories preloaded with your vectors.  You
could load your vectors one word at a time at whatever rate your source
could handle.  If, say, your source happens to be SDRAM connected to the
FPGA you could load the vectors at 133MHz (or 2x with DDR).  Depending on
the width of the data path that would mean one or more 20 bit word per
clock.  No need to consume I/O to pass the vectors in parallel.

So, a rough estimate of a complete load->compare->result cycle would be:
  M = N = 512 ... load = 7.7us; compare = 2.6ms
  M = N = 60  ... load = 0.9us; compare = 36us

Is that fast enough?  You could always run the FPGA faster.

If SDRAM was involved I would probably run the logic at the SDRAM clock (or
2x) rather than an unrelated frequency (like 100MHz).

There are a million possible variations of this concept.  It all depends on
the constraints you have to work within.  A binary search, for example,
would provide a very significant improvement in performance.  You could
replicate the circuit X times in order to obtain a further X-time
improvement in reaching a match.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




"Zhen" <zhenxu2000@hotmail.com> wrote in message
news:7b390929.0308100714.550cc60a@posting.google.com...
> There are two vectors, named V1 and V2, the sizes of which are 1*M and
> 1*N, respectively. We have known that there is at most one common
> element in both vectors. I am looking for the quick algorithm to
> search this common element.
>
> The general algorithm is to compare every element in V1 with each
> element in V2. the comparison complexity will be O(M*N). Is there any
> efficient method to complete it?
> I hope it can be done in FPGA. If M=N=60, and each element is 20 bit
> long,there isn't enough pins for the general search algorithms at one
> time. It need some loops to do it. So I am looking for an efficient
> algorithm and expect that the common element can be found in around
> 10ns~50ns. Is it possible?
> Thanks,



Article: 59176
Subject: Q: async flip-flop reset by a signal from a different clock domain
From: mbmsv@yahoo.com (Mikhail Matusov)
Date: 11 Aug 2003 10:38:39 -0700
Links: << >>  << T >>  << A >>
Hi all,

Is there a danger in doing async reset of a flip-flop by a signal
generated by a state machine running in a different clock domain (than
flip-flop clock)?
I have a bunch of flip-flops that get synchronously written in one
clock domain and they need to be reset from another clock domain. So,
I used async reset... Is this a potential problem? I am having some
misterious random failures and this is one of the suspicious places in
my design...

Thanks,
/Mikhail

Article: 59177
Subject: Re: Pad-to-pad hold time
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 11 Aug 2003 10:54:02 -0700
Links: << >>  << T >>  << A >>
Hold time issues.
Inside the FPGA, the global clock has very little skew, which means
there are no hold-time issues ( clock-to-Q + routing delay + set-up time
) is always longer than any clock skew.

In the I/O input register, the timing relationship is different. Let's
assume that the transmitting chip's output driver and the receiving
chip's input flip-flop use the "same" clock. And let's assume thet the
trasnmitter is pretty fast ( short clock-to-Q). That means the "new
data" will arrive soon after the incoming clock edge. But that clock
edge has to be amplified and distributed in the receiving chip, and it
is still supposed to clock in the "old data".
If the internal clock delay is longer than the incoming data delay, you
end up clocking in the wrong ( the new ) data. The part would have to be
specified with a positive hold time (The old data must be kept valid
beyond the clock edge that changes old data to new data) This is a bad
specification, very difficult to live with.
 
The solution to avoid any posittive hold time requirement is to
artificially delay the incoming data. (which does cause a performance
penalty, since it also increases the set-up time)
But it is better to sacrifice some top performance than to sacrifice
reliability. A hold time violation can cause system failure at any
speed. "Unsafe at any speed", to miquote Ralf Nader.
Inside the chip, this is a non-issue.

Peter Alfke, Xilinx
============================
> 
> Probably stupid question (sorry), but I cannot figure out an answer:
> 
> Xilinx devices has optional delay element in IOB which causes (when
> used) that pad-to-pad hold time is zero.
> Maybe someone could explain me, how to understand this pad-to-pad hold
> time, and when I should use this optional delay element?
> 
> Why does it only affects pad-to-pad hold time and not for example
> pad-register in CLB hold time? Is it because registers in CLBs have
> significantly shorter hold times?
> 
> Thanks!
> 
> --
> Robert P.

Article: 59178
Subject: Re: Q: async flip-flop reset by a signal from a different clock domain
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 11 Aug 2003 11:07:54 -0700
Links: << >>  << T >>  << A >>
Yes, you are violating a cardinal rule:
Never re-synchronize an asynchronous input in more than one flip-flop in parallel.
The solution for you is to take the asynchronous reset signal and
synchronize it in one single flip-flop ( feed it intoD and take it then
from Q to perform the reset.)  If you can afford the increased latency,
you should concatenate two flip-flops to avoid metastabilty problems.

Peter Alfke, Xilinx
=====================
Mikhail Matusov wrote:
> 
> Hi all,
> 
> Is there a danger in doing async reset of a flip-flop by a signal
> generated by a state machine running in a different clock domain (than
> flip-flop clock)?
> I have a bunch of flip-flops that get synchronously written in one
> clock domain and they need to be reset from another clock domain. So,
> I used async reset... Is this a potential problem? I am having some
> misterious random failures and this is one of the suspicious places in
> my design...
> 
> Thanks,
> /Mikhail

Article: 59179
Subject: Virtex "Virtual VCC"
From: lenz19@gmx.de (lenz)
Date: 11 Aug 2003 11:13:45 -0700
Links: << >>  << T >>  << A >>
Hi !

I have a PCI Mezzanine Card (PMC) with a Virtex 400 and a front panel
connector. The Virtex is connected to the SCSI-2 style front panel
connector with 68 pins.These pins are interleaved signal and ground
pairs.So, I have 34 free I/O at the front panel connector.
  
I would like to connect a little add-on board to this front panel
connector. This board will be populated with a Gigabit Ethernet
Controller (PMC-Sierra PM3387). Besides data and control signals I
have to provide power to the add-on board.

I am planning to connect the add-on board VCC plane with the I/O pins
at the front panel connector. Then the Virtex will drive '1' at the
front panel connector I/O. The add-on board ground plane will be
connected with the ground pins at the front panel connector.

Can this provide sufficient power to the add-on board ?
Is there a better way to provide power ?

Thanks in advance.

Mark Lenz

Article: 59180
Subject: Re: Q: async flip-flop reset by a signal from a different clock domain
From: John Eaton <johne@hpvcljte.vcd.hp.com>
Date: 11 Aug 2003 18:21:07 GMT
Links: << >>  << T >>  << A >>
Mikhail Matusov <mbmsv@yahoo.com> wrote:
: Hi all,

: Is there a danger in doing async reset of a flip-flop by a signal
: generated by a state machine running in a different clock domain (than
: flip-flop clock)?
: I have a bunch of flip-flops that get synchronously written in one
: clock domain and they need to be reset from another clock domain. So,
: I used async reset... Is this a potential problem? I am having some
: misterious random failures and this is one of the suspicious places in
: my design...

: Thanks,
: /Mikhail


You can always async reset any flop BUT you must ensure that you remove
the reset signal with a known relationship to the flops clk. If you 
remove reset near the time that those flops are being written then
all bets are off.


John Eaton

Article: 59181
Subject: Re: async flip-flop reset by a signal from a different clock domain
From: "Avrum" <avrum@REMOVEsympatico.ca>
Date: Mon, 11 Aug 2003 14:37:11 -0400
Links: << >>  << T >>  << A >>
There certainly is a potential for failure here.

The ASYNC reset of a flip-flop is edge sensitive - as long as the signal is
asserted, the flop ignores the D and CLK input, and holds the Q at the reset
value. Conversely, when the reset is not asserted, flop reverts to its
normal behaviour of sampling the D at every rising edge of CLK and placing
the value on the Q. In other words, the assertion of the async RST changes
the behaviour of the flop.

On de de-asserting edge of RST, the flop is changing from one behaviour to
another. As a result, there is a window where the behaviour of the flop is
unpredictable; if the deasserting edge of RST occurs very close to the
rising edge of the clock, which behaviour is the flop going to exhibit - is
it going to maintain the RST value, or is it going to sample the D and place
it on the Q? Within a certain window (called the reset recovery time) after
the deasserting edge of reset, the behaviour is undetermined - it may do
either or maybe even neither - the flip flop may go metastable if the reset
recovery time is violated.

Furthermore, if you have a state machine with multiple state bits, all of
which are connected to this same asynchronous reset, you have compounded the
issue. Since the async reset is routed (separately) to each of the flops,
the propagation path to each flop may be different. So, when the RST is
deasserted, the deassertion may reach the different flops at different times
(by definition, this path is unconstrained since is crosses asyncronous
clock boundaries, unless you constrain it by hand). So, if the clock arrives
near the deassertion of RST - the flops with short routing delays may
acknowledge the deassertion of reset (and hence clock D->Q), the flops with
long routing will sill remain in reset, and the ones in the middle will do
either or go metastable. This can be a problem if, say, the reset state is
0000, and the next state (assuming reset is deasserted) is 1111. When the
CLK and RST are close together, you can end up in pretty much any state,
even states that are normally illegal to the state machine.

In general, this is quite a dangerous practice. Even when you are only using
the RST for resetting the initial state of the state machine, you should
always connect the RST (be it a synchronous RST or async RST) to an input
that is already syncronized to the same clock domain (to ensure that you
don't violate the recovery time on RST deassertion). This may have changed
recently, but in the past, the tools would NOT check for violations of the
reset recovery time when using asynchronous resets - you had to force it to
do so by placing

ENABLE="Trck";

in your .ucf file.

Avrum

"Mikhail Matusov" <mbmsv@yahoo.com> wrote in message
news:21803aae.0308110938.1c152f6d@posting.google.com...
> Hi all,
>
> Is there a danger in doing async reset of a flip-flop by a signal
> generated by a state machine running in a different clock domain (than
> flip-flop clock)?
> I have a bunch of flip-flops that get synchronously written in one
> clock domain and they need to be reset from another clock domain. So,
> I used async reset... Is this a potential problem? I am having some
> misterious random failures and this is one of the suspicious places in
> my design...
>
> Thanks,
> /Mikhail



Article: 59182
Subject: Re: Virtex "Virtual VCC"
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 11 Aug 2003 11:39:21 -0700
Links: << >>  << T >>  << A >>
Mark, your question cannot be answered without knowing the Icc
consumption of that extra board.
If it is <10 mA and not too picky about low Vcc, this might work if you
select the strongest Output drive for the pin ( or do you intend to use
multiple pins?)

Once you know the current, you can experiment with a simple resistive
load. :-)

Peter Alfke, Xilinx
==========================
lenz wrote:
> 
> Hi !
> 
> I have a PCI Mezzanine Card (PMC) with a Virtex 400 and a front panel
> connector. The Virtex is connected to the SCSI-2 style front panel
> connector with 68 pins.These pins are interleaved signal and ground
> pairs.So, I have 34 free I/O at the front panel connector.
> 
> I would like to connect a little add-on board to this front panel
> connector. This board will be populated with a Gigabit Ethernet
> Controller (PMC-Sierra PM3387). Besides data and control signals I
> have to provide power to the add-on board.
> 
> I am planning to connect the add-on board VCC plane with the I/O pins
> at the front panel connector. Then the Virtex will drive '1' at the
> front panel connector I/O. The add-on board ground plane will be
> connected with the ground pins at the front panel connector.
> 
> Can this provide sufficient power to the add-on board ?
> Is there a better way to provide power ?
> 
> Thanks in advance.
> 
> Mark Lenz

Article: 59183
Subject: Re: Q: async flip-flop reset by a signal from a different clock domain
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 11 Aug 2003 14:39:28 -0400
Links: << >>  << T >>  << A >>
Mikhail Matusov wrote:
> 
> Hi all,
> 
> Is there a danger in doing async reset of a flip-flop by a signal
> generated by a state machine running in a different clock domain (than
> flip-flop clock)?
> I have a bunch of flip-flops that get synchronously written in one
> clock domain and they need to be reset from another clock domain. So,
> I used async reset... Is this a potential problem? I am having some
> misterious random failures and this is one of the suspicious places in
> my design...
> 
> Thanks,
> /Mikhail

Yes, there is very much danger in the way you are resetting the FF
across clock domains.  The reset input has setup and hold time
requirements in relation to the clock edge just as the data input does. 
Violate the setup or hold time on the reset and the FF can go
metastable.  This will give very erratic results.  

It would be best to resync the reset signal to the other clock domain. 
If this makes too much delay, then you need to consider a different way
of accomplishing your goal for what the FF is doing.  In other words, go
back and rethink your need for the FF being reset.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59184
Subject: Re: async flip-flop reset by a signal from a different clock domain
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 11 Aug 2003 12:19:29 -0700
Links: << >>  << T >>  << A >>
Avrum, I agree 99%, but please do not call the asynchr. reset edge
sensitive. It is really the level that resets (and holds reset) the
flip-flop. I suppose it was a typo of yours...

Peter Alfke, Xilinx
===========
Avrum wrote:
> 
> There certainly is a potential for failure here.
> 
> The ASYNC reset of a flip-flop is edge sensitive - as long as the signal is
> asserted, the flop ignores the D and CLK input.......,:

Article: 59185
Subject: Re: async flip-flop reset by a signal from a different clock domain
From: "Avrum" <avrum@REMOVEsympatico.ca>
Date: Mon, 11 Aug 2003 15:53:39 -0400
Links: << >>  << T >>  << A >>
Have you ever said something when you mean the exact opposite? That's what I
did here...

Please change the sentence to read "The ASYNC reset of a flip-flop is LEVEL
sensitive" (the rest of the description makes more sense when this error is
corrected).

Sorry, all.

Avrum


"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F37EC42.BF4752C1@xilinx.com...
> Avrum, I agree 99%, but please do not call the asynchr. reset edge
> sensitive. It is really the level that resets (and holds reset) the
> flip-flop. I suppose it was a typo of yours...
>
> Peter Alfke, Xilinx
> ===========
> Avrum wrote:
> >
> > There certainly is a potential for failure here.
> >
> > The ASYNC reset of a flip-flop is edge sensitive - as long as the signal
is
> > asserted, the flop ignores the D and CLK input.......,:



Article: 59186
Subject: Re: Clocking in a virtex 2 without using the clock trees : questions
From: "jean-francois hasson" <jfhasson@club-internet.fr>
Date: Mon, 11 Aug 2003 22:14:21 +0200
Links: << >>  << T >>  << A >>
Hi,

Unfortunatly, I can not drive a global buffer with this clock because the
maximum delay I get when I go by the global buffer is 8 ns which is
incompatible with the fact that data is synchronous to the falling edge of
the 80 MHz clock. I believe I will try something else with a much faster
clock but just if this information is available what is the maximum skew
provided by the clock tree in a Virtex II ? The reason for my question is
that I read in a previous post that is was below 100 ps but when I run the
timing analyzer it seems it is more like 300 ps. Did I miss something ? If
not is my 450 ps skew small enough to consider no extra effort necessary ?

Thanks,

J.F. Hasson

"Peter Alfke" <peter@xilinx.com> a écrit dans le message de news:
3F33D7C6.4086EA39@xilinx.com...
> A clock that drives 40 flip-flops should be distributed on a global
> clock. Then you do not have to worry about the myriad aspects of clock
> skew. Instead you have a delay, but that is a single parameter, and is
> much easier to deal with.
>
> Peter Alfke, Xilinx
> =========
> jean-francois hasson wrote:
> >
> > Hi,
> >
> > I have a serial bus coming in a Virtex II -5 in LVDS format at 80 MHZ
> > with 3 data in parallel. The data change on the falling edge of the
> > clock. The problem is that the clock is present only when data is
> > transmitted (no DCM possible) and the pads used for the clock does not
> > allow the use of a bufgp without an important routing delay. I am
> > using the MAXSKEW constraint on the received clock and the best I can
> > get is 450 ps (I can not use the local clock resources described in
> > xapp609). This clock goes to approximately 40 FFs. I have, on this
> > clock domain, among other things, a shift register so I have a FF to
> > FF path. When having the min skew of 450 ps parts of the shift
> > register are implemented in the same CLB so the output of a FF goes
> > through the local routing matrix of the CLB and back to the input of a
> > FF in the same CLB : I believe it must be the shortest and quickest
> > path to go from one FF to another. My problem is that I wonder if the
> > skew I have will always be smaller than the clock_to_out + prop_delay
> > : I believe the max values are ok but what about typical ?
> >
> > Thank you.
> >
> > J.F. Hasson



Article: 59187
Subject: Re: a quick searching problem
From: John Handwork <johnhandwork@mail.com>
Date: Mon, 11 Aug 2003 20:42:51 GMT
Links: << >>  << T >>  << A >>
Didn't you ask this same question 3 days ago?

Zhen wrote:

>There are two vectors, named V1 and V2, the sizes of which are 1*M and
>1*N, respectively. We have known that there is at most one common
>element in both vectors. I am looking for the quick algorithm to
>search this common element.
>
>The general algorithm is to compare every element in V1 with each
>element in V2. the comparison complexity will be O(M*N). Is there any
>efficient method to complete it?
>I hope it can be done in FPGA. If M=N=60, and each element is 20 bit
>long,there isn't enough pins for the general search algorithms at one
>time. It need some loops to do it. So I am looking for an efficient
>algorithm and expect that the common element can be found in around
>10ns~50ns. Is it possible?
>Thanks,
>  
>


Article: 59188
Subject: Win2k service packs for running Xilinx tools
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 11 Aug 2003 17:04:00 -0400
Links: << >>  << T >>  << A >>
I seem to recall that at one time the Xilinx tools were not compatible
with Win2k SP3.  Anyone know if that is still an issue?  I assume it is
since I still see SP2 listed under the System Requirements. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59189
Subject: Re: Win2k service packs for running Xilinx tools
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 11 Aug 2003 17:20:43 -0400
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> I seem to recall that at one time the Xilinx tools were not compatible
> with Win2k SP3.  Anyone know if that is still an issue?  I assume it is
> since I still see SP2 listed under the System Requirements.

Oh, and I noticed on the MicroSoft website that Windows 2000 is up to
SP4.  It seems like an update to the Xilinx support of W2k is needed.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59190
Subject: questions about PCI implemented in Actel APA300
From: "sarah shen" <sarahshenca@yahoo.ca>
Date: Mon, 11 Aug 2003 17:40:03 -0400
Links: << >>  << T >>  << A >>
Hi,

I have a big problem with PCI implemented in Actel APA300. Does anybody know
the very detailed information about Actel CorePCI except the datasheet?

Thanks in Advance!

Best Regards!

Sarah   ( sarahshen2003@yahoo.ca)



Article: 59191
Subject: Re: a quick searching problem
From: jimwu88NOOOSPAM@yahoo.com (Jim Wu)
Date: 11 Aug 2003 14:47:58 -0700
Links: << >>  << T >>  << A >>
Suppose every element in V1 is in a memory and V2 has only one element
called E2_0. Now the problem becomes to find out if E2_0 exists in the
V1
memory. Sounds a lot like IP address lookup, doesn't it? A CAM would
be a good choice for this type of problem. The search time would be in
the order of N not M*N.

Jim Wu
jimwu88NOOOSPAM@yahoo.com

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<cUPZa.10$Vd.1194175@newssvr14.news.prodigy.com>...
> You are thinking in terms of feeding the vectors into an FPGA in parallel.
> That is hardly necessary (unless you generate entire new vectors every
> 10ns).
> 
> Questions you need to answer:
> 
> -How quickly are new vectors generated?
> -Where will the vectors come from (or be stored)?
> -How quickly do you need an answer?
> -What is the maximum value of M and N?
> -Is it guaranteed that there will be only one matching value for all
> possible vector combinations?
> -How many different 20 bit values can a vector element have?  Is it a
> straight unsigned binary value or some sort of a code that would limit the
> number of distinct values to less than 2**20?
> 
> Just as an example, if M = N = 512, with the FPGA running at 100MHz, you
> could do a brute force comparison of two vectors in 2.6 ms.  Your M = N = 60
> example would take 36 microseconds.  Keep in mind, these are worst-case
> figures.
> 
> For the above use two SelectRAM memories preloaded with your vectors.  You
> could load your vectors one word at a time at whatever rate your source
> could handle.  If, say, your source happens to be SDRAM connected to the
> FPGA you could load the vectors at 133MHz (or 2x with DDR).  Depending on
> the width of the data path that would mean one or more 20 bit word per
> clock.  No need to consume I/O to pass the vectors in parallel.
> 
> So, a rough estimate of a complete load->compare->result cycle would be:
>   M = N = 512 ... load = 7.7us; compare = 2.6ms
>   M = N = 60  ... load = 0.9us; compare = 36us
> 
> Is that fast enough?  You could always run the FPGA faster.
> 
> If SDRAM was involved I would probably run the logic at the SDRAM clock (or
> 2x) rather than an unrelated frequency (like 100MHz).
> 
> There are a million possible variations of this concept.  It all depends on
> the constraints you have to work within.  A binary search, for example,
> would provide a very significant improvement in performance.  You could
> replicate the circuit X times in order to obtain a further X-time
> improvement in reaching a match.
> 
> 
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
> 
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"

Article: 59192
Subject: Cyclone's LVDS and Quartus II
From: jonesky1@hotmail.com (Joona R)
Date: 11 Aug 2003 14:53:33 -0700
Links: << >>  << T >>  << A >>
Hi!

I have wrote some VHDL and now I have tried to get some signals from
Cyclone FPGA chip.
But how to implement LVDS output or input for a signal with Quartus II?

I have tried these methods:

1. Adding signal with Assign Pins-editor. I/O Standard set to lvds.
Result:with Floorplan viewer I can see signal implemented, but it is not
a LVDS, other side is missing (p vs n).

2. I have produced megafunction altddio_in/out and its low and high signals
connected to signals or pins (vectors for low's and another for high's).
I/O Standard is set to lvds.
Result: Quartus will give this error message:
"Can't place pins assigned to pin location Pin_160 (IOC_X53_Y20_N1)
 Pin test_lo[3] is assigned to pin location Pin_160 (IOC_X53_Y20_N1)
 Pin test_hi[3](n) is assigned to pin location Pin_160 (IOC_X53_Y20_N1)"

3. Same as in two, but I/O standard is set to 2.5V, then no error
messages and viewing floorplan I can see signals correctly, but this
is no lvds anymore?

4. There is megafunction altlvds, but it is not supported by Cyclone.


If someone knows how to do this correctly, I would appreciate a little help! =)

- Joona

Article: 59193
Subject: Xilinx ISE error
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Mon, 11 Aug 2003 18:16:30 -0500
Links: << >>  << T >>  << A >>

Hello,

I have Xilinx ise 4.1.03i, and ran into a wierd problem I haven't seen 
before.

I have a multi-page schematic that I'm trying to compile to an XC95xx 
CPLD.  It has
2 8-input or gates on one sheet, and another one on a different sheet. 
 I get the following
message when doing the synthesize process :

ERROR:HDLParsers:3340 - Project file master.prj names two source files, 
D:/nchem/mothbrd/Motherboard/mb2.vhf and D:/nchem/mo
thbrd/Motherboard/mb1.vhf, that both define the same primary unit, 
work/OR8_MXILINX
ERROR:HDLParsers:3340 - Project file master.prj names two source files, 
D:/nchem/mothbrd/Motherboard/mb2.vhf and D:/nchem/mo
thbrd/Motherboard/mb1.vhf, that both define the same primary unit, 
work/OR8_MXILINX/SCHEMATIC

Looking into the .vhf files, I see the OR8_MXILINX is defined as an 
entity, and later as a component, in
both of these files.  This doesn't seem to be out of the ordinary, it 
looks just like the other standard library
definitions.

Does anyone have any suggestions?

Thanks,

Jon


Article: 59194
Subject: Re: Upgrading OS or WebPack
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 12 Aug 2003 12:16:57 +1200
Links: << >>  << T >>  << A >>
Stephen Williams wrote:
> 
> I am not generally a Windows user, but when forced by circumstances,
> I find that NT is a bit moldy, Windows 2000 is OK, and XP is spooky.
> I would suggest upgrading to Windows 2000 while (if!) you can still
> get it, then stay away from XP in perpetuity.

 I would concurr.
Generally Win2000 has good dos/batch support, which you tend to need
on engineering PCs. 
 Wrinkles I've seen so far in Win2000 in eng. development: 

 Within batch files, >file.log fails, but >>file.log works - go
figure....
( first should redirect to file, 2nd is same, but appends the file )

 Some Programmers editors launch DOS apps better than others in Win2000.
Still characterising that one....

-jg

Article: 59195
Subject: Webpack sees 2 clocks when there is only one
From: "Jason Berringer" <look_at_bottom_of@email.com>
Date: Mon, 11 Aug 2003 20:23:20 -0400
Links: << >>  << T >>  << A >>
Hello,

I'm implementing a data bus between a FPGA (XC2S100) and an 8051. Due to the
multiplexed data/address bus I have to latch the 16 bit address on the
falling edge of ALE (before the lower address byte is changed to the data
byte) so I implement the latch easy enough, however when I sythesize it
through the webpack it interprets this as a clock signal and gives me an
error that it is connected to the wrong pin, it states that I should have it
connected to a clock input. My question is how do I get the sythesizer to
overlook this signal as a clock and treat it as a simple input.

Your help would be greatly appreciated.

In case you needed to see the snipit of code that I'm using to latch the
data here it is (note I've also tried using ale_n'event and ale_n = '0'
instead of faling_edge just in case the translation was somewhat messed up).
This process latches the lower address byte into the signal address_low from
the address_data bidirectional port on my entity.

...
process(reset, ale_n) begin
    if reset = '1' then
        address_low    <= (others => '0');
    elsif falling_edge(clk) then
        address_low <= address_data;
    end if;
end process;
...

Thanks

Jason



Article: 59196
Subject: Re: FPGA for a Newcomer
From: "John Bowen" <johnboy@cafes.net>
Date: Mon, 11 Aug 2003 22:00:29 -0500
Links: << >>  << T >>  << A >>
Thanks, guys. I've gained a lot of valuable knowledge due to your responses,
and I feel like I'm now headed in the right direction.
John
"John Bowen" <johnboy@cafes.net> wrote in message
news:3f36447d@news.isdn.net...
> I've had several courses on Digital Logic, ......but that was in the early
> 1980s !!  I was very familiar with the 7400 series of integrated circuits,
> and could name the gates and truth tables off the top of my head. A lot of
> years have passed since I worked with these chips, and I've fallen way
> behind in technology. But now I'd like to do some experimenting on my own.
>   I wanted to build something like a simple Annunciator Panel type
project,
> so I dug out my old logic books to brush up. What I found out was that I
> needed about 50-75 Logic Gates for my particular design, though I'm sure I
> could pare that down some, but  the thought of mounting and wiring (I used
> to wire-wrap a lot) about 25 or more Integrated Circuits just kind of
> discouraged me. I was asking a fellow Technician about maybe using some
sort
> of EEProm, and he told me about Field Programmable Gate Arrays...according
> to what I've since learned, it looks like I should be able to program a
FPGA
> with my logic design(or reprogram it if I make a mistake)....my logic
would
> be a series of And, Nor, etc. gates, Flip Flops, etc, and use contact
> closures for inputs and LEDs for outputs. Am I correct in my
interpretation
> of what a FPGA is, and how it operates?
>    I was looking at 10 inputs (contact closures) and 10 simple LEDs for
the
> outputs on this first project. Since I'm not familiar with the pin
> assignments for the I/Os, and what's needed to program these FPGAs, would
> any of you have a recommendation on what family and size of FPGA I should
> start with? Or is an FPGA really what I need? What about a programmer (or
> programming method) and software? I'd be most comfortable using a software
> that graphically displays my gates and their connections if there is such
a
> thing, but since this is just going to be a playtoy for now, I guess cost
> needs to be a consideration, so inexpensive developmental would be best.
Is
> there a Complete Experimenter's Kit available for someone with my
interests?
> Or would I be better off buying individual components to suit my needs?
>   I've read some of the posts, and it sounds like you guys are WAAAY up on
> the curve....can you help me get started?
> Thanks, John.
>
>



Article: 59197
Subject: Data Structure Viewer
From: "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com>
Date: Tue, 12 Aug 2003 03:43:29 GMT
Links: << >>  << T >>  << A >>
Data Structure Viewer is a GUI based tool written in Perl and Perl-Tk. It
allows you to convert between a data structure (e.g. IPv4 header) and
individual fields in the data structure by simple mouse clicks. It can be
configured to support almost any data structure definition. Please check it
out at http://www.geocities.com/jimwu88/chips/

Please let me know about any questions or suggestions.
Thanks,

Jim Wu
jimwu88NOOOSPAM@yahoo.com  (remove NOOOSPAM)



Article: 59198
Subject: Re: Upgrading OS or WebPack
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 12 Aug 2003 00:54:13 -0400
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> Stephen Williams wrote:
> >
> > I am not generally a Windows user, but when forced by circumstances,
> > I find that NT is a bit moldy, Windows 2000 is OK, and XP is spooky.
> > I would suggest upgrading to Windows 2000 while (if!) you can still
> > get it, then stay away from XP in perpetuity.
> 
>  I would concurr.
> Generally Win2000 has good dos/batch support, which you tend to need
> on engineering PCs.
>  Wrinkles I've seen so far in Win2000 in eng. development:
> 
>  Within batch files, >file.log fails, but >>file.log works - go
> figure....
> ( first should redirect to file, 2nd is same, but appends the file )
> 
>  Some Programmers editors launch DOS apps better than others in Win2000.
> Still characterising that one....

As long as we are mentioning Win2k for running FPGA tools, I thought I
would mention that Xilinx does not support the W2k service packs beyond
2.  Also, there is a nasty bug running around at the moment that
requires a patch from MicroSoft.  If you use Win2k, you can get the
patch here...

http://www.microsoft.com/technet/treeview/default.asp?url=/technet/security/bulletin/MS03-026.asp

I just got this bug.  Turns out the virus detection files were just made
available today for my AV software.  Even so, I have no idea how I got
it.  I never run strange exe's or other potentially executable files. 
Heck, I don't even open email from a lot of sources.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59199
Subject: Re: Offshore engineering
From: "xno" <xno@xno.com>
Date: Tue, 12 Aug 2003 05:24:26 GMT
Links: << >>  << T >>  << A >>
> I was deadly serious, and the concept, though very simple, is also very
> hard to confute. When you have a working force ten times bigger, that
> works more hours a day for (a lot) less money, how can you think to
> compete? In my opinion, the real childish attitude is to blame the
> piracy rate.

> Some big countries are growing (at least) ten times faster than the
> "rich" ones. While in the beginning it was simple for the multinationals
> to slave entire villages of mid-east asians for making shoes at 30
> cents/hour, now (luckily, I might add) their demands are growing. It is
> still a great deal for multinationals, but the margin is smaller, and
> someone has to pay.
>
> In a smaller scale, there is the same "problem" here in Europe:
> countries like Germany, France or Italy move more and more frequently
> the production to east-european countries (Poland, Bulgary and so on),
> because it costs a lot less. We are just at the point the USA were in
> the mid-eighties: only the "easy" production (not engineering or other
> "creative" activities) is moved offshore. But engineering is just the
> next step. All men are equally smart, if they get an appropriate
> instruction.

The major high-tech companies in Europe (Siemens, Philips, etc.)
already have production facilities in Asian countries.  Infineon (formerly
part of Siemens) already splits DRAM IC production between its
primary owned facilities (fabs) and *contracted* fabs.  At least,
that's what i understand.  Siemens has a licensing agreement with UMC,
which amounts to a capacity agreement for Siemens to manufacture
RAM on UMC's foundry.

Infineon's goal is to lower the cost of DRAM production.  The reality
is that splitting production over more than one fab, even when the 2nd
fab (UMC) uses a familiar process-flow, is a complicated task.  Not
that Infineon isn't up to the challenge...it's just not something the
average
EE-company can get up and do.

No doubt, the European high-tech industry (as a whole) is in
the same situation as US companies when it comes to design-outsourcing...
just starting up!

> By the way: I'm not a supporter of globalization, at least of the kind
> of globalization we have seen in the last 20 years. This
> "conquistadores" way of globalizing will become a boomerang for the big
> corporations. And for us, of course.
>
> > If someone has the genuine ability to engage in a
> > discussion (on adult
> > terms) as to the effect that the "offshore revolution"
> > will have on
> > technology, markets, product development, IP,
> > manufacturing, the FPGA world,
>
> I think there won't be any technical change, the only effect will be the
> change of economic barycentre.

In the olden days, chip-design was an esoteric art that only the
richest could dream of doing.  The computers (mainframes or high-end
workstations) cost a lot of money, the design software cost a lot of
money, and the engineers (with the right educational background)
cost a lot of money.

Today?  'High-capacity' FPGAs (100k ASIC gates) are sub-$100 (USD),
and the development-software is *FREE*.  The only factor remaining
is the labor ... Verilog/VHDL is already a commodity skill, much like
C-programming became a decade ago.  A computer hobbyist can go to
the store, buy a $50 Verilog/VHDL book and a digital-logic design book,
and he's about $200 away from tackling CPU-design!

In other words, the hardware field (particuarly FPGAs) is accessible to
many more people than it used to be.





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search