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John wrote: > > Hi all: > I have the following verilog codes which shift the serial data to parallel > data.But it cost > too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not > what to do.Anybody would help me? > > reg[31:0] reg_in[7:0],reg_out[7:0]; > > always @(posedge clk) > begin > if(reset) > cnt8<=0; > else > if(cnt8==7) > begin > cnt8<=0; > reg_out[0]<=reg_in[0]; > reg_out[1]<=reg_in[1]; > reg_out[2]<=reg_in[2]; > reg_out[3]<=reg_in[3]; > reg_out[4]<=reg_in[4]; > reg_out[5]<=reg_in[5]; > reg_out[6]<=reg_in[6]; > reg_out[7]<=reg_in[7]; > end > else > begin > cnt8<=cnt8+1; > reg_in[0]<=reg_in[1]; > reg_in[1]<=reg_in[2]; > reg_in[2]<=reg_in[3]; > reg_in[3]<=reg_in[4]; > reg_in[4]<=reg_in[5]; > reg_in[5]<=reg_in[6]; > reg_in[6]<=reg_in[7]; > reg_in[7]<=data_receive; > > end > end I don't think an EAB will help you much. This code will use one LAB (8 LEs) for the shift register and 3 or 4 more LEs for the counter. The shift register can fit in an EAB (but not with the counter), so you will save only one LAB for using an EAB. Why do you think this uses too many LEs? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59001
>Vcc bounce is hardly an issue with most designs. That is why it is not often >considered. >Ground bounce affects everything: slicing level, jitter, timing, function of the >device (etc). >Vcc bounce my affect IO output timing, jitter, but is generally a second order >effect. Thanks. Why the asymmetry? I'd expect TTL type inputs (referenced to 2 diodes above ground) to be sensitive to ground bounce only, but what about others? I thought the reference for CMOS was roughly 1/2 way between Vcc and Ground. Wouldn't that wiggle if Vcc wiggled? Is PECL referenced to Vcc? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 59002
Hal Murray wrote: > > >Vcc bounce is hardly an issue with most designs. That is why it is not often > >considered. > > >Ground bounce affects everything: slicing level, jitter, timing, function of the > >device (etc). > > >Vcc bounce my affect IO output timing, jitter, but is generally a second order > >effect. > > Thanks. > > Why the asymmetry? > > I'd expect TTL type inputs (referenced to 2 diodes above ground) to be > sensitive to ground bounce only, but what about others? > > I thought the reference for CMOS was roughly 1/2 way between Vcc and > Ground. Wouldn't that wiggle if Vcc wiggled? Yes. What separates the issue on FPGA and bigger CPLD, is the core Vcc is not the same pins as Vcc[io] - whilst bounce on the common GND can disturb the core (where it is certainly noticed :) Vcc[io] bounce WILL disturb the IO threshold, but most digital signals pass thru the threshold very quickly. In a jitter paranoid application, you could expect to notice Vcc related crosstalk. > Is PECL referenced to Vcc? Outputs are emitter followers on open collectors, so yes. PECL is normally differential, so you get PSR that way, plus you also reduce any spikes, due to the balance drive. - jgArticle: 59003
<snip> > > > > p.p.s. > > Reading the LRM shows I really am being paranoid, as type TIME is > > guaranteed to include the range -2**9+1 to 2^9-1, so negative > > time values in variables of type TIME are ok. > That should have been -2**31+1 to 2**31-1, sorry. > The possibility of being negative was why I was using a variable instead > of just sticking it in the wait statement. I thought it would be better > to calculate it once and then test it and set to zero if negative. So > now I have to do the calculation twice. > OK, sounds sensible. > I am getting the same error from a different assignment now. The common > point is that a signal is on the right hand side of the assignment and a > variable is on the left. I am using the variable assignment operator, > ":=". This is reported as an error, not a warning. > > Last_Bus_Action := Bus_Command.Bus_Action; > > In both cases, part of the right hand expression is an element in a > record. The error reports the record "Bus_Command" as missing from the > sensitivity list, not the element! Could the VITAL process have a bug > in regards to dealing with record elements? This doesn't sound likely > to me. But then I don't even know what the VITAL process is. > That is weird. I thought that VITAL was a label you'd used in your code, e.g. vital: process... But if it's not? If it's vital as in "VITAL - VHDL Initiative Toward Asic Libraries" then I'd only expect to see it referred to if you were doing back-annotated gate level simulation? > Maybe I need to contact Mentor about ModelSim. > Sounds like a good idea. regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 59004
Hi,
I have a rack/shelf which has 3 cards:
the host, a PLX9030 card and a card with
Altera/FPGA MegaCore - all these cards are
connected via a Compact-PCI bus.
I tried to test the cards by simply
dumping out the PCI configuration spaces
of the PLX9030 and Altera cards.
When the host is a 'MEN F0001 Power-PC'
card, I used the provided MENMOM on-board
utility ('PCID') to dump out the PCI
configuration spaces of both cards (PLX9030
and Altera MegaCore). Both gave me expected
results.
When the host is a 'PEP CP302 Intel'. I
used two publicly available utilities: WinDriver
under Windows NT and PLXMon under DOS. Both
utilities did not dump out the expected
configuration space values for Altera/MegaCore
card (e.g. the Vendor ID and Device ID were
OK, but all the BARs were zeros). However, the
configuration space for PLX9030 was OK.
It seems the operating systems (Windows NT
and/or DOS) on the host did not allocate resources
for the Altera/FPGA card.
Any ideas, speculation.... why the results differ ?
Could it be Windows and/or DOS? Could it be
the 'PEP CP302 Intel' card itself ? or
any other reasons ?
Thanks in advance!
Regards
Beeson
Article: 59005John Williams wrote: > (example from drivers/char/xilinx_gpio): My project is not using xilinx_gpio at the moment, as when I looked at it this did not seem to be available - I use my own driver for leds. Jon.Article: 59006
"Yash Bansal" <yash@viper.ece.ucdavis.edu> schrieb im Newsbeitrag news:Pine.HPX.4.21.0307301129160.4735-100000@viper.ece.ucdavis.edu... > > On Wed, 30 Jul 2003, Andras Tantos wrote: > > > > I am currently trying to perform a readout from FPGA to a LINUX PC using > > > parallel port. I have implemented the state-machine for EPP communication > > > in the FPGA and it works well however the system is slow. > > > > > > I think this is because EPP devices are supposed to negotiate the best > > > available transfer mode during initialization but the FPGA is not > > > currently setup to do that. As a result, I had to fall back on software > > > emulation of the data transfer handshaking. > > > > > > I was wondering if anyone has experience performing readout from FPGA > > > using EPP. My aim is to get 1MByte/sec communication. Any help would be > > > appreciated. > > > > > > > I had the same experience: the PC parallel port HW wouldn't switch into EPP > > mode without the proper negotiation. You will stay in SPP mode on the SW > > side, though you can emulate the EPP protocoll from SW. And yes, it's slow. > > > > Andras Tantos > > Were you able to implement the proper negotiation and avoid staying in > SPP? If so what do you recommend? > > -Yash > Hello Yash, we reached about 500 Kbytes transfer rate using EPP mode for read or write. Half rate using PS2 (8-bit bi-dirctional mode) read or write mode and SPP(standard parallel port, byte out/nibble in) write mode. Quarter rate at SPP read mode. We used Win2000 and a none PCI based parallel port chip at the PC side (standard at PC mainboards). Using a parallel port based on a PCI card, transfer rate could be up to 450 Kbytes using PS2 mode, but implementing EPP mode can be hard (if it ever works). Seems to be chip dependent, and we didn´t get good support from PCI chip manufacturer. Hint: do not set port to ECP or ECP/EPP mode, better set it to EPP mode (via PC BIOS). good luck, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 59007
The only difference between "your" code and the one posted is the read scheme. Yours is "write firste" where as the posted is "read firste". The testbench never writes to and reads from the same address in the same clock cycle, so the read scheme can't explain why the last read value is incorrect. I have tried using your code and it has exactly the same problem. A screenshot of the wave forms for behavioural and post-translate simulation can be found at. http://www.student.dtu.dk/~s001467/simulation.jpg Bo Esbech "Mike Treseler" <mike.treseler@flukenetworks.com> skrev i en meddelelse news:3F3007B1.6060002@flukenetworks.com... > Christian Obel wrote: > > I am doing a project for a Virtex2 fpga with the Free ISE WebPACK 5.2i with > > all the latest patches. I am writing a piece of behavioral VHDL that will > > synthesize as dual ported block ram and a testbench to verify its behavior > > by writing three values to it and then read them back. This works all fine > > in a behavioral simulation, but when I advance to a post-translate or > > post-place & route simulation the last of the three values read ( the first > > written) is wrong. Can someone tell me what is wrong? Maybe it is never > > written? > > Maybe you need to register the address. > http://groups.google.com/groups?q=sync_ram+entity+lpm_ram_dq > > -- Mike Treseler >Article: 59008
I have the same problem as Rgr and I already did what you said. I imported the updated files back to XPS and used "update bitstream". I tried downloading the program onto the board and it doesn't work. By the way I'm using EDK 5.1i and the ML300 evaluation board. Michelle >>Looks like your trying to download a bit-file to a PROM (xc18v04). >>What I know from the toolchain using a PowerPC is that you generate the >>bit-file with project navigator, then import that in Platform Studio >>again to include the embedded software (assuming you store the software >>in BRAM-blocks) using 'update bitstream'. The resulting bitstream can be >>converted with Impact to a mcs-file to be programmed in the PROM. >>Regards, >Rienk Rgr wrote: > Hi NG. I am using ISE5.2i and EDK 3.2 and tries to implement a > MicroBlaze-design. > > The funny thing is that my design synthesizes fine, and I can even download > it to my FPGA board (Virtex II) using the project navigator, the problem is > that my written C-code does not get implented as well, so I have to download > from the EDK software. > When I do I get the error bellow. Anyone have an idea on what is wrong? As > mentioned I can perfectly download a design to my board using the project > navigator, but not with the EDK software, so I do not think it's my cable > causing trouble :-( > > > Command bash -c "cd /xygdrive/c/EDKproj1/; make -f system.make download; > exit;" Started... > ********************************************* > Downloading Bitstream onto the target board > ********************************************* > impact -batch etc/download.cmd > // *** BATCH CMD : setMode -bs > // *** BATCH CMD : setCable -port lpt0 -baud 9600 > Connecting to cable (Parallel Port - lpt1). > Checking cable driver. > Driver windrvr.sys version = 5.0.5.1. LPT base address = 0378h. > Cable connection established. > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > INFO:iMPACT:1366 - > Reading etc\xc18v04_vq44.bsd... > INFO:iMPACT:1366 - > Reading C:/Xilinx/xc18v00/data\xc18v04_vq44.bsd... > INFO:iMPACT:501 - '1': Added Device XC18V04_VQ44 successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > INFO:iMPACT:1366 - > Reading etc\xc18v04_vq44.bsd... > ---------------------------------------------------------------------- > // *** BATCH CMD : addDevice -position 1 -part etc/xc18v04_vq44.bsd > // *** BATCH CMD : setAttribute -position 1 -attr configFileName -value > etc/xc18v04_vq44.bsd > INFO:iMPACT:1366 - > Reading etc\xc18v04_vq44.bsd... > INFO:iMPACT:1366 - > Reading C:/Xilinx/xc18v00/data\xc18v04_vq44.bsd... > INFO:iMPACT:501 - '1': Added Device XC18V04_VQ44 successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > INFO:iMPACT:1366 - > Reading etc\xc18v04_vq44.bsd... > '2': Loading file 'implementation/download.bit' ... > done. > INFO:iMPACT:1366 - > Reading C:/Xilinx/virtex2/data\xc2v1000.bsd... > INFO:iMPACT:501 - '2': Added Device xc2v1000 successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > // *** BATCH CMD : addDevice -position 2 -file implementation/download.bit > // *** BATCH CMD : program -p 2 > Validating chain... > INFO:iMPACT:1209 - Testing for '0' at position 6.The Instruction capture of > the > device 1 does not match expected capture. > INFO:iMPACT:1206 - Instruction Capture = '11111111110101' > INFO:iMPACT:1207 - Expected Capture = '000XXX01XXXX01' > ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'. > A problem may exist in the hardware configuration. > Check that the cable, scan chain, and power connections are intact, > that the specified scan chain configuration matches the actual hardware, and > that the power supply is adequate and delivering the correct voltage. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Done. > Command bash -c "cd /xygdrive/c/EDKproj1/; make -f system.make init_bram; > exit;" Started... > make: Nothing to be done for `init_bram'. > Done. > >Article: 59009
hmurray@suespammers.org (Hal Murray) wrote in message news:<viofmij2jhd50b@corp.supernews.com>... > >As a study for a project I need to investigate the possibility of > >implementing a tiny TCP/IP stack and tiny MAC controller on FPGA. This > >stack is capable to transfer some data packets directly into S(D)RAM > >without help of the microcontroller. Thus a simple communication via > >Ethernet from the desktop PC is required for download/upload to/from > >the memory. > > TCP gets pretty complicated. I expect the best way to do in in an > FPGA would be to build a CPU and treat it as a software problem. > > You might try UDP first. A server-only UDP implementation doesn't > need any timers or routing tables. (You can send the packet back > where it came from. Be sure to fixup the broadcast case.) What do you mean about "Be sure to fixup the broadcast case"? It is not the intention to implement all TCP/IP functions in the FPGA (target). As far I had read and understand some stuffs about Ethernet protocols. The minimum "processor-less" requirements is the UDP protocol for a simple data transfer without data loss checks. In the UDP frames a sequence number can be inserted to verify the data completeness. Checksum calculation and handlers can also be implemented in the FPGA. No stack is required when all valid UDP packets will be processed immediately and stored into the SRAM memory. In this case all TCP functions/stack can be removed. It will lead to reduce the amount FPGA logic elements substantiatelly. I am not sure about some things and have some questions: 1. Is only the UDP protocol sufficient to be implemented in FPGA for simple data transfers to the target (FPGA) from the PC? Do I need also the ARP or other protocols? 2. Which protocols can I miss when the PC knows the 32-bit IP number of the target? Is a 48-bit ethernet address required? 3. Suppose that all UDP packets will also be forwarded through the router(s) to the target. Does it needs a special attention when only the UDP is implemented? Will the routers change the IP header (and UDP header) of the UDP packets before they are arrived at target? 4. Is the connection negotiation required between the PC and the target? Do you think that the PC will always transfer some UDP packets without restrictions?Article: 59010
Beeson Wong wrote:
> Hi,
>
> When the host is a 'MEN F0001 Power-PC'
> card, I used the provided MENMOM on-board
> utility ('PCID') to dump out the PCI
> configuration spaces of both cards (PLX9030
> and Altera MegaCore). Both gave me expected
> results.
>
> When the host is a 'PEP CP302 Intel'. I
> used two publicly available utilities: WinDriver
> under Windows NT and PLXMon under DOS. Both
> utilities did not dump out the expected
> configuration space values for Altera/MegaCore
> card (e.g. the Vendor ID and Device ID were
> OK, but all the BARs were zeros). However, the
> configuration space for PLX9030 was OK.
>
> It seems the operating systems (Windows NT
> and/or DOS) on the host did not allocate resources
> for the Altera/FPGA card.
>
>
I have had problems with the PLX PCI9052 and certain versions of the
Compaq EVO series. It appears to be a BIOS problem, they aren't allowing
the PLX chip enough time to load from the EEPROM. At least, that was
PLX's view of the problem (of course, Compaq never replied so I don't
know what theirs is).
If your end system is DOS based, if you poke the correct values to the
registers, it works fine thereafter. I expect you can do it with some
Windows versions too, though not NT, MX etc. But plug and play might
mess things up if any hot plugging happens.
Paul Burke
Article: 59011
I have a design which needs an S-R flipflop with Reset having priority over
Set. This VHDL code
dir_srff: process (dirset, dirrst, reset_w)
begin
if dirrst='1' or reset_w='1' then
direction <= '0';
elsif dirset='1' then
direction <= '1';
end if;
end process;
synthesises into a Xilinx 'LDC' cell with the 'D' input tied to PWR.
According to the Xilinx docs here:
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0266_250.html#wp10
01293 this cell should ignore the gate enable (G) when the clear input (CLR)
is high. However, the generated simulation model doesn't appear to behave
like it should.
When the design is reset, the Reset input to the cell gets asserted, but a
combinatorial race also causes a glitch on the Set input. Instead of this
glitch being ignored, the cell output goes to 'X', even though the Reset
input is asserted through, and well after, the glitch on Set. This is
contrary to both the description of the LDC cell and the expressed intent of
the VHDL code.
The instantiation of the simulation element looks like this:
I0_notri_i_abridge_fifo_s2m_flag_gen_lat_direction : X_LATCHE
port map (
I => I0_notri_i_abridge_fifo_s2m_flag_gen_direction_LOGIC_ONE,
GE => VCC,
CLK => I0_notri_i_abridge_fifo_s2m_flag_gen_direction_FFY_CK_LATNOT,
SET => GND,
RST => I0_notri_i_abridge_fifo_s2m_flag_gen_direction_FFY_RST,
O => I0_notri_i_abridge_fifo_s2m_flag_gen_direction
);
Is the simulation model for LDC wrong, or does this indicate a real problem
with my design or the way it has been synthesised?
I could probably switch off 'X' generation from this cell, but then I
wouldn't see any 'real' timing violations.
I am using Xilinx ISE 5.1.03i for P+R and simulation model generation..
If you are interested, the SRFF in question is the 'direction' flag inside
an asynchronous FIFO in the style of Cummings and Alfke, SNUG 2002.
Article: 59012Jim Granville <jim.granville@designtools.co.nz> wrote: : If the fitter has not at this stage reported the Prod terms, you : could re-target a 9572XL,(just for the purposes of getting : a complete fitter report!), and then compare with the one below. Good idea. However what I tried instead was disabling my constraints file (which simply determines the pinout). It still fails to fit, but this time it does report the counts: Macrocells used: 36/36 (100%) Product terms used: 180/180 (100%) Registers used: 36/36 (100%) Pins used: 34/34 (100%) Function block inputs used: 73/108 (67%) It then reports "Cannot place signal P<4>". This compares with the successful XC9536 report: Macrocells used: 36/36 (100%) Product terms used: 146/180 (81%) Registers used: 36/36 (100%) Pins used: 34/34 (100%) Function block inputs used: 56/72 (77%) So the number of product terms has gone from 146 on the XC9536 to 180 on the XC9536XL and the number of function block inputs has gone from 56 to 73. Does this shed any light ? Is it likely it will ever fit in an XC9536XL ? Richard. http://www.rtrussell.co.uk/Article: 59013
Hi Jay: the big thing to get through here is an understanding of what a gate is - it can be a transistor in some ASIC vendors "speak" (like maxim SiGe), or a 2 input nands in others (IBM/LSI), or other. Let's say that this is a 2 input nand case - you need two of these for a simple flop, and can build logic accordingly - I would guess that you are not starting with the ASIC and trying to implement it in the CoolRunner, but I may be wrong, so, what you need to do is compile the thing and look at register usage and cell usage - I'm not familiar enough with the coolrunner parts to gauge this, but if you can fit say 8 logic "gates" in one CLB or two registers - you might come close if you look at the ASIC type. Routing is another variable - I would guess that you are not going to use more than 80% of your coolrunner part, and an ASIC will be close to 100% usable. You could try to judge accordingly, but the best way to do this is to contact your ASIC vendor (each process is different in terms of definitions and number of metal layers and "process (3 microns and down)" and number of transistors/resistors/layout). They will know better than anyone in a newsgroup. Here, we are shooting in the dark, and it willl not help you too much in reality. If you are trying to implpement an ASIC intop a coolrunner part, you will either need the HDL code or a schematic that was used to generate the ASIC for just logic considerations, and you should be able to crunch that through quick and get an idea of the number of cells you will use in the coolrunner. Andrew Jay wrote: >Thanks for your response. > >To simplify the case, just suppose that I have a 5k gate array ASIC designs >(general logic for control and interface)to implement to one CPLD(may be >CoolRunnerII) > >What's the relationship between the ASIC gate array and CPLD macrocells? > >"Andrew Paule" <lsboogy@qwest.net> >??????:ynlXa.981$h_3.65136@news.uswest.net... > > >>What kind of gates - If you are running standard cell type ASIC, then >>the vendor can give you a good idea. If it's a semi custom, you can >>figure about 40 transistors for most standard logic gates and flops, but >>you'll have to build your own and steer the currents with the available >>resistors. >> >>Are there mapped cells (i.e. cells that are fixed in your target ASIC)? >>Are there dedicated I/O flops, are there clock specific mask layers? >>You need the architecture of your target ASIC to get a good idea of this >>ratio, and the architecture of your FPGA -Actel SX and SXA can get >>pretty close to 1:1 for some types of ASICs, old PAL based CPLD >>structures are dependent on what they call a gate, most others are in >>between somewhere. >> >>Andrew >>Jay wrote: >> >> >> >>>Hi all, >>> >>>I'm doing prototyping for ASICs. Before I start my work, I have to >>> >>> >estimate > > >>>the gates the FPGA or CPLD would use. >>>I know it's hard to get a precise result. I just want some common answer, >>>1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just >>>logic) >>>Please tell me your experience. >>> >>>Thanks, >>>Jay >>> >>> >>> >>> >>> >>> > > > >Article: 59014
Hi Rob, Perhaps you could consider using a B5-X300 mainboard for your application - it is a low cost FPGA board that comes with a JTAG cable. I suggest this because, reading your previous post in this group, you also have a requirement for a device/board that can be plugged or mated to your custom board, for putting into your production design. We sell the B5-X300 boards: http://www.burched.com.au Many of our customers are building these boards into equipment, and then on-selling the complete product to their customers. They are using these boards as the "FPGA engine" for their products, and getting their products to market more quickly, and with less risk. We do unbeatable deals for volume purchases of the B5-X300 mainboards, and we support our customers during design and production phases. And we are in Australia, but we support customers in all countries. The B5-X300 has the XC2S300E device on it, which is currently the largest device supported by the free Xilinx Webpack tools. I remember the A4 digital audio processing ASIC that you are interested in, had about 191K transistors (note that this number is transistors, not gates), but alot of the internal processing was done with bit-serial arithmetic, which allowed a fairly small number of transistors, and hence silicon area. If you are using a high level language design methodology, and mostly parallel arithmetic, I would not be surprised if you utilised most of a 300E device to implement something similar to the A4, but I am only guessing. I agree with you that putting the micro in the FPGA would also be a great way to go. Best regards, Tony Burch http://www.BurchED.biz FPGA boards for System-On-Chip prototyping and education "Rob Judd" <judd@ob-wan.com> wrote in message news:3F2F7310.94F811D1@ob-wan.com... > Hi y'all, > > Right, we're making some progress on parts sourcing, thanks in no small > way to some of you out there who shall remain nameless to avoid > embarrassment. (Thanks!) > > What has come up next is the requirement for a JTAG programmer. I've > found one here: > > http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm > > but wonder whether using it on devices only capable of 3v3 or lower may > kill them. I'm also wondering whether some of the chips I'm considering > (Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx > XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs > that make a generic JTAG pod unworkable. If it merely requires level > translation, I'm golden. > > Comments? > > RobArticle: 59015
On Tue, 05 Aug 2003 12:18:31 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Alan Fitch wrote: >> >> "rickman" <spamgoeshere4@yahoo.com> wrote in message >> > This is the line of code producing the error... >> > >> > WaitTime := (ARM_command.RelTime - (now - CurrentTime)); >> > >> It sounds like Modelsim is confused. Is it actually an error, or just >> a warning? Having a signal read that is not in the sensitivity list >> is not an error. Can you disable Modelsim's synthesis checks? >I am getting the same error from a different assignment now. The common >point is that a signal is on the right hand side of the assignment and a >variable is on the left. I am using the variable assignment operator, >":=". This is reported as an error, not a warning. > > Last_Bus_Action := Bus_Command.Bus_Action; If that's the case, then assigning the record field to an intermediate signal would probably "fix" it. Not nice, but as an expedient to (a) keep moving and (b) home in on the real problem, maybe worth trying. -- parallel signal assignment tempAction <= Bus_Command.Bus_Action; -- within process or whatever Last_Bus_Action := tempAction; Assuming it works, then a support call to ModelSim, asking why one works, but not the other, would be very worthwhile. - BrianArticle: 59016
Hello,
How can I determine the memory map(in/out port, address, etc)
allocated by SOPC builder to user defined peripheral?
Thanks.
Article: 59017Andrew Paule wrote: > <snip>Let's say that this is a 2 input nand case - you need two of these for a simple flop, and can build logic accordingly - Wow, a flip-flop out of two 2-input NANDs ? Yes, you can make them into a latch with independenr SET and RESET (active Low), but you need 2 more gates to make it a D input, and you double the whole thing to get from a latch to a flip-flop. And then there is Clock Enable, and perhaps asynchronous CLEAR and/or PRESET, plus perhaps Clock inversion. You get all that in FPGA flip-flops "for free". I agree gate count is silly in FPGAs, but let's not distort the argument even further. Peter Alfke, XilinxArticle: 59018
Hi, This is a high level question about IP Core business models. I know about the "free" cores at opencores.org and I know you can pay someone $15,000.00 to license a USB core. What I'm looking for are companies that are in the middle whose pricing competes with dedicated chips. For example I need a USB 2.0 port on a project. I can call my NetChip rep and for $8-$15 (Qty. 30-50) a pop put a USB port in my design. Now for annual quantities in the low 100's the IP Core's $15,000 startup fee is out of the question. So my question is, are there any IP Core companies that compete with NetChip (or Cypress etc.) on pricing models? Thanks, KenArticle: 59019
Hi Peter: I agree 100% (an RS is the most fundamental valid flop) - and for a D type you do need two more gates. I guess that the whole premis here is that there is some talk going around trying to make an FPGA - ASIC conversion "standard", being able to count the whatevers in an FPGA and relate that to whatever type of gate the ASIC manufacturer is doing. Until there is an understnding of the ASIC type being targeted, and the FPGA type being used to proto, there cannot be any sort of gate counting relationship, but I don't want to jerk the poor guys chain too hard. I think that he's been assigned the task, and is trying to learn some fundamentals, albeit in the wrong frame. Andrew Peter Alfke wrote: >Andrew Paule wrote: > > >> <snip>Let's say that this is a 2 input nand case - you need two of these for a simple flop, and can build logic accordingly - >> >> > >Wow, a flip-flop out of two 2-input NANDs ? >Yes, you can make them into a latch with independenr SET and RESET >(active Low), but you need 2 more gates to make it a D input, and you >double the whole thing to get from a latch to a flip-flop. And then >there is Clock Enable, and perhaps asynchronous CLEAR and/or PRESET, >plus perhaps Clock inversion. >You get all that in FPGA flip-flops "for free". > >I agree gate count is silly in FPGAs, but let's not distort the argument >even further. >Peter Alfke, Xilinx > >Article: 59020
jaroslawk@hotmail.com (Jerry) wrote in message news:<711e889f.0308050755.12980a6e@posting.google.com>... > y_p_w@hotmail.com (y_p_w) wrote in message news:<591da479.0308041524.4ac35381@posting.google.com>... > > The URL would be too long. It's patent 6,601,126, and > > is available at <http://patft.uspto.gov/netahtml/srchnum.htm> > > Congratulations for USPTO: good work, boys! I've heard that the next > patent in line is: "round device that minimizes friction while moving > vehicles, a.k.a. wheel", granted for GM, of course... I couldn't agree more. How embarrassing it must be to admit that you work for the Patent Office ! I just hope that some large(r) company will file a nasty complaint with the USPTO and they recall the pattent again. This is really absurd ! I have been using the technique they are patenting back in the early 80th ... Cheers, rudi -------------------------------------------------------- www.asics.ws --- Solutions for your ASIC/FPGA needs --- ----------------- FPGAs * Full Custom ICs * IP Cores --- FREE IP Cores --> http://www.asics.ws/ <-- FREE IP CoresArticle: 59021
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F3079B9.9E9AD29C@yahoo.com>... > John wrote: > > > > Hi all: > > I have the following verilog codes which shift the serial data to parallel > > data.But it cost > > too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not > > what to do.Anybody would help me? > > > > reg[31:0] reg_in[7:0],reg_out[7:0]; > > > > always @(posedge clk) > > begin > > if(reset) > > cnt8<=0; > > else > > if(cnt8==7) > > begin > > cnt8<=0; > > reg_out[0]<=reg_in[0]; > > reg_out[1]<=reg_in[1]; > > reg_out[2]<=reg_in[2]; > > reg_out[3]<=reg_in[3]; > > reg_out[4]<=reg_in[4]; > > reg_out[5]<=reg_in[5]; > > reg_out[6]<=reg_in[6]; > > reg_out[7]<=reg_in[7]; > > end > > else > > begin > > cnt8<=cnt8+1; > > reg_in[0]<=reg_in[1]; > > reg_in[1]<=reg_in[2]; > > reg_in[2]<=reg_in[3]; > > reg_in[3]<=reg_in[4]; > > reg_in[4]<=reg_in[5]; > > reg_in[5]<=reg_in[6]; > > reg_in[6]<=reg_in[7]; > > reg_in[7]<=data_receive; > > > > end > > end > > I don't think an EAB will help you much. This code will use one LAB (8 > LEs) for the shift register and 3 or 4 more LEs for the counter. The > shift register can fit in an EAB (but not with the counter), so you will > save only one LAB for using an EAB. Why do you think this uses too many > LEs? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX Question... Wont you receive valid serial data when cnt8 = 8 ? Your code does not seem to sample serial data when cnt8 = 8 and just seems to output parallel data. - PrasannaArticle: 59022
In comp.arch.fpga Pacbell User <dont_reply@dont_reply.com> wrote: > > === > > The 'licensing' portion -- I understand that the 'GPL' license > is fairly restrictive in that it forces derivative works to be > distributed in documented *AND* modifiable form. This is not in most cases the problem with hardware licenced under GPL - the problem is that if you include such inside a larger work (processor, whetever), the rest of it has to be GPL aswell. > > My goal is to let *anyone* use my integer-divider as they see > fit. If they want to use it in a closed commercial project, that's > fine. It seems like a GPL-release cannot be used in a closed > project, is that correct? > > So under which license should I release my divider? LGPL, BSD, etc.?!? > The way to getting things be widely used is to use a BSD licence or similar (MIT, X11, png, zlib, etc). -- Sander +++ Out of cheese error +++Article: 59023
Ken Land wrote:
> This is a high level question about IP Core business models.
> I know about the "free" cores at opencores.org and I know you can pay
> someone $15,000.00 to license a USB core.
>
> What I'm looking for are companies that are in the middle whose pricing
> competes with dedicated chips.
This is like buying a used car, pricing is negotiable.
Cores are hard to sell and there are lots of sellers
and consultants.
Write a detailed proposal telling exactly what
your are doing and what your willing to pay.
In your case the value to you is about
$10 * 300 * 3 years = $9000.
So maybe offer $4500.
Request a compiled sim model and testbench
to evaluate the core.
Email it out, and you should get some responses.
Deal directly the author or his company
rather than resellers.
If they don't respond, or can't provide
a model and testbench, cross them off the list.
Like you say, you can always call NetChip instead.
-- Mike Treseler
Article: 59024rickman <spamgoeshere4@yahoo.com> wrote in message news:3F3079B9.9E9AD29C@yahoo.com... > > I don't think an EAB will help you much. This code will use one LAB (8 > LEs) for the shift register and 3 or 4 more LEs for the counter. The > shift register can fit in an EAB (but not with the counter), so you will > save only one LAB for using an EAB. Why do you think this uses too many > LEs? > > -- I guess you overlooked the register definition: reg[31:0] reg_in[7:0],reg_out[7:0]; Corret me if I am wrong, the code is actually converting an 8 bit wide data input to a 256 wide data output, so it requires much more than 8 LEs. Take a look at the link below to see if it helps: http://www.altera.com/support/software/eda_maxplus2/synplty/intro/logicop.ht ml Jim Wu jimwu88NOOOOOOSPAM@yahoo.com
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