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The DLL can handle either a 1x or 2x clk as it's feedback. It just can't use the fx or phase offset ouputs as the feedback Markus Meng wrote: > Hi All, > > I discovered that I use in my working application the x2 Clock Output > as the feedback - after the GBUF - for a DLL that deskews a 48Mhz > input clocks and provides to output clocks for internal usage. > > Is this wrong, I am not shure anymore, however I read in XAPP132 > and XAPP174 that you have to use x1 output signal - after the GBUF - > if you want to to make use of an internal x1 and x2 clock that > are in phase, controlled by one DLL... > > A short note would help > > markus > >Article: 57826
Be carefull. Usually when you instantiate a ibufg, you are actually instantiating a IOB configured as an input, and a bufg. You only want to use an IOB as the input and make sure it is loc'd to a clk input pin location. As for your div/2, you can divide the input to the dll by 2 using the CLKIN_DIVIDE_BY_2 parameter. Don't know if this helps because the clk0 will be div/2 since the dll is dividing the input to the dll. Markus Meng wrote: > Hi All, > > some notes I could not figure out directly from one of the XAPP132, 174 > from Xilinx. If I want to drive an Off-Chip device with half of the clkin > frequency > without using a GBUF driver, can I feedback the devided signal from the obuf > driving the pin through an IBUFG and still having the DLL functionality of > phase > shift an duty cycle correction. I read that the feedback signam MUST be > clkout > or 2xclkout. The problem is that I am running out of GBUF's in my design ... > > markus >Article: 57827
Hey guys, I'd recommend that splitting up your design into smaller projects is not the way to proceed, IMHO. You are just going to complicate your design and make it more difficult to simulate. How much memory does your PC have? What's the processor? Is the hard disk working a lot during compilation? Check the memory usage using the Task Manager: see if the machine is running out of RAM and paging to hard disk. If so, you should buy some more RAM: RAM is cheap, far cheaper than messing around with your project to get it to compile in a smaller memory space. Paging to hard disk will slow down compilation vastly (perhaps by a factor of 10 or more). You should alsi install DK2.0 SP1 and PDK 2.0. PDK 2.0 has a new standard library with more efficient implementations (in terms of compilation time) of the useful macros. Don't use the netlist simulator: this is old and has not been updated for a while. I think it is provided by Celoxica merely for backwards compatibility or for long-term users. The new simulator simulates a lot faster and is much more stable. Also, the netlist simulator cannot simulate multiple projects at once any more than the new simulator can. Make sure you have the latest version of the Xilinx tools with the latest service packs. Things you can look for are: heavy use of recursive macros. These should be avoided as they take a lot of time and memory to compile. Read the Celoxica Knowledge Base (http://www.celoxica.com/support) for tips on optimising your design: there is plenty of useful information there. Sometimes optimisations that produce more efficient code can also bring down the compilation time. Good designing Noel "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<bdpbf9$m5c$1$8302bc10@news.demon.co.uk>... > "P. Prasad" <pprasad@chandra.cse.iitb.ac.in> wrote in > message > news:Pine.GSO.4.40.0306212128530.29004-100000@chandra.cse.iitb.ac.in... > > Hi, > > I am working on a HANDELC project on Xilinx FPGA(RC1000 > board) and using Celoxica's DK1 environment. I have some > doubts regarding HANDELC. I am new to HANDELC and FPGA. > > > > > > The Problem > > ----------- > > > > As the project is getting bigger and bigger, the > compilation(synthesis into EDIF) time is taking many hours. > So the goal is to reduce the compilation time. > > > > My experience of this is that people don't think enough > about hardware. > For instance, if you divide by 2^12, I have seen code where > people write > > A = B /4096; > > This will result in HandelC attempting to synthesise a large > divider. > This is a) very slow in hardware b) very slow to compile. > > So my first suggestion is to look through your code for > "sillies" like this. > You can get big clues by getting the timing and area reports > from DK1 and > correlating them with the code you've written. > > (By the way, the above line should be > > A = B << 12; > > which essentially synthesises to some wires!) > > So step one is to check the code for sensible "hardware" > style coding. > > > > The approach which I tried to use was to break up the > program into smaller parts, compile these into separate > EDIFs and hook them into the main HANDELC program using > interfaces(ports). So the parts of the program which have > already been synthesized into EDIF do not take any time at > all thus saving lot of time. > > > > But I am doing some mistake in my code and I am clueless > to what is wrong. Actually I feel that I need to synchronise > the EDIF component with the main HANDELC program but don't > know how ( maybe use interfaces properly???). I have given > below the detailed description of the things I tried. > > You approach makes sense. Remember that you need to create > separate > mains (i.e. separate projects) in DK1 to create separate > EDIF netlists. > > Secondly, when you combine everything, you cannot simulate > it in > the C simulator - you would have to simulate it in the > netlist simulator. > > I guess in your example below, you are talking about "actual > hardware" > rather than simulation? > > So step 2 is to check you are using the netlist simulator. > > Other than that, your code looks sensible, > > regards > > Alan > > -- > Alan Fitch > HDL Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * > Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, > Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: > alan.fitch@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > The contents of this message may contain personal views > which are not the > views of Doulos Ltd., unless specifically stated.Article: 57828
HI,
I have a Avnet Spartan2 board, if I download the the .mcs (prom
file) comming with the board to it, it seems everything is OK. Then I
build my design, went through the implementation flow, and I run a
script to run impact.exe,
setMode -bscan
setCable -p lpt1
addDevice -p 1 -part xc18v01
addDevice -p 2 -file download.bit
program -p 2
quit
but what I see is at the end of its running is like this,
'2':Programming device...done.
INFO:iMPACT:579 - '2': Completed downloading bit file to device.
INFO:iMPACT:580 - '2':Checking done pin ....done.
'2': Programming terminated, Done did not go high.
----------------------------------------------------------------------
----------------------------------------------------------------------
Done.
Do you know what might be the problem? Note that I have the same P4
download cable, JTAG cable and power supply.
Thanks,
Jim
Article: 57829Hi I encountered a problem during synthesis and I really hope I can get your help. I declared a std_logic_vector(7 downto 0) (inout type) entity port in my VHDL program. In the testbench, I will try to assign some value to this port. But after synthesis using Synopsys Design Compiler, I found this port wouldn't accept the value from signal assignment in the test bench and the value of this port becomes "XX". BTW, even I initialize this port to "ZZZZZZZZ" in the entity definition, it still doesn't work. Thanks a lot. MikeArticle: 57830
I have searched around the net (googled groups and web) for an existing eCOS port for Altera's NIOS. Did find on the red hat site some limited discussion about somebody wanting to port. Altera's web site had a press release about supporting an eCOS port for NIOS but no ported code. Is there any interest in this group about an eCOS port? Right now we are using a RTOS that has royalties associated with it which is bad for my profit sharing. Is this the proper group to bring this subject up? Is there anybody out there that would participate in a port? regards JerryArticle: 57831
On Mon, 07 Jul 2003 14:05:47 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >I have not been having a good day (weekend actually) trying to download >the Altera web edition software. Large downloads like this normally >take three or so tries to get the full file. > >But I find that I am not able to get a license file anyway. I don't >have an Ethernet adapter in the PC where I will be running the tools and >the web site is not set up for anything else. So what do I need to do >to get running with quartus web edition? You can select the 30 day trial license option. Don't need an adapter for that. After the 30 days check the warez groups probably be a crack available by then.Article: 57832
On Mon, 7 Jul 2003 21:41:57 -0400, "Jerry" <nospam@nowhere.com> wrote: >I have searched around the net (googled groups and web) for an existing eCOS >port for >Altera's NIOS. Did find on the red hat site some limited discussion about >somebody wanting to port. >Altera's web site had a press release about supporting an eCOS port for NIOS >but no ported code. > >Is there any interest in this group about an eCOS port? Right now we are >using a RTOS that has >royalties associated with it which is bad for my profit sharing. > >Is this the proper group to bring this subject up? Is there anybody out >there that would participate in a port? > >regards >Jerry > > have you tried uCOSII ? >Article: 57833
Thanks Krzysztof I've tried comparing the environment variables between the working and the non working accounts but they are the same, so it has to be something else. Thank you anyway NirArticle: 57834
"Jimy" <jim@hotmail.com> schrieb im Newsbeitrag news:3F0A0919.5BA08E3@hotmail.com... > HI, > I have a Avnet Spartan2 board, if I download the the .mcs (prom > file) comming with the board to it, it seems everything is OK. Then I > build my design, went through the implementation flow, and I run a > script to run impact.exe, > > setMode -bscan > setCable -p lpt1 > addDevice -p 1 -part xc18v01 > addDevice -p 2 -file download.bit > program -p 2 > quit > > > but what I see is at the end of its running is like this, > > > '2':Programming device...done. > INFO:iMPACT:579 - '2': Completed downloading bit file to device. > INFO:iMPACT:580 - '2':Checking done pin ....done. > '2': Programming terminated, Done did not go high. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Done. > > > > Do you know what might be the problem? Note that I have the same P4 > download cable, JTAG cable and power supply. > > Thanks, > Jim > > > Hello Jim, think You want to program a ser. PROM. Did YOU already try to create a *.mcs file for the serial PROM instead of a *.bit file? with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail info@seng.de net http://www.seng.de #############################Article: 57835
GSR sets the internal registers to their initial state. If you want to reconfigure you need to drive the oe/reset pin of the prom then the prog_b of the fpga. You can do this from the fpga itself. Steve "Charles Krinke" <someone@pacbell.net> wrote in message news:UhlOa.161$q%6.95@newssvr16.news.prodigy.com... > Gentlemen: > I have a situation where some of my compatriots want to be able to reset > a Virtex2 in order to reload the program from the 18V04 chips. Generally, > they are going to want to do this after they have loaded a new image into > the eprom's and they want to do it under program control. > > Would I be correct in assuming that all they need to do is instantiate > glbl.v in their design and assert the GSR signal hi? At that point, the chip > should tri-state that same assertion and all the other signals, read the > eproms and start afresh? > > Charles > >Article: 57836
> What does "multiple" mean? More than one column. There is a load multiple column command. This loads columns that are contigous to each other. Usually the reconfiguration process loads one column on the left side of the die and then one on the right side of the die. This is to distribute the current evenly over the chip. > If I take the 30 ms boundary seriuosly a full (re)configuration would > destroy the device :o) A full configuration loads one side then the other. > > Is it possible to create a reconfigurable design with a static and a > dynamically changed > module arranged on top of each other (share the same columns)? > Actually, it should work with differential bitstreams due to the fact that > only bits are toggled > that where modified. You answered your own question. The answer is "yes." The "static" bits of the design would just get reloaded as they are. SteveArticle: 57837
Guys, About your postings on comp.arch.fpga : Take a look at Intrinsyc's uEngine. http://www.intrinsyc.com/products/microEngine/ FPGA + CPU of choice on a Dimm. Tell them I sent ya... maybe they will give me discount for forwarding inquiries... (I'm saving up now, to maybe buy one). Bram Stolk On Wed, 2 Jul 2003 18:07:31 +0000 (UTC) "Leon Heller" <leon_heller@hotmail.com> wrote: > > <eholbrook@austin.rr.com> wrote in message > news:874r24dalp.fsf@vole.holby-net... > > I'm looking for a DIMM format FPGA board like Pilchard or the AcB from > > (now defunct?) Nuron. I've done several web searches, but found > > nothing that both fits the bill, and is from a company that is > > apparently alive. I've found a couple of things that are close to what > > i want (from mite.cz, and sunrise-systems.de), but they don't return > > emails, so i figure they're dead, too. > > > > Has anyone heard of something like this, or do i need to design/build > > it myself? > > I was thinking of developing one. How about us collaborating? > > Leon > -- > Leon Heller, G1HSM > leon_heller@hotmail.com > http://www.geocities.com/leon_heller > > -- ------------------------------------------------------------------------------ Bram Stolk, VR Specialist. SARA Academic Computing Services Amsterdam, PO Box 94613, 1090 GP AMSTERDAM email: bram@sara.nl Phone +31-20-5923059 Fax +31-20-6683167 "Gates' Law: Every 18 months, the speed of software halves." ------------------------------------------------------------------------------Article: 57838
I have the need to duplicate the code that is in one Altera EPC2 to another one on an identical bit of hardware. The device has a 10 pin JTAG connector. Is there a low cost, easy way to suck the bits out and put them into the other EPC2? I also have a .jbc file as well if that makes it easier. I was doing a flash upgrade but the device reset before it finished resulting it a dead bit of hardware. To get it fixed, it has to be sent 1/2 world away and tech support hasn't ever done that and don't know if they can even fix it so I'm looking for a better option if one exists. -tim http://web.abnormal.comArticle: 57839
> In extremely long product life markets you have to warehouse everything. > Any board that is old enough to have a 3000 on it is full of components > that haven't been manufactured for years. Chances are you have parts that > were made by companies that aren't even in business anymore. The only way > that you can continue to make those boards is to have stockpiles of parts. > If you are stockpiling parts then you can stockpile software and a couple > of old computers to run it on. Keeping and a couple of old Sparc 1s or 386 > PCs in the corner is far cheaper then stockpiling components. Actually, we are able to still procure all of the components for that board. All of the companies are still in business. I'm not even sure why you are making these remarks as you don't work for us. Again, we do end up keeping old PCs around and our older copies of the software if they were used to create a design. I would need to do this even if our friends at Xilinx stopped dropping support for parts every few years. > One more thing, you said the reason for continuing to build outdated > systems is the cost of qualifying a new design. Well the same goes for > tools, you don't want to have to qualify a new tool set on the old parts > just so you can do a bug fix. You know that the old tools worked, you > don't know what bugs would pop up in the new tools if you tried to use > them for a really outdated part. I have to qualify each new tool as they become available. You are right, it takes a lot of time which prevents me from releasing every new update for our own internal use. If the Xilinx did not remove support for devices as the tools advance I would qualify them for older designs. Again, to allow us to leverage a standard user interface, etc.Article: 57840
Hello, I want to make a phase measurement at 100MHz with a NCO at 200+ MHz This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The output will be only one bit. I will use a phase comparator followed by an integrator (digital or analogic if needed). At 100MHz the NCO output will be very very noisy but if I integrate it for a rather long time (10ms) will it have a 0 mean ? Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? Where can I find some maths on this subject ? Thanks Marc BattyaniArticle: 57841
Marc Battyani wrote: > > Hello, > > I want to make a phase measurement at 100MHz with a NCO at 200+ MHz > This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The > output will be only one bit. > I will use a phase comparator followed by an integrator (digital or analogic > if needed). > At 100MHz the NCO output will be very very noisy but if I integrate it for a > rather long time (10ms) will it have a 0 mean ? > Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? > Where can I find some maths on this subject ? A 32 bit accumulator will have very, very low noise in the digital domain due to the high resolution. If you need to convert this to analog, you will find significant noise from the discrete time sampling. However the noise level will be affected by your filter. The phase noise is an AC measurement so it will not integrate to zero over time. With a 32 bit phase accumulator, I expect nearly all of your phase noise will be due to your osciallator source giving time error of the samples. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57842
Hi. My company is working on a xc2v8000 design, I expect it to be almost fully utilized (85%). I feel that our computing power is not sufficient. I am using Sun Ultra-80 with 4 GB memory. fpga_editor and floorplanner take a lot of time. P&R flow takes a lot of time. I read in Xilinx docs that the recommendation for xc2v8000 is 3 GB memory. Do you have from your experience additional recommendations, such as graphic card type, Processor, memory, or a brand name computer that you successfully use? ThankX NAHUMArticle: 57843
Hi Nir,
Have you tried changing directory to the bin directory where grep, ls,
etc executables are ("cd /bin" should probably take you there in the
Nios Bash shell)?
From there, type ./ls and press enter.
If this works, your PATH variable has problems.
-- Pete
nir_drabkin@hotmail.com (Nir) wrote in message news:<9b862770.0307070826.214d4754@posting.google.com>...
> Hello to All
>
> I don't know what I did wring but I've uninstalled Nios by mistake and
> when I try to install it back, I get the following messages when I run
> the sopc_builder and also the bash:
> bash.exe: warning: could not find /tmp, please create!
> bash: uname: command not found
> bash: grep: command not found
> bash: uname: command not found
> bash: grep: command not found
> bash: uname: command not found
> bash: grep: command not found
> bash: uname: command not found
> ...
>
> This is very weird, because when I try to go directly to
> C:\Altera\Excalibur\sopc_builder_2_5\Cygwin\bin and double click the
> bash.exe file I also get a message saying that /tmp is not found and
> it does not know any commands (grep, uname, ls etc).
>
> I've uninstalled and reinstalled Nios but with no success. One success
> I did have though: when I log in as a different user all is well. The
> problem is that I don't to log in as a different user each time I have
> to work on Nios.
>
> This has happened a few times to other people in my company and we
> could not get any help from our local Altera representative. I'm sure
> someone here must have encountered this in the past. Please help me
>
> Thanks in advance
> Nir
Article: 57844Rick, In article <3F0C25FB.7BC1C0C9@yahoo.com>, spamgoeshere4@yahoo.com says... > Falk Brunner wrote: > > Get a download manager like Gozilla or something. The can resume a aboarded > > download. > > My concern is that once installed, I will have no way to control it if I > don't want to use it for some files. I remember Netscape adding > something like this (or I added some download, I can't remember which). > There were times I did not want it to pop up and could not find a way to > turn it off. It also showed ads while running. > > Anyone know of a review of download utilities that would help me pick > one? WGET! Wget does it all and it's open source, doesn't include spyware, works really really well (hey, some of us HAVE been on dial-up too). Thanks, TRArticle: 57845
On Tue, 08 Jul 2003 05:21:50 -0700, lecroy wrote: >> In extremely long product life markets you have to warehouse everything. >> Any board that is old enough to have a 3000 on it is full of components >> that haven't been manufactured for years. Chances are you have parts >> that were made by companies that aren't even in business anymore. The >> only way that you can continue to make those boards is to have >> stockpiles of parts. If you are stockpiling parts then you can stockpile >> software and a couple of old computers to run it on. Keeping and a >> couple of old Sparc 1s or 386 PCs in the corner is far cheaper then >> stockpiling components. > > Actually, we are able to still procure all of the components for that > board. All of the companies are still in business. I'm not even sure why > you are making these remarks as you don't work for us. Again, we do end > up keeping old PCs around and our older copies of the software if they > were used to create a design. I would need to do this even if our friends > at Xilinx stopped dropping support for parts every few years. > I made this statement because one of my clients is in a marketplace (military and medical) where they ship systems for years and years because the customers don't care about the costs they just don't want to rewrite or requalify software. These systems contain lots of parts that either haven't been made for years (for example the Intel I860) or where the manufacturer has lost the recipe (they had problems with a TI FIFO for example where TI had made a mask fix on the original but then failed to duplicate the fix when they tried to move production to a newer process). That company stockpiles the parts they need. They also never throw out a copy of Xilinx tools, they have a bookcase full of old tools). >> One more thing, you said the reason for continuing to build outdated >> systems is the cost of qualifying a new design. Well the same goes for >> tools, you don't want to have to qualify a new tool set on the old parts >> just so you can do a bug fix. You know that the old tools worked, you >> don't know what bugs would pop up in the new tools if you tried to use >> them for a really outdated part. > > I have to qualify each new tool as they become available. You are right, > it takes a lot of time which prevents me from releasing every new update > for our own internal use. If the Xilinx did not remove support for > devices as the tools advance I would qualify them for older designs. > Again, to allow us to leverage a standard user interface, etc. You don't seem to understand that Xilinx isn't removing support for the old devices, they aren't adding support for those devices to new tools. Even though the names of the programs remain the same, map, par, etc..., they aren't necessarily the same code at all from release to release. Periodically Xilinx completely rewrites some component. They do this because the requirements change for each new generation. Not only are there major architectural changes that they have to accommodate but the huge jump in size that occurs with each new family requires new routing technology. Whenever a major rewrite occurs the amount of testing work that is required to assure an acceptable level of quality is huge. It's not realistic to expect that they qualify every part that they've ever made on the new version of the tool, if they did it would adversely the tool quality for the current generation of parts. It also serves no purpose for them to support parts that are not available for new designs. Those parts are supported by the tool set that was current when the part was current. The version of the tools that was around at the tail end of the life of any particular part is going to have the fewest bugs for that part. If you were to add support for old parts into the new tools you would expect that the new tools to be riddled with bugs for that part for the simple reason that nobody is using that tool set on that part, and therefore nobody is finding the bugs. Anyone who uses a brand new part knows how buggy the tools can be for the first six months or so. Now imagine that you are the only person in the world that was using that part, the bugs would never get fixed. That's exactly the situation that an obsolete part would be in if it were supported by the newest tools. It would be like the part was perpetually in beta release.Article: 57846
I need to vent a little steam. So at risk of making myself look stupid (or more stupid) I will do it here. I have been trying to get the Quartus 3.0 software and a license since last Thursday. I tried three times over the weekend to download it, but the slow modem link I have to use would not complete the entire transfer without a problem. I think I have that licked as my brother tells me he has downloaded it for me. But I have been trying to get a license file that does not require an Ethernet interface and am getting nowhere. I have received several emails from Altera people who say that they support this and I need to contact my local FAE or the main office. I have tried to do both. All of the FAEs I know are either on vacation or in California at training. Calling both 800 numbers has gotten me nowhere since I reach people who are the "first line" and always have to refer it to someone else. I have left about half a dozen voice mails, sent easily a dozen emails, spoken with two types of support and still I have not heard back from anyone at Altera about this. Right now I have been holding for about 15 minutes waiting for a third number to connect me with a person. I know that if I was this hard to get ahold of no one would *ever* buy any of my products! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57847
> Does anybody knows if this condition > affects only simulation? If you see it in the simulation then there is a good chance that it is going to happen in the hardware. If you see it in hardware you may be able to reproduce it in the simulator. That is life. SteveArticle: 57848
"Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message news:beedln$ina@library2.airnews.net... > Hello, > > I want to make a phase measurement at 100MHz with a NCO at 200+ MHz > This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The > output will be only one bit. A 1-bit output will give you NCO phase noise that has a range of 5nS peak-to-peak based only on the single bit output. The only exception to this value is when you run at a fractional value such as 100 MHz from the 200MHz clock where the accumulator acts as a divide-by 2. [I guess all frequencies will be a fractional relation - 1329046/2^32 is still a fraction. The arguement applies to small whole number fractions such as 3/16.] The way to get good performance from the system is to use the full DDS - an NCO with a D/A such as those very nifty Analog Devices parts. > I will use a phase comparator followed by an integrator (digital or analogic > if needed). > At 100MHz the NCO output will be very very noisy but if I integrate it for a > rather long time (10ms) will it have a 0 mean ? If you compare the phase to a noise-free reference that is precisely the desired frequency, the low-passed output of the phase comparator will conceptually be the phase offset between your NCO and the noise-free reference. I say conceptually because this is not a practical test. If you're trying to figure out of the phase noise is "lopsided," you should find the phase comparator output is some form of sawtooth. If the frequency is very close to a fraction of the 200MHz clocking frequency, your phase comparator output will appear to recover from a step function while the reality is that it's a very long sawtooth. Your frequency give you results with phase variations that are much closer in time where it's hard to see the longer term sawtooth characteristics beyond the very large, high frequency variations you see without the lowpassing. > Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? The NCO can be implemented in the FPGA. You could drive a D/A with the FPGA though it's recommended that the D/A's clock be sourced direclty from your low phase-noise source rather than passing the clock through the FPGA. The DDS chips with integrated D/As are the best for this kind of thing. > Where can I find some maths on this subject ? Unfortunately, the maths are a little loose on the phase noise results. I've only seen textbook treatment of simple jitter: a sinusoidal phase variation. The Bessel function is a result of the Fourier of the sin(wt+Psin(at)) kind of form (ah, my kingdom for an ohmega, phi, or alpha on this keyboard). The Bessels give you only a slight idea of what happens in the NCO realm. The investigations I did went through a theoretical setup I described above. Determine the time domain of the phase comparator output from your NCO compared to the "ideal" noise-free reference mathematically. The pattern will repeat when the NCO accumulator values repeat which will happen at least every 2^32 cycles. This time-domain result might be what you seek. The frequency domain interested me, so I took the FFT of the time domain. If you're only interested in close-in phase noise and higher frequencies are a non-issue, there are ways to increase the peak-to-peak phase noise while decreasing the close-in phase noise. A google on "MASH" and "frequency synthesis" might bring up results on that advanced subject. > Thanks > > Marc BattyaniArticle: 57849
I have been playing around with the idea of a 32-bit DDS circuit at 200 MHz ( as a digitally controlled VCO) and I know some tricks to reduce the timing uncertainty from the obvious 5 ns by a factor of 4. Then I was going to use an external PLL to reduce it further. These are just ideas... Peter Alfke ============= Marc Battyani wrote: > > Hello, > > I want to make a phase measurement at 100MHz with a NCO at 200+ MHz > This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The > output will be only one bit. > I will use a phase comparator followed by an integrator (digital or analogic > if needed). > At 100MHz the NCO output will be very very noisy but if I integrate it for a > rather long time (10ms) will it have a 0 mean ? > Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? > Where can I find some maths on this subject ? > > Thanks > > Marc Battyani
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