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When you write up a patent you are expected to be an expert in the field and give the patent examiner _all_ the prior art associated with your invention. The problem occurs when the applicant tries to hide prior art that may damage or invalidate their claim. You see if what you claim is important and there is money to be made someone else will dig up the prior art and you will be out of luck. It will cost time and money for everyone. While the patents from SRC look like they have all the prior art they don't. There is a good chance if it goes to trial they will loose. Steve > > > From what I hear, SRC Computers holds patents in this area and is not > > > licensing to anyone right now. > > > > > > www.srccomp.com > > > > What! > > > > maybe I read it too fast maybe I just can't read patents or maybe > > I just don't understand, but don't they basically claim that they > > have patented programble logic memory mapped on a microprocessor? > > > > I would have guessed that that is widely used and has been for some > > time :) > > > > -Lasse > > > I think your reading it right, I would have thought it was widely used as well.Article: 57951
I tried to implement a 1024 word FFT using the XILINX CoreGen, but seems that the program is unable to produce the outputs. Does anyone have the same problem? Thank youArticle: 57952
> Therefore, the soultion in the app note (using a phase shifted internal > clock to capture the read data) is the only way to go. The interesting thing of that app note is that it uses DQS to latch the read data first and then transfer the latched data to read clock domain. Why don't latch the read data directely by read clock (which is phase shifted ddr_clk)? I really don't see any advantage of using DQS to latch read data. Similarly, since the > DQ/DQS timing relationship is required to do writes to the DDR-SDRAM, it is > necessary to generate a delay, either using a DCM or board delays (as is > done in the app note). > DQS for writing is not a big issue. A 90 degree-dalayed ddr_clk will do the job. As long as the DQS PCB trace is the some length as other data traces, the DQS will alway arrive the memory at centre of the data valid phase. > AvrumArticle: 57953
When I compile my program I get a warning on the range of these two constants under Quartus 3.0 web edition. I checked some other copies of NUMERIC_STD that I have on my hard drive and found them all to be the same. What is this about? What are these constants for and why are they defined this way? Should this report as a warning? package body NUMERIC_STD is -- null range array constants constant NAU: UNSIGNED(0 downto 1) := (others => '0'); constant NAS: SIGNED(0 downto 1) := (others => '0'); From my days of C programming, I am uncomfortable with warning statements. If there are warnings, even if they are not problems, I get rid of them so that they don't obscure warnings about *real* problems. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57954
Hi,
The actual flipflops in the FPGA (assuming its a Xilinx part) will clock on
EITHER edge (but not on both) depending on how your design is defined. The
Look-Up Table (LUT) is just exactly that. For example a 4 input LUT can be any
one of the possible 16 binary combinatorial functions of 4 inputs (2^4). I took
a relatively simple 3 credit course at the local university on VHDL and FPGA's.
For me the only hard part was in figuring out how to get an FPGA to actually
load from a serial EEPROM. (Hint: read the book. Read the book again. If you
are really lucky, look at someone elses functional design. Call Xilinx for
technical support. Figure that you are going to need to make some minor tweeks
in the board for the first prototype. I had the advantage to start with the now
obsolete SpartanXL. That eliminated dealing with the two supply voltages and
the DLL's, etc. so all I had to deal with was serial programming.)
Theron
juice28 wrote:
> Marc,
>
> Thanks for taking the time to reply. I have a pretty good understanding of
> digital design, but this stuff is a bit foreign to me. I am starting to
> grasp the idea of how they work and how to design a circuit in the
> schematics editor and burn it, but the vhdl part I fear I will never
> understand. It also seems that the Xilinx software is very picky and buggy.
> I am unfortunatly using a old version as its the only one I could get
> running on my win 98 computer. I think its version 3.1
>
> The Flip flops in the schematics don't tell you if they clock on pos or neg
> clock cycle or if the enable is pos or neg. I assum the logic such as ands
> and ors are positive logic. Any ideas on this.
>
> Thanks again for your help.
>
> Fred
> "Marc Guardiani" <marc@guardiani.com> wrote in message
> news:7IycncIHnbQcJZGiRTvUqA@fyi.net...
> > Fred,
> >
> > It's more than just the software, you also have to understand the
> > hardware... :-)
> >
> > There is only a Q output from the flip-flop. Just use an inverter.
> >
> > You can clock and reset the flip-flops from either dedicated signals or
> > from global nets. There are restrictions on the global reset net. I
> > don't know about schematics, but in VHDL if you use *any* asynchronous
> > clear in your design, ISE will use the normal routing resources for the
> > reset. If you have *no* asynchronous resets, the global reset net will
> > be used.
> >
> > The best pin to use for the clock is the dedicated clock pin.
> >
> > The best (and only) pin to use for the global reset net is the dedicated
> > global set/reset pin.
> >
> > Marc
> >
> > juice28 wrote:
> > > Could someone please let me in on how the Flip Flops work in ISE Webpack
> > > schematics. Where is the Q/ . Do I simply run an inverter off from Q or
> > > what. Are these also global clk and rst or only if you assign them that
> way.
> > > When running a clock into the chip for a design (say 6mhz) which pin is
> best
> > > to use? Sorry for all the Newbe questions but this stuff is hurting my
> > > head.... Man why can't they just use easy software like Palasm :)
> > >
> > > Thanks,
> > >
> > > Fred
> > >
> > >
> > >
> >
> > --
> >
> >
> > Marc Guardiani
> >
> > To reply directly to me, use the address given below. The domain name is
> > phonetic.
> > fpgaee81-at-eff-why-eye-dot-net
> >
Article: 57955Hi, I'm currently building an oversampling DAC for digital audio. I'm having a hard time figuring out how to design the fpga so that it can accept multiple audio data rate. The digital output of a cd player (SPDIF format) is converted to serial I2S using the CS8416 chip from crystal semiconductor (http://www.cirrus.com/en/products/pro/detail/P1005.html). The I2S signal is fed into a Xilinx SpartanIIE fpga where serial to parallel conversion is performed so that the 16-bit words of audio data are recovered. I thus have a 16-bit register which is updated at the original audio sample rate (Fs = 44.1khz). The DAC is basically a sigma-delta modulator that works at 64 times oversampling so that my output bit-rate is around 2.8224Mhz. In my current design, the fpga is clocked with a 256Fs (11.2896Mhz) and I enable the D-flipflops of the modulator at 64Fs. This keeps the design synchroneous and everything works. However, if I use a 48kHz digital audio source (computer soundcard for example), nothing works anymore. I would have to change the clock of the fpga so that it runs at 256Fs, where Fs is now 48kHz. This is obviously not a good solution... Here are the solutions I can think of: -The easiest one would be to clock the fpga using the clock signal generated by the CS8416 chip (it outputs a 256Fs clock). This way, I would always be synchronous with the CS8416. I wonder however if it is a good design practice to use this kind of signal to clock the fpga. Furthermore, since this clock is not always present (during reset and startup), I would need another clock directly fed in the fpga to clock the controller and other logic. Is this acceptable? -If the above does not work, I guess I would need to upsample/decimate the incoming data so that it always end up being a fixed frequency (a multiple of the fpga clock). This would add a lot of complexity to the system and the signal quality would be affected since the filters are not perfect. I'm sure this is a common 'problem' in digital design. I would really appreciate any help/guidelines. Thank you very much DavidArticle: 57956
Theron Hicks wrote: > > Hi, > The actual flipflops in the FPGA (assuming its a Xilinx part) will clock on > EITHER edge (but not on both) depending on how your design is defined. The > Look-Up Table (LUT) is just exactly that. For example a 4 input LUT can be any > one of the possible 16 binary combinatorial functions of 4 inputs (2^4). There actually are more than 65000 different functions of the four input variables. This is another one of my pet interview questions, that I have used since 1975, long before Xilinx was founded... Peter AlfkeArticle: 57957
I found this on xilinx website: http://www.xilinx.com/support/programr/files/0380507.pdf Seems to be what I need (it's different from the cable I got...specially for the feedback signals). However, I'm wondering about the power supply. The parallel port is 5V and my XC18V02 is 3.3V. Do I simply supply the 74HC125 with 3.3V and hope the parallel port will work with that ? Thanks "..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message news:_C2Pa.101491$Il3.2931504@wagner.videotron.net... > Hi, > > I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm > developing under Xilinx ISE 5. I'm wondering what would be the simplest JTAG > cable I could build (or buy if real cheap) to download my code in the PROM. > Is any JTAG cable supposed to do the job? The fact is I already a very > simple JTAG interface (with a 74HC244 buffer for parallel port)...I tried it > but it didn't work. > > Thanks > >Article: 57958
On Thu, 10 Jul 2003 16:28:39 -0400, Theron Hicks <hicksthe@egr.msu.edu> wrote: >Hi, > The actual flipflops in the FPGA (assuming its a Xilinx part) will clock on >EITHER edge (but not on both) depending on how your design is defined. Right. The distributed clock can be selectively inverted at each slice (so flip flops are paired for this selection), so that while the flip flops are only clocked by the rising edge, since the clock can be inverted, the effect is that it can be clocked by the falling edge. Another alternative in some FPGA families is to distribute both normal and inverted clocks (from a DCM). This can reduce some clock symetry issues related to inverting the clock at each CLB. >The >Look-Up Table (LUT) is just exactly that. For example a 4 input LUT can be any >one of the possible 16 binary combinatorial functions of 4 inputs (2^4). Actually, it is 3984 interesting functions, not 16. The correct description of what a LUT can do is: "Any combinatorial function of 4 or fewer inputs, 1 output, and no feedback". See here: http://www.fpga-faq.com/FAQ_Pages/0022_How_many_permutations_can_a_4LUT_have.htm http://www.fpga-faq.com/archives/23500.html#23505 >I took >a relatively simple 3 credit course at the local university on VHDL and FPGA's. >For me the only hard part was in figuring out how to get an FPGA to actually >load from a serial EEPROM. (Hint: read the book. Read the book again. Right. Maybe read the book once more. It is all in there. >If you >are really lucky, look at someone elses functional design. Call Xilinx for >technical support. Figure that you are going to need to make some minor tweeks >in the board for the first prototype. Maybe look at this too, and the links it has: http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm >I had the advantage to start with the now >obsolete SpartanXL. That eliminated dealing with the two supply voltages and >the DLL's, etc. so all I had to deal with was serial programming.) > >Theron Philip Philip Freidin FliptronicsArticle: 57959
Followup to: <DikPa.7509$Pe2.141735@wagner.videotron.net> By author: "David" <gretzteam@hotmail.com> In newsgroup: comp.arch.fpga > > -The easiest one would be to clock the fpga using the clock signal generated > by the CS8416 chip (it outputs a 256Fs clock). This way, I would always be > synchronous with the CS8416. I wonder however if it is a good design > practice to use this kind of signal to clock the fpga. Furthermore, since > this clock is not always present (during reset and startup), I would need > another clock directly fed in the fpga to clock the controller and other > logic. Is this acceptable? > This would make sense. Typically you feed that clock into a PLL/DLL, and your "other" clock into another PLL/DLL on the chip. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57960
Hi,
I'm having a problem doing behavioral simulation for VHDL code using
Modelsim. The problem is that the simulator ignores the rising edge
of any signal but the clock from the testbench process. It ignores
combinational logic signals' rising edges as well as DCM outputs. I'm
using the code "wait until (clk'event and clk='1');" to detect the
edge. If I use the clock signal straight from the test bench process,
i.e. not from the DCM output, then everything works fine.
Any ideas what's going on? I attached the code below for two of the
entities, not including the testbench. I appreciate any help. Thanks!
Pete
(1):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pn_generate is
port(clk : in std_logic;
clk2x: in std_logic;
reset: in std_logic;
en : in std_logic;
q : out std_logic_vector(7 downto 0));
end pn_generate;
architecture behavioral of pn_generate is
component rrc_filter
port (
ND: IN std_logic;
RDY: OUT std_logic;
CLK: IN std_logic;
RST: IN std_logic;
RFD: OUT std_logic;
DIN: IN std_logic_VECTOR(0 downto 0);
DOUT: OUT std_logic_VECTOR(16 downto 0));
end component;
attribute box_type : string;
attribute box_type of rrc_filter: component is "black_box";
constant seed : std_logic_vector(14 downto 0) :="000000000000011";
signal stored_value : std_logic_vector(14 downto 0);
signal i1, qint : std_logic;
signal qint_vec : std_logic_vector(0 downto 0);
signal rrc_ready, rrc_rfd : std_logic;
signal rrc_dout : std_logic_vector(16 downto 0);
begin
process
begin
wait until (clk'event and clk='1'); -- RISING EDGE IGNORED
HERE.
if reset ='1' then
stored_value <= seed;
q <= (others=>'0');
qint <= '0';
i1 <= '0';
else
if true then
i1 <= stored_value(4) xor stored_value(0);
stored_value <= i1 & stored_value(14 downto 1);
qint <= stored_value(0);
else
i1<=i1;
qint <= stored_value(0);
end if;
end if;
q <= "0000000" & qint;
qint_vec(0) <= qint;
end process;
U2 : rrc_filter
port map (
ND => clk, -- new data (when asserted, sample at DIN is
loaded.)
RDY => rrc_ready, -- output data ready.
CLK => clk2x,
RST => reset,
RFD => rrc_rfd, -- ready for data (meaning finished with
current calculation.)
DIN => qint_vec,
DOUT => rrc_dout);
end behavioral;
(2):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--synopsys translate_off
library UNISIM;
use unisim.vcomponents.all;
--synopsys translate_on
entity wcdma is
port( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
PNOUT : out STD_LOGIC_VECTOR(7 downto 0));
end wcdma;
architecture inside of wcdma is
component pn_generate
port(clk : in std_logic;
clk2x: in std_logic;
reset: in std_logic;
en : in std_logic;
q : out std_logic_vector(7 downto 0));
end component;
COMPONENT DCM1
PORT(
rst_in : IN std_logic;
clkin_in : IN std_logic;
locked_out : OUT std_logic;
clk2x_out : OUT std_logic;
clk0_out : OUT std_logic
);
END COMPONENT;
signal clk_dcm, clk_dcm_2x, dcm_locked : std_logic;
begin
u1 : pn_generate
port map( clk => clk_dcm,
clk2x => clk_dcm_2x,
reset => reset,
en => enable,
q => pnout);
Inst_DCM1: DCM1 PORT MAP(
rst_in => reset,
clkin_in => clk,
locked_out => dcm_locked,
clk2x_out => clk_dcm_2x,
clk0_out => clk_dcm);
end inside;
Article: 57961
You are aware of course that Xilinx does not recommend cascading more than two
DLLs. The reason is the max jitter spec for them to stay locked. If you have a
clean clock source and are careful, you can get away with 3 DLLs in cascade, but
it is not recommended for a long career. I don't know what the real minimum is,
but it is greater than 2 clocks. Given that, it is cheaper to use the SRL16 for
the delay than using other delay methods, in which case the recommended 16 clock
delay costs you no more than a 2 clock delay. In the case of the virtexE, you
have a max of 8 DLLs, so you need a maximum of 4 invert-delays if you follow the
recommended cascade limitations, which takes up 4 slices. I'll bet if you look
hard enough at your design you could shake loose 4 slices worth of LUTs. In a
pinch you can be a bit creative with tbufs, carry chains, unbonded i/o etc to
help shake loose extra resources.
Morten Leikvoll wrote:
> I do a rather heavy cascaded clock division/multiplication using DLL's in a
> VirtexE and have problems with routing resources from/to the dll's.
> I do not have enough resources to route all LOCKED signals through an
> inverter (and delay for 2x feedback's) and therefore do a delayed reset from
> one to the next. My question is:How much delay do I need to be sure that the
> output of one DLL is locked before I reset the next one? Does anyone have
> experience with this?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 57962On a sunny day (Thu, 10 Jul 2003 16:48:33 -0400) it happened "David" <gretzteam@hotmail.com> wrote in <DikPa.7509$Pe2.141735@wagner.videotron.net>: >Hi, >I'm currently building an oversampling DAC for digital audio. I'm having a >hard time figuring out how to design the fpga so that it can accept multiple >audio data rate. >The digital output of a cd player (SPDIF format) is converted to serial I2S >using the CS8416 chip from crystal semiconductor >(http://www.cirrus.com/en/products/pro/detail/P1005.html). The I2S signal is >fed into a Xilinx SpartanIIE fpga where serial to parallel conversion is >performed so that the 16-bit words of audio data are recovered. I thus have >a 16-bit register which is updated at the original audio sample rate (Fs = >44.1khz). > >The DAC is basically a sigma-delta modulator that works at 64 times >oversampling so that my output bit-rate is around 2.8224Mhz. In my current >design, the fpga is clocked with a 256Fs (11.2896Mhz) and I enable the >D-flipflops of the modulator at 64Fs. This keeps the design synchroneous and >everything works. > >However, if I use a 48kHz digital audio source (computer soundcard for >example), nothing works anymore. I would have to change the clock of the >fpga so that it runs at 256Fs, where Fs is now 48kHz. This is obviously not >a good solution... Here are the solutions I can think of: Interesting, why not use 2 xtals, and a frequency detector (one shot will do) and switch on input frequency. xtals are cheap.Article: 57963
Hi, Anyone know if exist any implementation, for free, of 802.11 protol on FPGA? ThanksArticle: 57964
David wrote: > > Hi, > I'm currently building an oversampling DAC for digital audio. I'm having a > hard time figuring out how to design the fpga so that it can accept multiple > audio data rate. > The digital output of a cd player (SPDIF format) is converted to serial I2S > using the CS8416 chip from crystal semiconductor > (http://www.cirrus.com/en/products/pro/detail/P1005.html). The I2S signal is > fed into a Xilinx SpartanIIE fpga where serial to parallel conversion is > performed so that the 16-bit words of audio data are recovered. I thus have > a 16-bit register which is updated at the original audio sample rate (Fs = > 44.1khz). > > The DAC is basically a sigma-delta modulator that works at 64 times > oversampling so that my output bit-rate is around 2.8224Mhz. In my current > design, the fpga is clocked with a 256Fs (11.2896Mhz) and I enable the > D-flipflops of the modulator at 64Fs. This keeps the design synchroneous and > everything works. > > However, if I use a 48kHz digital audio source (computer soundcard for > example), nothing works anymore. I would have to change the clock of the > fpga so that it runs at 256Fs, where Fs is now 48kHz. This is obviously not > a good solution... Here are the solutions I can think of: > > -The easiest one would be to clock the fpga using the clock signal generated > by the CS8416 chip (it outputs a 256Fs clock). This way, I would always be > synchronous with the CS8416. I wonder however if it is a good design > practice to use this kind of signal to clock the fpga. Furthermore, since > this clock is not always present (during reset and startup), I would need > another clock directly fed in the fpga to clock the controller and other > logic. Is this acceptable? > > -If the above does not work, I guess I would need to upsample/decimate the > incoming data so that it always end up being a fixed frequency (a multiple > of the fpga clock). This would add a lot of complexity to the system and the > signal quality would be affected since the filters are not perfect. > > I'm sure this is a common 'problem' in digital design. I would really > appreciate any help/guidelines. > Thank you very much > David Yes, this is a common problem. But the solution is not hard. If you pick a clock rate that is higher than the 256 * Fs of your fastest signal, you can generate an enable from which ever clock domain you wish to be synchronous with. Then the fast clocked circuit will run on a clock by clock basis as enabled by (and data is presented to or from) the source clocked domain. The clocks don't actually need to be synchronized. The data and handshakes do however. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57966
If anyone interest in a FPGA DIMM module using Xilinx Virtex (XCV600) with 512K SRAM, onboard 10/100 Ethernet + Flash + JTAG/ROM/CPLD and 16bit PCM Codec please email me. The board size is 5.25" x 3" 168 pins DIMM module. The next batch of production run is due in 3 weeks, bare board PCB and semi assemble board are available nowArticle: 57968
Hi, My question is about QR-RLS algorithm implementing in FPGA or ASIC chips. I have read the article (http://www.quixilica.com/pdf/asilomar99.pdf). But I cannot understand the meaning in table 5. Especially in the last three rows, the plus sign with two numbers. It is a long time for me to think about it. Could you help me? Thanks in advanceArticle: 57969
Peter, Mea culpa. I think I _have_ seen that before. Maybe this time it will stick. Theron Peter Alfke wrote: > Theron Hicks wrote: > > > > Hi, > > The actual flipflops in the FPGA (assuming its a Xilinx part) will clock on > > EITHER edge (but not on both) depending on how your design is defined. The > > Look-Up Table (LUT) is just exactly that. For example a 4 input LUT can be any > > one of the possible 16 binary combinatorial functions of 4 inputs (2^4). > > There actually are more than 65000 different functions of the four input variables. > This is another one of my pet interview questions, that I have used > since 1975, long before Xilinx was founded... > > Peter AlfkeArticle: 57970
I don't really understand what you mean...Could you please give me a very simple example with numbers? Thank you very much David > > Yes, this is a common problem. But the solution is not hard. If you > pick a clock rate that is higher than the 256 * Fs of your fastest > signal, you can generate an enable from which ever clock domain you wish > to be synchronous with. Then the fast clocked circuit will run on a > clock by clock basis as enabled by (and data is presented to or from) > the source clocked domain. > > The clocks don't actually need to be synchronized. The data and > handshakes do however. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57971
Jun wrote: > I really don't see any advantage of using DQS to latch read data. A very simplified example. Suppose the Clock period was 10 ns. Clock to DQS/data varied from 2 to 8 ns, and delay tracks, or in other words, if the data delay is 7 ns, the DQS delay is also 7 ns. As the half period of the clock is 5 ns, there is NO time that the data can be sampled by clock. After the data is sampled by DQS, it is now no longer double data rate, and can be sampled by plain old clock (with 2 ns setup and 2 ns hold). -- Phil HaysArticle: 57972
David wrote: > > I don't really understand what you mean...Could you please give me a very > simple example with numbers? > Thank you very much > David > > > > > Yes, this is a common problem. But the solution is not hard. If you > > pick a clock rate that is higher than the 256 * Fs of your fastest > > signal, you can generate an enable from which ever clock domain you wish > > to be synchronous with. Then the fast clocked circuit will run on a > > clock by clock basis as enabled by (and data is presented to or from) > > the source clocked domain. > > > > The clocks don't actually need to be synchronized. The data and > > handshakes do however. It depends on exactly what you are doing with the data. If you are processing word samples, then you only need a clock as fast as the fastest sample rate you expect to see. If you are doing work at a multiple rate then you need a clock at that multiple rate of your highest sample rate. When a sample comes in, your interface circuit provides an enable for that clock cycle. The next stage of logic will process the data and pass the enable on to the next stage. On any clock cycle where there is no data from the interface, no enable should be provided and the data and enable are not clocked through to the next stage. The only tricky part is generating the enable since that will have to cross clock domains. But since the sample rate is much slower than the clock rate, if I understand what you are doing, then you will be passing one enable pulse every 256 clocks (at the most) and the circuit in the high speed clock domain will generate how ever many enables are needed to complete the processing. Depending on the exact nature of your processing and clocks, you may need a double register or possibly a FIFO if the clock rate is close to the sample rate. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57973
If the little XC18V's will do it, the big ones will too. Just ignore the extra bits. The Spartan will stop clocking when it's done. What you're really looking for doesn't exist, and won't. The Spartan and the SpartanXL are dead parts (in Xilinx's view). Sorry, SH On Thu, 10 Jul 2003 12:36:57 +0930, Anup Kumar Raghavan <araghava@asc.corp.mot.com> wrote: >I need to select a Configuration solution for programming the Spartan XL >XCS10XL device. I have chosen to use the Master Serial Mode >configuration using the PROM XC17S10XL, which is OTP. I havent found any >reference to ISP (EPROM) solutions for the Spartan XL and hence need >some advice on this. I know there is this device XC18V256PC20C, but >Xilinx mentions that this is not supported anymore. > >Thanks and regards >AnupArticle: 57974
I have been away from VHDL for a while since my last few projects were
Verilog. Now I am trying to get Quartus working (which I am not overly
familiar with either) and my simple test program won't give me the
hardware I want. It is not making the tristate buffers and connecting
them up like they should. I expect I am doing something very simple
wrong, but I have been looking at this code for hours as well as putting
in all sorts of things to try to show me my problem. But it keeps doing
the same thing, no tristate buffers (well, they are there, but they are
not driven with anything).
I added some "KEEP" directives to try to force it to retain some of the
signals and now it *tells* me it is deleting them. But it is still the
same result. Here is the full code. Everything other than the register
read and write logic is added to try to debug something. The only
register bit that is synthesized is bit 0 and both the signal and the
control inputs to the tristates are ground.
I am guessing that it has something to do with the fact that the INOUT
is both the input and the output of the register and the tristates. Or
do I need to do something special for chip IOs?
-- VHDL created by Rick Collins
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.STD_LOGIC_ARITH;
ENTITY Test1 is
PORT (
-- ADC Board Signals
Data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
CSN : IN STD_LOGIC;
RDN : IN STD_LOGIC;
WRN : IN STD_LOGIC;
LED : OUT STD_LOGIC;
Reset : IN STD_LOGIC;
SysClk : IN STD_LOGIC); -- 50 MHz Clock
END Test1;
ARCHITECTURE behavior OF Test1 IS
constant SysClkRate : real := 50000.0; -- Rate in KHz
signal DataIn : STD_LOGIC_VECTOR (7 downto 0);
signal DataOut : STD_LOGIC_VECTOR (7 downto 0);
signal ScratchReg : STD_LOGIC_VECTOR (7 downto 0);
signal ReadScratchReg : STD_LOGIC;
attribute keep: boolean;
attribute keep of DataIn: signal is true;
attribute keep of DataOut: signal is true;
attribute keep of ReadScratchReg: signal is true;
BEGIN
ReadScratchReg <= (not RDN) WHEN (Addr = "00001000") and (CSN =
'0') ELSE '0';
Data <= DataOut WHEN (ReadScratchReg = '1')
ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z');
DataIn <= Data;
DataOut <= ScratchReg;
ScratchRegister: process (SysClk, Reset) begin
if (Reset = '1') then
ScratchReg <= (others => '0');
elsif (rising_edge(SysClk)) then
if (Addr = "00001000") THEN
if (WRN = '0' and CSN = '0') THEN
ScratchReg <= DataIn (7 downto 0);
end if;
end if;
end if;
end process ScratchRegister;
LED <= ScratchReg(0) AND ReadScratchReg;
END behavior;
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
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