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Hi all,
'figthing' maybe with a clock skew problem, I get the following report out
of the
FPGA Editor from a local clock - no global clock lines:
Net "LVDS_RX3_CLK_c":
driver - Pin "D12.I"
4.402ns - Pin "D7.CLK"
4.154ns - Pin "CLB_R1C25.S0.CLK"
4.220ns - Pin "CLB_R1C24.S1.CLK"
4.435ns - Pin "CLB_R1C28.S0.CLK"
4.344ns - Pin "CLB_R1C27.S1.CLK"
4.344ns - Pin "CLB_R1C27.S0.CLK"
4.342ns - Pin "CLB_R1C26.S1.CLK"
4.342ns - Pin "CLB_R1C26.S0.CLK"
4.181ns - Pin "CLB_R1C22.S0.CLK"
4.448ns - Pin "CLB_R1C29.S0.CLK"
4.089ns - Pin "CLB_R1C21.S0.CLK"
4.448ns - Pin "CLB_R1C29.S1.CLK"
4.220ns - Pin "CLB_R1C24.S0.CLK"
4.089ns - Pin "CLB_R1C21.S1.CLK"
4.085ns - Pin "CLB_R1C20.S0.CLK"
4.435ns - Pin "CLB_R1C28.S1.CLK"
4.181ns - Pin "CLB_R1C22.S1.CLK"
4.152ns - Pin "CLB_R1C23.S1.CLK"
I see that there is a certain clock delay, however the skew is ~0.6ns.
Is this still in the allowable range for a Spartan-II 200 -5 device?
Can I count on those numbers to be worst case?
ISE 5.1i SP3
Best Regards
Markus
--
Mit freundlichen Grüssen
Markus Meng
P.S. Achtung wir haben eine neue FAX-Nummer
********************************************************************
** Meng Engineering Telefon 056 222 44 10 **
** Markus Meng Natel 079 230 93 86 **
** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! **
** CH-5400 Baden Email meng.engineering@bluewin.ch **
** Web www.meng-engineering.ch **
********************************************************************
** You cannot create experience. You must undergo it. Albert Camus**
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Article: 57201Hi, I need to interface an IDE hard drive to a Spartan2E. The trouble is the Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are 5V. Does anyone know a simple method to get around the voltage problem? I don't suppose the Spartan2E could tollerate a 5V input? I found a company called BurchEd which sells an IDE interface to a Spartan2E evaluation board. Looking at the picture of the IDE interface it has no logic between the hard drive and the Spartan2E. How do they do it? Thanks for any help,Article: 57202
Hi: Here's a chronicle of today's headaches. 1. ECS schematic editor can't deal with filenames that contain anything except 0-9 a-z A-Z . 2. I selected a large block of schematic, and when I tried to move it, ECS said "Internal Error: Delete Branch" 3. I guess nobody uses schematic entry because the editor is simply impossible to use. It is an absolute disaster. I try to select a group of objects to move, and it simply won't let me select them. They don't highlight. I try to select everything I have drawn to move it, and I get error mentioned in #2 above. The autorouting is useless. Get rid of it. Hint: humans are smarter than computers. Just let me draw my own wires. 4. Oh good grief, I moved some things, and then I simply cannot select anything anymore. You see folks, when you make software this bad, even if it is free, rather than making me want to pay for the "good" software, it makes me think you simply can't write good software. What evidence do I have that if I pay for your non-free tools, that they will be any better? None. On the contrary, I have volumous evidence that I will simply be paying for the exact same thing, only I will not only be frustrated, but poorer. The end result is the same. I can't use your silicon. So perhaps I have made a big mistake. Perhaps I should have gone with Altera. I just don't know now. Or perhaps analog design would be a way to avoid all this crap altogether. I don't seem to have much trouble with SPICE simulators. Heck even Linear Technology's LTSpice *FREE* simulator is very useable. Argh! 5. I closed the schematic editor hoping that if I re-opened my file it might reset som eof its internal data structures, and start working again. Now I try to reopen my schematic source from Project Navigator, and nothing happens. It simply sits there when I click "open". <Mr. Carlen strikes head with palm, to try to wake up from the bad dream.> Nope this is reality. Bummer. Aha! Project Navigator couldn't open my source because it didn't have the same name that I created it with. I created it as "cross32-52" which Project Navigator accepted just fine. But ECS wouldn't save the file with this name, even though it opened it the first time. So I saved it as something else, which of course broke Project Navigator. Well that's certainly my fault. I should have expected ECS to not save filenames with '-' characters. 6. After closing everything an reopening, I can select and move things in ECS again. Oh joy! 7. I wanted to start a new project to develop a modified version of a previous design done from scratch in 5.2i. I copied the .sch and .ucf files to the new project dir. I can edit the schematic, so I deleted some stuff I didn't want in there. Then I can't open the .ucf file because it has nets that aren't in the schematic. I don't know why in the original project, when I would add or remove nets from the schematic, the user constraints file was automatically updated to reflect the nets in the schematic. This doesn't work now, but perhaps it's because there is some file missing. So I will remove the .ucf source and add a new one which I'll set up from scratch. I click "remove" and then I add a new source, a user constraints with the same name as the one that isn't working. Project NAvigator prompts me if I want to overwrite the old file. I click "Ok" and expect that when I open the new .ucf file, it will be a reflection of the nets in my schematic. No such luck, the broken .ucf was not everwritten, so it still complains of errors of missing nets. Well that's all before lunch time. Let's see what happens this afternoon... I guess if there's a point to all this, I should look around on Xilinx's web site some more and find out where to report bugs. But I have reached a point with software in general where I am tired of doing this. That is because, I often wind up spending hours reporting the bugs in the rigorous detail that is needed if there is to be any hope of anyone actually fixing them. Unless of course, the software had been rigorously tested in the first place. -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.Article: 57203
Sorry to refer to such an ancient device - but can anyone point me to either a reverse compiler for the GAL16V8 or the definition of its fuse map bits to be able to derive the logic function from same? Our company bought another years ago and the products from them that we're making often have no documentation or source code. In getting ISO certified we have to reengineer what's going on. We have all the rights to the designs - we just don't know what they are(!!). Any pointers will be most appreciated. Jim Horn, Penngrove, CaliforniaArticle: 57204
iMPACT is telling you that you are getting all 0's back from the device when it is expecting the IDCODE. Assuming the device is currently unprogrammed, I would first check your physical cable connections to the device making certain that the device itself and the cable are both properly powered This error does not appear to be related to the software tk wrote: > Hi all, > > I get the following error when I try to program xc2vp7 device using iMPACT > (ISE 5.1i): > > ERROR:iMPACT:583 - '1': The idcode read from the device does not match the > idcode in the bsdl File. > INFO:iMPACT:629 - '1': Device IDCODE : 00000000000000000000000000000000 > INFO:iMPACT:630 - '1': Expected IDCODE: 00000001001001001010000010010011 > > I've found that this problem is discussed in the Xilinx web page: > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=16490 > > However, I don't use the encryption function for the bitstream. Why I still > get the problem? > Even I install the service pack 3, the problem is still there. > Can anyone kindly tell me how to solve it? > Thanks in advance. > > tk > > > PS: the following are the options used by BitGen: > > Summary of Bitgen Options: > +----------------------+----------------------+ > | Option Name | Current Setting | > +----------------------+----------------------+ > | Compress | (Not Specified)* | > +----------------------+----------------------+ > | Readback | (Not Specified)* | > +----------------------+----------------------+ > | CRC | Enable** | > +----------------------+----------------------+ > | DebugBitstream | No** | > +----------------------+----------------------+ > | ConfigRate | 4** | > +----------------------+----------------------+ > | StartupClk | JtagClk | > +----------------------+----------------------+ > | DCMShutdown | Disable** | > +----------------------+----------------------+ > | DisableBandgap | No** | > +----------------------+----------------------+ > | CclkPin | Pullup** | > +----------------------+----------------------+ > | DonePin | Pullup** | > +----------------------+----------------------+ > | HswapenPin | Pullup* | > +----------------------+----------------------+ > | M0Pin | Pullup** | > +----------------------+----------------------+ > | M1Pin | Pullup** | > +----------------------+----------------------+ > | M2Pin | Pullup** | > +----------------------+----------------------+ > | PowerdownPin | Pullup** | > +----------------------+----------------------+ > | ProgPin | Pullup** | > +----------------------+----------------------+ > | TckPin | Pullup** | > +----------------------+----------------------+ > | TdiPin | Pullup** | > +----------------------+----------------------+ > | TdoPin | Pullnone | > +----------------------+----------------------+ > | TmsPin | Pullup** | > +----------------------+----------------------+ > | UnusedPin | Pulldown** | > +----------------------+----------------------+ > | GWE_cycle | 6** | > +----------------------+----------------------+ > | GTS_cycle | 5** | > +----------------------+----------------------+ > | LCK_cycle | NoWait** | > +----------------------+----------------------+ > | Match_cycle | NoWait | > +----------------------+----------------------+ > | DONE_cycle | 4** | > +----------------------+----------------------+ > | Persist | No* | > +----------------------+----------------------+ > | DriveDone | No** | > +----------------------+----------------------+ > | DonePipe | No** | > +----------------------+----------------------+ > | Security | None** | > +----------------------+----------------------+ > | UserID | 0xFFFFFFFF** | > +----------------------+----------------------+ > | ActivateGclk | No* | > +----------------------+----------------------+ > | ActiveReconfig | No* | > +----------------------+----------------------+ > | PartialMask0 | (Not Specified)* | > +----------------------+----------------------+ > | PartialMask1 | (Not Specified)* | > +----------------------+----------------------+ > | PartialMask2 | (Not Specified)* | > +----------------------+----------------------+ > | PartialGclk | (Not Specified)* | > +----------------------+----------------------+ > | PartialLeft | (Not Specified)* | > +----------------------+----------------------+ > | PartialRight | (Not Specified)* | > +----------------------+----------------------+ > | Encrypt | No** | > +----------------------+----------------------+ > | Key0 | pick* | > +----------------------+----------------------+ > | Key1 | pick* | > +----------------------+----------------------+ > | Key2 | pick* | > +----------------------+----------------------+ > | Key3 | pick* | > +----------------------+----------------------+ > | Key4 | pick* | > +----------------------+----------------------+ > | Key5 | pick* | > +----------------------+----------------------+ > | Keyseq0 | M* | > +----------------------+----------------------+ > | Keyseq1 | M* | > +----------------------+----------------------+ > | Keyseq2 | M* | > +----------------------+----------------------+ > | Keyseq3 | M* | > +----------------------+----------------------+ > | Keyseq4 | M* | > +----------------------+----------------------+ > | Keyseq5 | M* | > +----------------------+----------------------+ > | KeyFile | (Not Specified)* | > +----------------------+----------------------+ > | StartKey | 0* | > +----------------------+----------------------+ > | StartCBC | pick* | > +----------------------+----------------------+ > | IEEE1532 | No* | > +----------------------+----------------------+ > | Binary | No** | > +----------------------+----------------------+ > * Default setting. > ** The specified setting matches the default setting. > >Article: 57205
Hi all, I've been testing both Quartus II 2.2 and a copy of Quartus II 3.0 beta on Gentoo Linux 1.4 in bleeding-edge mode and both work just fine. I suggest that Peter downloads a stock kernel (2.4.21 is the most recent in the 'stable' series), configures, compiles and installs it, and then tries again running this stock kernel. The current GUI portability layer (no, not Wine, it's MainWin) and the tools themselves are probably using the old LinuxThreads stuff, and there may be other low-level things that RedHat has mad incompatible with earlier versions. Ben leon qin wrote: > I have run Quartusii 2.2 SP2 on Slackware 9.0. > I think because Redhat 9.0 adopt LWP lib instead of LinuxThreads lib,so > Quartusii 2.2 might not runs well on Redhat 9.0. > > leon > > > "H. Peter Anvin" <hpa@zytor.com> wrote in message > news:bd8mr9$cm4$1@cesium.transmeta.com... >> Since I see that some Altera people are reading this group... the >> current version of Quartus II has a Linux version, which I have access >> to; however, it's a Winelib application and they only formally support >> RedHat 7.1, which is ancient by now. It does not work on my RedHat 9 >> workstation. >> >> Does Altera have any plans to upgrade this to a modern version of >> Linux? >> >> -hpa >> -- >> <hpa@transmeta.com> at work, <hpa@zytor.com> in private! >> "Unix gives you enough rope to shoot yourself in the foot." >> Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 >> x86-64 -- BenArticle: 57206
Christopher wrote: > Hi! > > Does anyone know or have used the Quartus II? If so, I am looking for > an inexpensive FPGA such that I can build a cable to communicate with > the chip directly. I don't want to purchase the programmer. Some of > these kits are $150. I am on a budget and just want to get my feet > wet. Download the datasheet of Altera's ByteBlaster cable. The schematic is in there, and the actual component cost is not that high (a few resistors, a TTL buffer, a parallel cable connector, some ribbon cable and a 10-pin header), so you may be able to construct the circuit using a little piece of breadboard PCB. As to a the FPGA kit - while you're at it you may want to buy a PLCC44 wire-wrap socket and stick that on the breadboard as well. Once you've done that you could buy an EPM7064SLC44 CPLD for a few dollars that you could then program the device with. Best regards, BenArticle: 57207
James Horn <jimhorn@svn.net> writes: > either a reverse compiler for the GAL16V8 or the definition of its fuse > map bits to be able to derive the logic function from same? GALs are made by Lattice. They still make them. The data sheets are on their website as PDFs. They have (at least in the old copies I have) in them descriptions of signalling, frame format, bit arrangement, and fuse map. Should be enough to reverse engineer one. Hmmm, just looked on the website, only fuse numbers are given: http://www.latticesemi.com/lit/docs/datasheets/pal_gal/16v8.pdf?CFID=2538619&CFT OKEN=27693493 Pages 5 and 7. I am sure I once saw an description of this stuff, somewhere in the 50M of Lattice docs I got on CD-ROM. IIRC it is frames of 5 bits command, 6 bits address and then 32 or 40 bits data, per row of fuse bits. Or something like that. Look out for repeatin identical 5 bits "load" command, woth incrementing 6bits of address, 0, 32, 64, ... (if 20pin) or 0, 40, 80, ... (if 24pin). -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 57208
Markus, you have to distinguish between physics and worst-case simulation: Clock skew becomes a problem when the downstream flip-flop is triggered later than the upstream flip-flop, and this clock skew exceeds the sum of clock-to-out + routing + set-up time. And it's the real delay that matters, not the worst-case simulation delay. Mathematically: If min ( clock-to-out +routing + set-up) < clock skew, then you will have a race condition if the destination flip-flop is the one that is triggered late. A positive hold time, which is the extreme case of a "short set-up" can easily get you in trouble. I have used that question with hundreds of job applicants... Peter Alfke Markus Meng wrote: > > Hi all, > > doing some "night shift investigations ...:-)" I did find out, that a local > clock skew of > ~500 psec seems to work with no problems at all. I even move the voltage and > change > the temperature, and it still works. However I have the 'feeling' that in > the range of > 1ns clock skew between the FF's it might get a problem. > > However it would be nice if some folks from Xilinx could describe the > minimum > requirements for the Spartan-II 200 -5 regarding max local clock skew ... > > markus > > "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag > news:3ef9bf6c_8@corp.newsgroups.com... > > Hi all, > > > > 'figthing' maybe with a clock skew problem, I get the following report out > > of the > > FPGA Editor from a local clock - no global clock lines: > > > > Net "LVDS_RX3_CLK_c": > > driver - Pin "D12.I" > > 4.402ns - Pin "D7.CLK" > > 4.154ns - Pin "CLB_R1C25.S0.CLK" > > 4.220ns - Pin "CLB_R1C24.S1.CLK" > > 4.435ns - Pin "CLB_R1C28.S0.CLK" > > 4.344ns - Pin "CLB_R1C27.S1.CLK" > > 4.344ns - Pin "CLB_R1C27.S0.CLK" > > 4.342ns - Pin "CLB_R1C26.S1.CLK" > > 4.342ns - Pin "CLB_R1C26.S0.CLK" > > 4.181ns - Pin "CLB_R1C22.S0.CLK" > > 4.448ns - Pin "CLB_R1C29.S0.CLK" > > 4.089ns - Pin "CLB_R1C21.S0.CLK" > > 4.448ns - Pin "CLB_R1C29.S1.CLK" > > 4.220ns - Pin "CLB_R1C24.S0.CLK" > > 4.089ns - Pin "CLB_R1C21.S1.CLK" > > 4.085ns - Pin "CLB_R1C20.S0.CLK" > > 4.435ns - Pin "CLB_R1C28.S1.CLK" > > 4.181ns - Pin "CLB_R1C22.S1.CLK" > > 4.152ns - Pin "CLB_R1C23.S1.CLK" > > > > I see that there is a certain clock delay, however the skew is ~0.6ns. > > Is this still in the allowable range for a Spartan-II 200 -5 device? > > > > Can I count on those numbers to be worst case? > > ISE 5.1i SP3 > > > > Best Regards > > Markus > > > > > > -- > > Mit freundlichen Grüssen > > Markus Meng > > > > P.S. Achtung wir haben eine neue FAX-Nummer > > ******************************************************************** > > ** Meng Engineering Telefon 056 222 44 10 ** > > ** Markus Meng Natel 079 230 93 86 ** > > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > > ** Web www.meng-engineering.ch ** > > ******************************************************************** > > ** You cannot create experience. You must undergo it. Albert Camus** > > > > > > > > > > > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > > -----== Over 80,000 Newsgroups - 16 Different Servers! =----- > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 57209
Hi all, doing some "night shift investigations ...:-)" I did find out, that a local clock skew of ~500 psec seems to work with no problems at all. I even move the voltage and change the temperature, and it still works. However I have the 'feeling' that in the range of 1ns clock skew between the FF's it might get a problem. However it would be nice if some folks from Xilinx could describe the minimum requirements for the Spartan-II 200 -5 regarding max local clock skew ... markus "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag news:3ef9bf6c_8@corp.newsgroups.com... > Hi all, > > 'figthing' maybe with a clock skew problem, I get the following report out > of the > FPGA Editor from a local clock - no global clock lines: > > Net "LVDS_RX3_CLK_c": > driver - Pin "D12.I" > 4.402ns - Pin "D7.CLK" > 4.154ns - Pin "CLB_R1C25.S0.CLK" > 4.220ns - Pin "CLB_R1C24.S1.CLK" > 4.435ns - Pin "CLB_R1C28.S0.CLK" > 4.344ns - Pin "CLB_R1C27.S1.CLK" > 4.344ns - Pin "CLB_R1C27.S0.CLK" > 4.342ns - Pin "CLB_R1C26.S1.CLK" > 4.342ns - Pin "CLB_R1C26.S0.CLK" > 4.181ns - Pin "CLB_R1C22.S0.CLK" > 4.448ns - Pin "CLB_R1C29.S0.CLK" > 4.089ns - Pin "CLB_R1C21.S0.CLK" > 4.448ns - Pin "CLB_R1C29.S1.CLK" > 4.220ns - Pin "CLB_R1C24.S0.CLK" > 4.089ns - Pin "CLB_R1C21.S1.CLK" > 4.085ns - Pin "CLB_R1C20.S0.CLK" > 4.435ns - Pin "CLB_R1C28.S1.CLK" > 4.181ns - Pin "CLB_R1C22.S1.CLK" > 4.152ns - Pin "CLB_R1C23.S1.CLK" > > I see that there is a certain clock delay, however the skew is ~0.6ns. > Is this still in the allowable range for a Spartan-II 200 -5 device? > > Can I count on those numbers to be worst case? > ISE 5.1i SP3 > > Best Regards > Markus > > > -- > Mit freundlichen Grüssen > Markus Meng > > P.S. Achtung wir haben eine neue FAX-Nummer > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ** Web www.meng-engineering.ch ** > ******************************************************************** > ** You cannot create experience. You must undergo it. Albert Camus** > > > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =----- -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 57210
XC3430 has never been a standard Xilinx part ( I know, I have been here since the old XC3000 family was introduced in late '87). We also checked that it is not a Philips-derived CPLD name either. It is possible that the name was once used for a "hardwire" part, effectively a custom circuit, in which case there cannot be a meaningful data sheet. This tries to be a friendly and helpful newsgroup. Let's keep it that way... Peter Alfke ======================================== eawckyegcy@yahoo.com wrote: > > I am looking for a datasheet for this part. > > The Xilinx website says that to obtain a datasheet for a discontinued > part you have to "open a case" with them, which requires you register > with them, providing all sorts of irrelevant, but very personal > details of your life, and then, "for your security", you must wait a > "full business day" to confirm the registration. > > I'm hoping someone can dispense with this nonsense and just email me > the PDF file.Article: 57211
Thanks, Neil! I saw the spec page but missed the fuse information. It's all there indeed. Now to plot dots and manually simplify. Many thanks again! Jim HornArticle: 57212
Yes, you have discovered the not-so-secret of the lack of bug support for schematic users. I can't say this is unique to Xilinx since I have never tried schematic with Altera parts. But I expect the problem will not get better with time. I can say I am a bit surprised. A few years ago Xilinx was using an editor that was not perfect, but worked ok. I guess this was something they were paying for per license and were eating the cost. To save that fee I assume they switched to something they bought or wrote in house. Regardless, you will be better off using an HDL than schematics. A lot of people fought tooth and nail against HDL, but it is a better solution for large designs and the FPGA vendors really don't want to have to support both. So the support for schematic is not good simply because not many people use it and why spend money supporting something that is little used. I know you are thinking, "why have it if you don't support it?" I can't answer that one, you will need to ask X and A. But I can say you are definitely swimming upstream with schematic capture. I know I did my last schematic design some years ago and will not look back (or look the schematics up :) Keep in mind the number of bugs you have found so far and you only worked for half a day. Wait until you try to place and route your schematic design! You will really be having fun then! Just think of all the newer chip features and how poorly they will be supported via schematic. Chris Carlen wrote: > > Hi: > > Here's a chronicle of today's headaches. > > 1. ECS schematic editor can't deal with filenames that contain anything > except 0-9 a-z A-Z . > > 2. I selected a large block of schematic, and when I tried to move it, > ECS said "Internal Error: Delete Branch" > > 3. I guess nobody uses schematic entry because the editor is simply > impossible to use. It is an absolute disaster. I try to select a group > of objects to move, and it simply won't let me select them. They don't > highlight. I try to select everything I have drawn to move it, and I > get error mentioned in #2 above. The autorouting is useless. Get rid > of it. Hint: humans are smarter than computers. Just let me draw my > own wires. > > 4. Oh good grief, I moved some things, and then I simply cannot select > anything anymore. > > You see folks, when you make software this bad, even if it is free, > rather than making me want to pay for the "good" software, it makes me > think you simply can't write good software. What evidence do I have > that if I pay for your non-free tools, that they will be any better? > None. On the contrary, I have volumous evidence that I will simply be > paying for the exact same thing, only I will not only be frustrated, but > poorer. The end result is the same. I can't use your silicon. > > So perhaps I have made a big mistake. Perhaps I should have gone with > Altera. I just don't know now. > > Or perhaps analog design would be a way to avoid all this crap > altogether. I don't seem to have much trouble with SPICE simulators. > Heck even Linear Technology's LTSpice *FREE* simulator is very useable. > > Argh! > > 5. I closed the schematic editor hoping that if I re-opened my file it > might reset som eof its internal data structures, and start working > again. Now I try to reopen my schematic source from Project Navigator, > and nothing happens. It simply sits there when I click "open". > > <Mr. Carlen strikes head with palm, to try to wake up from the bad dream.> > > Nope this is reality. Bummer. > > Aha! Project Navigator couldn't open my source because it didn't have > the same name that I created it with. I created it as "cross32-52" > which Project Navigator accepted just fine. But ECS wouldn't save the > file with this name, even though it opened it the first time. So I > saved it as something else, which of course broke Project Navigator. > Well that's certainly my fault. I should have expected ECS to not save > filenames with '-' characters. > > 6. After closing everything an reopening, I can select and move things > in ECS again. Oh joy! > > 7. I wanted to start a new project to develop a modified version of a > previous design done from scratch in 5.2i. I copied the .sch and .ucf > files to the new project dir. I can edit the schematic, so I deleted > some stuff I didn't want in there. Then I can't open the .ucf file > because it has nets that aren't in the schematic. I don't know why in > the original project, when I would add or remove nets from the > schematic, the user constraints file was automatically updated to > reflect the nets in the schematic. This doesn't work now, but perhaps > it's because there is some file missing. > > So I will remove the .ucf source and add a new one which I'll set up > from scratch. I click "remove" and then I add a new source, a user > constraints with the same name as the one that isn't working. Project > NAvigator prompts me if I want to overwrite the old file. I click "Ok" > and expect that when I open the new .ucf file, it will be a reflection > of the nets in my schematic. > > No such luck, the broken .ucf was not everwritten, so it still complains > of errors of missing nets. > > Well that's all before lunch time. Let's see what happens this afternoon... > > I guess if there's a point to all this, I should look around on Xilinx's > web site some more and find out where to report bugs. But I have > reached a point with software in general where I am tired of doing this. > That is because, I often wind up spending hours reporting the bugs in > the rigorous detail that is needed if there is to be any hope of anyone > actually fixing them. Unless of course, the software had been > rigorously tested in the first place. > > -- > _______________________________________________________________________ > Christopher R. Carlen > Principal Laser/Optical Technologist > Sandia National Laboratories CA USA > crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57213
Thanks for your replies. I've looked at the document '5V Tolerant I/Os' on the XILINX website. Using the 100ohm resistor would be the easiest to implement, but would it allow bidirectional communications? I've looked on the XILINX website and it "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message news:bdbtk5$a86$1@newsg4.svr.pol.co.uk... > Hi, > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are > 5V. Does anyone know a simple method to get around the voltage problem? I > don't suppose the Spartan2E could tollerate a 5V input? > > I found a company called BurchEd which sells an IDE interface to a Spartan2E > evaluation board. Looking at the picture of the IDE interface it has no > logic between the hard drive and the Spartan2E. How do they do it? > > Thanks for any help, > >Article: 57214
Hamish, You need to insert a latch into the path when you jump from the falling edge clock domain to the rising edge. FF(falling) -> Latch -> Q(rising or 175Mhz) A transparent high latch will give you 1.5 (350Mhz clock) period for the setup of the falling edge data into the a rising edge (or 175Mhz) flop. Verses the 0.5 clock period your struggling with. hamish@cloud.net.au wrote: > Hi all, > > As part of a design I need to transfer data which is arriving on both > edges of a 350 MHz clock to a 175 MHz clock. The 175 MHz clock comes > from the divided output of the same DCM as the 350, but there could be > clock skew. Data is arriving on every edge of the 350 and all of it > needs to be transferred. > > I'm using a Virtex-II -5. It isn't possible to transfer data between > opposite edges of the 350 MHz clock (according to TRCE the chip simply > won't run that fast - FF to FF needs to be about 1.35 ns and the best > I've seen is about 1.38, which is still pretty impressive!). > > Any suggestions? All the designs I could find in app notes used x1 and > x4 clocks, or could transfer data between edges of the same clock > because the clock frequency was sufficiently low. > > The positive 350 to 175 case is solvable but I can't see an obvious > solution to the negative 350 to 175 case, because the negative edge of 350 > isn't aligned to anything in the 175. > > Thanks, > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57215
Not putting down Xilinx software particularly. Other than not generating instantiation templates from Verilog2001-style port declarations I haven't had many issues --knock on wood. However, it has been my opinion for several years now that the state of EDA/Electronics CAD sofware is absolutely deplorable. I've spent thousands upon thousands of dollars on EDA tools that have bugs and ideosyncracies that would make the software a business failure in any other market ... yet engineers seem to put up with it ... and EDA companies don't seem to give a hoot about getting these things fixed. If you are in the sub-$10K US range they've got you by the gonads because the next strata is up well above $30K and past $100K. So, they almost don't have to worry because the playing field is so limited. I absolutely despise the EDA tool I'm using, but after having put nearly $10k into it, what are you going to do, go spend another $10K? It's high time for some guy in a garage to get excited about this and create something for engineering, by engineers that puts bad software in the proper context. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57216
Unfortunately, the board is already designed and I cant add another chip. What if I were to modify the data out such that its similar to NTSC and then pass it the encoder core. Instead of VGA, I could output 1 field at a time 30hz (still at 640x480). > I doubt that core will help you. > > It doesn't buffer VGA lines then read them out in interlaced order and at > half speed, which is what you'd need to squash VGA into NTSC or PAL. > > It only converts the colour signals from RGB to CVBS. > > And even that isn't worth using 50K gates when you can by ready-made chips > to do the same job cheaply. > (AD722, AD724, AD725, CXA1645P, CXA2075M, TDA8501). RS Components sell only > the Sony CXA1645P for £6.13+VAT.Article: 57217
Chris, What version are you running? It sounds like you may be using an older version and possibly have some misconceptions about how the tools work together. Steve Chris Carlen wrote: > Hi: > > Here's a chronicle of today's headaches. > > 1. ECS schematic editor can't deal with filenames that contain > anything except 0-9 a-z A-Z . > > 2. I selected a large block of schematic, and when I tried to move > it, ECS said "Internal Error: Delete Branch" > > 3. I guess nobody uses schematic entry because the editor is simply > impossible to use. It is an absolute disaster. I try to select a > group of objects to move, and it simply won't let me select them. > They don't highlight. I try to select everything I have drawn to move > it, and I get error mentioned in #2 above. The autorouting is > useless. Get rid of it. Hint: humans are smarter than computers. > Just let me draw my own wires. > > 4. Oh good grief, I moved some things, and then I simply cannot > select anything anymore. > > You see folks, when you make software this bad, even if it is free, > rather than making me want to pay for the "good" software, it makes me > think you simply can't write good software. What evidence do I have > that if I pay for your non-free tools, that they will be any better? > None. On the contrary, I have volumous evidence that I will simply be > paying for the exact same thing, only I will not only be frustrated, > but poorer. The end result is the same. I can't use your silicon. > > So perhaps I have made a big mistake. Perhaps I should have gone with > Altera. I just don't know now. > > Or perhaps analog design would be a way to avoid all this crap > altogether. I don't seem to have much trouble with SPICE simulators. > Heck even Linear Technology's LTSpice *FREE* simulator is very useable. > > Argh! > > > 5. I closed the schematic editor hoping that if I re-opened my file > it might reset som eof its internal data structures, and start working > again. Now I try to reopen my schematic source from Project > Navigator, and nothing happens. It simply sits there when I click > "open". > > <Mr. Carlen strikes head with palm, to try to wake up from the bad > dream.> > > Nope this is reality. Bummer. > > Aha! Project Navigator couldn't open my source because it didn't have > the same name that I created it with. I created it as "cross32-52" > which Project Navigator accepted just fine. But ECS wouldn't save the > file with this name, even though it opened it the first time. So I > saved it as something else, which of course broke Project Navigator. > Well that's certainly my fault. I should have expected ECS to not > save filenames with '-' characters. > > 6. After closing everything an reopening, I can select and move > things in ECS again. Oh joy! > > 7. I wanted to start a new project to develop a modified version of a > previous design done from scratch in 5.2i. I copied the .sch and .ucf > files to the new project dir. I can edit the schematic, so I deleted > some stuff I didn't want in there. Then I can't open the .ucf file > because it has nets that aren't in the schematic. I don't know why in > the original project, when I would add or remove nets from the > schematic, the user constraints file was automatically updated to > reflect the nets in the schematic. This doesn't work now, but perhaps > it's because there is some file missing. > > So I will remove the .ucf source and add a new one which I'll set up > from scratch. I click "remove" and then I add a new source, a user > constraints with the same name as the one that isn't working. Project > NAvigator prompts me if I want to overwrite the old file. I click > "Ok" and expect that when I open the new .ucf file, it will be a > reflection of the nets in my schematic. > > No such luck, the broken .ucf was not everwritten, so it still > complains of errors of missing nets. > > > Well that's all before lunch time. Let's see what happens this > afternoon... > > > I guess if there's a point to all this, I should look around on > Xilinx's web site some more and find out where to report bugs. But I > have reached a point with software in general where I am tired of > doing this. That is because, I often wind up spending hours reporting > the bugs in the rigorous detail that is needed if there is to be any > hope of anyone actually fixing them. Unless of course, the software > had been rigorously tested in the first place. > > >Article: 57218
Hi, I wonder how it is possible to implement a multirate system in an fpga. Let's say I want to upsample audio data at 44.1khz to 48khz. I guess I first need an interpolation filter (L) and then a Decimation filter (M) so that: 44.1*L/M = 48kHz. First I don't really know how to find L and M but it would be easy to write a small software that finds the best fraction using not too big integers. However, I really don't understand how the data could run at 48khz at the output of the system. Do you need multiple clocks? Thanks DavidArticle: 57219
James Horn wrote: > > Sorry to refer to such an ancient device - but can anyone point me to > either a reverse compiler for the GAL16V8 or the definition of its fuse > map bits to be able to derive the logic function from same? There's nothing wrong with a 16V8 - we still use them in new designs :) > > Our company bought another years ago and the products from them that we're > making often have no documentation or source code. In getting ISO > certified we have to reengineer what's going on. We have all the rights > to the designs - we just don't know what they are(!!). Any pointers will > be most appreciated. Look for a pgm called JED2EQN, which can take a JED file, for simple devices, and create a boolean eqn for the same. If you want to fully re-create the device, it will be a good idea to also create Test vectors - these allow functional test in device programmers. One detial to watch for, in doing EQN -> JED again, is the allocate of the OR terms ( 8 wide in a 16V8) can legally occur in any order, so the fuse maps will differ. - ie you can have identical logic but different (shuffled) JED content. -jgArticle: 57220
stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0306241507.16472c57@posting.google.com>...
> Hello,
>
> I have constructed a 256 pt complex fft. My scaling is causing
> problems as the outputs from each stage are divided by 4 to avoid
~~~~
2 is enough
> overflow. The input data and the twiddle factor coeffs are 16 bits
> wide (Q15). My problem is that when the data arrives at the last two
> butterfly stages of the FFT, it is non-existant, due to all the
> scaling beforehand. All inputs to these stages are zero. Thus I get
> nothing at the output.
>
> How can I work around this?
>
> Many thanks
>
> Bob
Article: 57221Amen brother! The "pay" tools are essentially the same, and work just as deplorably. I have a copy of ISE 5.2, and it uses the same sorry excuse for a schematic editor. I invented the "hexplitive", which was swearing in base 16, when working with X schematic tools. Xilinx clearly has no interest in catering to the schematic entry crowd and their tools show it. Their schematic tools are about as good as something like OrCad was -- OrCad from 15 years ago running under DOS that is. I have worked exclusively with Altera tools since the late '80s because their support for schematics was SO MUCH better. There is simply no comparison. I think that for most FPGA designs, X or A parts would work just fine. However, the crap you have to go through to use X tools was never worth it. Still isn't in my book. Their tools can take a one day design and turn it into a week of rebooting and hair pulling. I also can't buy into the HDL argument. The reason is simple. If you were a software developer and you needed your code to be as small as possible and run as fast as possible, what language would you use? Well, every software developer I've ever met answers the same -- native assembly language for the processor in question. No compiled code will be more efficient because of the layers of abstraction that higher level languages impose. The embedded developers I've worked with always got a good chuckle out of their C language counterparts sucking up 100's of kilobytes of memory compared to the few K that their assembly code needed. HDL is the same. You abstract designs (so that non-designers can pretend to be designers I suppose) and pay a penalty by having circuit bloat. If you want the smallest design possible, and want it to run as fast as possible, you need to use the design equivalent of assembly coding -- i.e. schematics. A picture is worth a thousand words, so you can make a picture or type a thousand words. Which one will be easier for someone else to understand, hmm? I recently talked to an FAE for an FPGA vendor. He said that fully 80% of the designs he has seen are done in schematics. You can even read about graphical versions of HDL coming out. Sounds like schematics to me. Except that you add a layer of obfuscation in there that will make for a more bloated design. Why bother? An ironic thing to notice is that if you open many of the X design examples included with the tools, you'll see that they are schematic based. With a schematic it is sooooo simple to identify each and every flop and see what it is doing in a simulation. Something isn't working in HDL? Good luck. Oh yeah, and with schematics, you never have to do all that modeling nonsense. While most "designers" are modeling what their circuit is supposed to do, I've already got it done, simulated, verified on the bench, off my plate and onto the next thing. I was taught the power of schematics and their companion, the timing diagram, when I was a wee engineer pup. My first boss would sit me down and go over the schematics with me, asking me to justify each and every component on the page. If there wasn't a good reason for it, it was gone. Amongst the many invaluable lessons he taught me was that every component in the circuit should have a reason. Try doing that with an HDL abstraction. Most "designers" haven't a clue how that hunk of code they wrote got implemented in actual gates. Scott Adams would probably call them "Duhsigners". <getting off soapbox now> So, I'm with you 100%. Schematics rule. Xilinx has no reason whatsoever to support schematics, as the bloated designs that HDLs produce force folks into buying larger, faster speed grade parts that are naturally more costly. Works for them. You can always download the free Altera tools and play with their stuff. Fully integrated schematic capture, compiler and simulator. Very nice. Not perfect or bug free, but then no tool is. It is, however, VASTLY superior to the X garbage schematic tools. When I need to design something in an X part, I do it first in the A tools and use their native simulater. Then I re-enter it in X. Doing the drawings twice is STILL faster than doing the design from scratch in X. Try it. I tend to always push my clients to use A parts simply because the tools are so superior. Design times are radically reduced, and that saves them tangible money. If they insist on X parts, I revert to the paragraph above. Don't buy into the HDL propaganda. Schematics will never do you wrong. "Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message news:bdcqge$jo5$1@sass2141.sandia.gov... > Hi: > > Here's a chronicle of today's headaches. > > 1. ECS schematic editor can't deal with filenames that contain anything > except 0-9 a-z A-Z . > > 2. I selected a large block of schematic, and when I tried to move it, > ECS said "Internal Error: Delete Branch" > > 3. I guess nobody uses schematic entry because the editor is simply > impossible to use. It is an absolute disaster. I try to select a group > of objects to move, and it simply won't let me select them. They don't > highlight. I try to select everything I have drawn to move it, and I > get error mentioned in #2 above. The autorouting is useless. Get rid > of it. Hint: humans are smarter than computers. Just let me draw my > own wires. > > 4. Oh good grief, I moved some things, and then I simply cannot select > anything anymore. > > You see folks, when you make software this bad, even if it is free, > rather than making me want to pay for the "good" software, it makes me > think you simply can't write good software. What evidence do I have > that if I pay for your non-free tools, that they will be any better? > None. On the contrary, I have volumous evidence that I will simply be > paying for the exact same thing, only I will not only be frustrated, but > poorer. The end result is the same. I can't use your silicon. > > So perhaps I have made a big mistake. Perhaps I should have gone with > Altera. I just don't know now. > > Or perhaps analog design would be a way to avoid all this crap > altogether. I don't seem to have much trouble with SPICE simulators. > Heck even Linear Technology's LTSpice *FREE* simulator is very useable. > > Argh! > > > 5. I closed the schematic editor hoping that if I re-opened my file it > might reset som eof its internal data structures, and start working > again. Now I try to reopen my schematic source from Project Navigator, > and nothing happens. It simply sits there when I click "open". > > <Mr. Carlen strikes head with palm, to try to wake up from the bad dream.> > > Nope this is reality. Bummer. > > Aha! Project Navigator couldn't open my source because it didn't have > the same name that I created it with. I created it as "cross32-52" > which Project Navigator accepted just fine. But ECS wouldn't save the > file with this name, even though it opened it the first time. So I > saved it as something else, which of course broke Project Navigator. > Well that's certainly my fault. I should have expected ECS to not save > filenames with '-' characters. > > 6. After closing everything an reopening, I can select and move things > in ECS again. Oh joy! > > 7. I wanted to start a new project to develop a modified version of a > previous design done from scratch in 5.2i. I copied the .sch and .ucf > files to the new project dir. I can edit the schematic, so I deleted > some stuff I didn't want in there. Then I can't open the .ucf file > because it has nets that aren't in the schematic. I don't know why in > the original project, when I would add or remove nets from the > schematic, the user constraints file was automatically updated to > reflect the nets in the schematic. This doesn't work now, but perhaps > it's because there is some file missing. > > So I will remove the .ucf source and add a new one which I'll set up > from scratch. I click "remove" and then I add a new source, a user > constraints with the same name as the one that isn't working. Project > NAvigator prompts me if I want to overwrite the old file. I click "Ok" > and expect that when I open the new .ucf file, it will be a reflection > of the nets in my schematic. > > No such luck, the broken .ucf was not everwritten, so it still complains > of errors of missing nets. > > > Well that's all before lunch time. Let's see what happens this afternoon... > > > I guess if there's a point to all this, I should look around on Xilinx's > web site some more and find out where to report bugs. But I have > reached a point with software in general where I am tired of doing this. > That is because, I often wind up spending hours reporting the bugs in > the rigorous detail that is needed if there is to be any hope of anyone > actually fixing them. Unless of course, the software had been > rigorously tested in the first place. > > > > -- > _______________________________________________________________________ > Christopher R. Carlen > Principal Laser/Optical Technologist > Sandia National Laboratories CA USA > crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply. >Article: 57222
While the ATA spec says 5v for backwards compatibility, I
don't believe there are ANY ATA-6 drives that drive beyond
LVTTL levels. You should be fine as long as you don't put
an early legacy drive on there. The spec also calls for
series termination resistors which IIRC are 66 ohm or 100
ohm, which is enough to limit the current for 5v inputs to
the FPGA.
marlboro wrote:
> What IDE HD are you using, what ATA version does it
> compliance?
>
> The T13's ATAPI-6 spec (T13/1410D rev 3b) already
> recommend some series termination at both device and host
> for UDMA.
>
> If your host and your device follow T13's spec, it seems
> to be all right, all signals have about 100 ohm series
> termination, except data lines DD[15:0] have 66 ohm,in my
> opinion it's probbably okay.
>
> I also attemp to build such thing (ATAPI-6) in a
> Spartan2E/VirtexE, let me know if this work for you?
>
> regard,
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 57223
you do at the analog interfaces of the system. For the digital parts though,
you can get away with using one clock with clock enables. Generally what I try
to do in these type situations is to run with 2 clocks, one for input, one for
output, and then do the intermediate processing using the faster of the two, or
a third clock. You may have to do some tricks to handle extra or short samples
if the ratio of the input and output clocks is not solidly locked (eg. derived
from different sources)
David wrote:
> Hi,
> I wonder how it is possible to implement a multirate system in an fpga.
> Let's say I want to upsample audio data at 44.1khz to 48khz. I guess I
> first need an interpolation filter (L) and then a Decimation filter (M) so
> that: 44.1*L/M = 48kHz.
> First I don't really know how to find L and M but it would be easy to write
> a small software that finds the best fraction using not too big integers.
> However, I really don't understand how the data could run at 48khz at the
> output of the system. Do you need multiple clocks?
> Thanks
> David
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 57224can't agree more. I come from a software development background, so maybe I've been a bit more spoiled by the tools, but the xilinx suite is totally ridiculous; this is a totally retarded design (from a software perspective). I can't imagine paying for that; even if the pay version is ten times better, it wouldn't be worth $50. All tools have a lame interface, they are buggy, they have a disfunctional way of communicating and a totally sparse and useless documentation. the vendor question is still up in the air for us, and I think that just for that reason I am going to go against xilinx; no matter how good the chips can be, user support and tools are key; they have neither. On Wed, 25 Jun 2003 11:44:41 -0700, Chris Carlen <crcarle@BOGUS.sandia.gov> wrote: > Hi: > > Here's a chronicle of today's headaches. > > 1. ECS schematic editor can't deal with filenames that contain anything > except 0-9 a-z A-Z . > > 2. I selected a large block of schematic, and when I tried to move it, > ECS said "Internal Error: Delete Branch" > > 3. I guess nobody uses schematic entry because the editor is simply > impossible to use. It is an absolute disaster. I try to select a group > of objects to move, and it simply won't let me select them. They don't > highlight. I try to select everything I have drawn to move it, and I get > error mentioned in #2 above. The autorouting is useless. Get rid of it. > Hint: humans are smarter than computers. Just let me draw my own wires. > > 4. Oh good grief, I moved some things, and then I simply cannot select > anything anymore. > > You see folks, when you make software this bad, even if it is free, > rather than making me want to pay for the "good" software, it makes me > think you simply can't write good software. What evidence do I have that > if I pay for your non-free tools, that they will be any better? None. On > the contrary, I have volumous evidence that I will simply be paying for > the exact same thing, only I will not only be frustrated, but poorer. > The end result is the same. I can't use your silicon. > > So perhaps I have made a big mistake. Perhaps I should have gone with > Altera. I just don't know now. > > Or perhaps analog design would be a way to avoid all this crap > altogether. I don't seem to have much trouble with SPICE simulators. > Heck even Linear Technology's LTSpice *FREE* simulator is very useable. > > Argh! > > > 5. I closed the schematic editor hoping that if I re-opened my file it > might reset som eof its internal data structures, and start working > again. Now I try to reopen my schematic source from Project Navigator, > and nothing happens. It simply sits there when I click "open". > > <Mr. Carlen strikes head with palm, to try to wake up from the bad > dream.> > > Nope this is reality. Bummer. > > Aha! Project Navigator couldn't open my source because it didn't have > the same name that I created it with. I created it as "cross32-52" which > Project Navigator accepted just fine. But ECS wouldn't save the file > with this name, even though it opened it the first time. So I saved it > as something else, which of course broke Project Navigator. Well that's > certainly my fault. I should have expected ECS to not save filenames > with '-' characters. > > 6. After closing everything an reopening, I can select and move things > in ECS again. Oh joy! > > 7. I wanted to start a new project to develop a modified version of a > previous design done from scratch in 5.2i. I copied the .sch and .ucf > files to the new project dir. I can edit the schematic, so I deleted > some stuff I didn't want in there. Then I can't open the .ucf file > because it has nets that aren't in the schematic. I don't know why in > the original project, when I would add or remove nets from the schematic, > the user constraints file was automatically updated to reflect the nets > in the schematic. This doesn't work now, but perhaps it's because there > is some file missing. > > So I will remove the .ucf source and add a new one which I'll set up from > scratch. I click "remove" and then I add a new source, a user > constraints with the same name as the one that isn't working. Project > NAvigator prompts me if I want to overwrite the old file. I click "Ok" > and expect that when I open the new .ucf file, it will be a reflection of > the nets in my schematic. > > No such luck, the broken .ucf was not everwritten, so it still complains > of errors of missing nets. > > > Well that's all before lunch time. Let's see what happens this > afternoon... > > > I guess if there's a point to all this, I should look around on Xilinx's > web site some more and find out where to report bugs. But I have reached > a point with software in general where I am tired of doing this. That is > because, I often wind up spending hours reporting the bugs in the > rigorous detail that is needed if there is to be any hope of anyone > actually fixing them. Unless of course, the software had been rigorously > tested in the first place. > > >
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