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Hi! I have just uppgraded to Xilinx EDK 3,2 and now i cant choose to synthesise with Synplify in "project options -> hierarchy and flow. It worked with EDK 3,1 but not in EDK 3,2. Do you have any sugestions what seems to be the problem. Please advice. Martin Ericson Halmstad Univercity SwedenArticle: 62051
Panic wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote [......] > > Thanks a lot! > > > You can analyze the differences on paper all day, and you still won't > > know how your design will do in either family of parts. The best thing > > to do is to write your HDL to be generic and see how it fits. > > Sure, and normally I would. But I've studied a paper written by > François-Xavier Standaert, where he and some other reasearchers optimizes a > implementation of the Rijndael algorithm to better match the Xilinx slice. > And the results are impressive! > > So I wanted to try and figure out how I could transfer such a design > strategy to the Altera-FPGA I am working on (EPXA1F484C1). But in order to > do that, I need to understand how I can make the different stages fit in > Alteras slice-equivalent :p > > I will try and grab a detailed data sheet from Alteras website, allthough I > have downloaded all the documentation marked for EPXA1, and haven't seen > anything like it in there. But I suppose that if I search for LC or LAB > layout or something similar, I will eventually find it :-) I understand. The data sheet is just a start in learning about optimizing a design. The routing is also important which is not described. What aspect are you trying to optimize? Speed, size? What Xilinx CLB features did they optimize for? There are only a few significant differences in the two brands, but they can be *very* significant depending on the design. Just ask Ray Andraka. BTW, do you have the part number scrambed? Alteras part numbers are mostly EPxy where x is a number and letter and denotes the product line line while y is a number indicating the size. Example, EP2A40 is an APEX II at 3 million gates. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62052
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote in message news:<O6Hcb.347818$lK4.11111238@twister1.libero.it>... > "Valeria Dal Monte" <aaa@bbb.it> ha scritto nel messaggio > news:9qkbb.335067$Ny5.10649409@twister2.libero.it... > > > Some days ago Xilinx did workshops in many european > > states. > > Why Italy was excluded? > > Well, if you think that some multinationals put Italy into their SEMEA > division (South Europe, Middle Europe and Africa), you can guess. We are > considered just like Bulgaria or Libia and, with all the respect for > these countries, I think we could deserve a little more. Lorenzo, I think it is not a matter of Libia or Bulgaria or other countries: if the FPGA market in Italy can't swallow enough chips, then Altera/Xilinx/XYZ will simply neglect this market. I can understand their position. Luca PonteArticle: 62053
Stephane, I hope I understand your question correctly. As of version 2.7, SOPC Builder allows the synthesis to be performed by Quartus (called native synthesis). It is settable on the "System Generation" tab. I am running ver 3.0, and there is no option at all anymore, so it ALWAYS gets synthesized by Quartus (SOPC only produces VHDL or Verilog). -- Pete > Thanks Mike, > That's we are already doing. The problem is that I want to synthesize the > sopc project before and just perform the P&R during the course to speed up the whole > process. So I have to synthesize the sopc project with leonardo or > Quartus. In this later case, is it possible to just perform a synthesis > with Quartus ? > What can I do ? > thanks a lot. > > Stéphane >Article: 62054
rickman wrote: > > Panic wrote: > > > > "rickman" <spamgoeshere4@yahoo.com> wrote [......] > > > > Thanks a lot! > > > > > You can analyze the differences on paper all day, and you still won't > > > know how your design will do in either family of parts. The best thing > > > to do is to write your HDL to be generic and see how it fits. > > > > Sure, and normally I would. But I've studied a paper written by > > François-Xavier Standaert, where he and some other reasearchers optimizes a > > implementation of the Rijndael algorithm to better match the Xilinx slice. > > And the results are impressive! > > > > So I wanted to try and figure out how I could transfer such a design > > strategy to the Altera-FPGA I am working on (EPXA1F484C1). But in order to > > do that, I need to understand how I can make the different stages fit in > > Alteras slice-equivalent :p > > > > I will try and grab a detailed data sheet from Alteras website, allthough I > > have downloaded all the documentation marked for EPXA1, and haven't seen > > anything like it in there. But I suppose that if I search for LC or LAB > > layout or something similar, I will eventually find it :-) > > I understand. The data sheet is just a start in learning about > optimizing a design. The routing is also important which is not > described. What aspect are you trying to optimize? Speed, size? What > Xilinx CLB features did they optimize for? There are only a few > significant differences in the two brands, but they can be *very* > significant depending on the design. Just ask Ray Andraka. > > BTW, do you have the part number scrambed? Alteras part numbers are > mostly EPxy where x is a number and letter and denotes the product line > line while y is a number indicating the size. Example, EP2A40 is an > APEX II at 3 million gates. Opps, nevermind to this last part. I searched on the Altera site and found that this is an Excalabur part with built in ARM CPU. I did not have this one on my hard drive. The architecture of the LABs is the same as the APEX 20KE. Download that data sheet and you should find what you are looking for. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62055
"rickman" <spamgoeshere4@yahoo.com> wrote > Opps, nevermind to this last part. I searched on the Altera site and > found that this is an Excalabur part with built in ARM CPU. I did not > have this one on my hard drive. The architecture of the LABs is the > same as the APEX 20KE. Download that data sheet and you should find > what you are looking for. I'll do that. Thanks a lot :-)Article: 62056
Naveed wrote: > My experience with Altera's mySupport is pretty bad. Out of 5 > questions I asked them none was replied to my satisfication. When I > followed up, they asked for my design files, when it was completely > unnecessary. I wasn't really asking for any design problems, but > rather capabilities and features of the Cyclone. In-house tech support groups for any company are optimized to answer FAQs and provide work-arounds for reproducable bugs. It's the sales and field apps guys that love to talk capabilities and features. -- Mike TreselerArticle: 62057
Nicholas C. Weaver wrote:
> Tell me about it! Worse, Darpa is NOT funding security work, at least
> unclassified security work.
I expect that banks, brokers and amazon.com are.
-- Mike Treseler
Article: 62058Martin Ericson wrote: >Hi! >I have just uppgraded to Xilinx EDK 3,2 and now i cant choose to >synthesise with Synplify in "project options -> hierarchy and flow. It >worked with EDK 3,1 but not in EDK 3,2. Do you have any sugestions >what seems to be the problem. > This was a change that we made to reduce confusion. Since EDK must use XST to synthesize the Xilinx processor peripherals, people were getting confused when they saw XST being run after selecting Synplify. You can still select Synplify in the Project Navigator and use it to synthesize everything except the Xilinx IP. Steve > >Please advice. >Martin Ericson >Halmstad Univercity >Sweden > >Article: 62059
Chad Bearden <chadb@beardendesigns.com> wrote in message news:906428f5.0310160842.420b70b8@posting.google.com... > Is it possible to create a 3rd party pci dma engine? > I would like to dma to/from host memory to a pci device that supports > burst read/writes but has no dma hardware. > This mythical circuit would be saying "Hey! Mr Host please send a > block of data to that pci device over there." or "Hey, Mr Host grab a > block of data from that pci device and put it in your ram." > chad. You would probably have to design hardware with master functionality to do this. This could then grab the data in a burst from the source (as long as it's on the same local bus, I think there might be implications with crossing bridges) then burst write it to the destination. Dependant on the amount of intormation to be transferred this double action would probably be faster than the host reading the info 4 bytes at a time. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 62060
Metastability is unavoidable. Whether it hurts you depends on the clock and data frequencies and also on the technology used. I will not guarantee that SRL16s recover as fast from metastability as the "normal" flip-flops that I documented, since SRLs are implemented in a different circuit design. (Different might mean better or worse). Peter Alfke ================= David R Brooks wrote: > > If I create a two-FF chain (with common clock), XST will likely pull > those two FFs into a SRL16. Is it permissible to use two bits of a > SRL16 as a synchroniser in this way? (It surely must be the > shortest-possible path between two FFs). > > Peter Alfke <peter@xilinx.com> wrote: > > :You should always be concerned about metastability, whenever > :asynchronous signals are being synchronized. Let me add some numbers to > :Phil Freidin's excellent comments: > : > :Metastability creates unpredictable additional settling delays (even > :oscillations can be considered delays to valid out). The probability of > :a specific max delay depends on the clock rate, the data rate, and the > :IC technology. > : > [snip]Article: 62061
rickman wrote: > You can analyze the differences on paper all day, and you still won't > know how your design will do in either family of parts. The best thing > to do is to write your HDL to be generic and see how it fits. Well said. Working generic synth code cuts through technobabble like a knife. It tests the tools and the device from front to back and provides utilization and fmax benchmarks that you just can't get any other way. That said, I have noticed that Altera's ep1s series is much more Xilinx-like than ep20k. -- Mike TreselerArticle: 62062
Vazquez wrote:
> process
> begin
> t_reset <= '1', '0' after 100 ns;
> wait;
> end process;
>
> I thought that is was a legal wait-statement when writing a testbench for functional
> simulation.
The problem is that the wait is unconditional.
Even if the code were legal, you would never
get past the first loop of the process at 0 nS.
-- Mike Treseler
Article: 62063Hi all, I have updated my Xilinx software to 6.1 a few days ago and it looks like I am in for a ride; the design that worked well under the previous version (5.2 with all service packs) wouldn't even go through PAR anymore!! I managed to work around this by setting thr effort level to maximum for the place&route but when I program the FPGA (XC2V4000-5) with this new bitstream my board doesn't work anymore!!? Anybody having similar problems? I guess I shoild have known better: the service pack for this latest software creation arrived before the CD with the software did! In my humble oppinion the best software from Xilinx was 4.2, it's all downhill from there; it seems that a nice GUI is valued more than a decent and consistent PAR algorithm these days. --- jakabArticle: 62064
> BTW, do you have the part number scrambed? Alteras part numbers are > mostly EPxy where x is a number and letter and denotes the product line > line while y is a number indicating the size. Example, EP2A40 is an > APEX II at 3 million gates. > Rick, Altera's part numbering changed after Apex to give a rough estimate of LE count (LE count * 1000 actually), rather than an ASIC-like gate count (i.e., 20K200E = Apex 20KE family, ~200K gates). That 20K200E apex chip had ~8k LEs... a similar-sized (well, a little larger) device in terms of LE count is the Stratix 1S10 -- 1S meaning the family, (Stratix 1st edition), and 10 meaning ~10K LEs in the device. So, a 1S40 has about 40,000 LEs, and a Cyclone 1C6 has about 6,000 LEs, and so forth. The device Mr(s). Panic refers to is the Excalibur XA1, where XA is the family name "for Excalibur Arm". The family has EPXA1, XA4, and XA10 devices, where the number is related to gate count (gate count / 100K). The XA1 is sort of like the 20K100E, but with the ARM CPU aboard. The Excalibur family is based on the Apex 20KE FPGA fabric, and thus the gate count terminology was still used. Anyways, even though I work here I am very happy we number the parts now with respect to the number of logic elements inside. Nice and simple. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 62065
Yesterday, I clicked on a Google ad for a Xilinx FPGA dev board from these folks: http://www.charmedlabs.com/ It looks really interesting to me. Anyone try this product? It seems reasonably priced. PeteArticle: 62066
In article <bmp871$22k$1@news.storm.ca>,
"jakab tanko" <jtanko@ics-ltd.com> writes:
|> Anybody having similar problems?
Me too. A design for a 2S200 which needs to run at 130MHz (5.1 achieved ~133MHz
without floorplaning) is slowed down with 6.1 to about 110MHz. "High effort" etc.
does not help at all. Looking at the timinganalyzer output, it seems that MAP
ignores the first carry chain block and uses regular logic and routing instead,
thus stealing about 2ns :-(
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 62067Is it possible to define a macro through the GUI of ISE or by any command line means? I mean, just like we give a +define+MACRO_NAME along with a verilog compilation commandline in Modelsim or in NC verilog. How do I do it? As, otherwise, it becomes quite messy affair of commenting and uncommenting lines containing `define in the source code. Xilinx Answer records don't seem to have anything on this. Regrds SwarnaArticle: 62068
Jesse Kempa wrote: > > > BTW, do you have the part number scrambed? Alteras part numbers are > > mostly EPxy where x is a number and letter and denotes the product line > > line while y is a number indicating the size. Example, EP2A40 is an > > APEX II at 3 million gates. > > > > Rick, > > Altera's part numbering changed after Apex to give a rough estimate of > LE count (LE count * 1000 actually), rather than an ASIC-like gate > count (i.e., 20K200E = Apex 20KE family, ~200K gates). That 20K200E > apex chip had ~8k LEs... a similar-sized (well, a little larger) > device in terms of LE count is the Stratix 1S10 -- 1S meaning the > family, (Stratix 1st edition), and 10 meaning ~10K LEs in the device. > So, a 1S40 has about 40,000 LEs, and a Cyclone 1C6 has about 6,000 > LEs, and so forth. > > The device Mr(s). Panic refers to is the Excalibur XA1, where XA is > the family name "for Excalibur Arm". The family has EPXA1, XA4, and > XA10 devices, where the number is related to gate count (gate count / > 100K). The XA1 is sort of like the 20K100E, but with the ARM CPU > aboard. The Excalibur family is based on the Apex 20KE FPGA fabric, > and thus the gate count terminology was still used. > > Anyways, even though I work here I am very happy we number the parts > now with respect to the number of logic elements inside. Nice and > simple. > > Jesse Kempa > Altera Corp. > jkempa at altera dot com As long as I have the attention of someone from Altera, let me make an observation about the Excalibur parts. This is a part that I could use on my current board since I have an ARM MCU along with an FPGA in direct connection using the same power supplies. Having only a single package would save me board space (in theory) and being on a single chip should save me power and cost (again in theory). I am currently looking at power consumption of about 100 to 300 mW (won't know for sure until it is built) and the combination will cost me about $30. Your smallest Excalibur, as you say, is the EPXA1. It comes in a 484 pin package (23 x 23 mm), costs over $100 and will use Watts, not mWatts. Unfortunatly this is way too much chip in every respect and since it is not 5 volt tolerant, I would have to add buffering taking up any board space I might save. Is there any plans for a lower end combination of 50 MHz ARM 7 perhaps with FPGA in a reasonably sized package with a lower power curve? Even if 5 volt tolerance is not an option, such a part with a reasonable price tag could save lots of space on a board. To be honest, I just can't see paying triple the price for a combined part especially when it still requires an external Flash which is included with an ARM MCU. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62070
Followup to: <Uisib.4367$zw4.3042@nwrdny01.gnilink.net> By author: <sc01@hotmail.com> In newsgroup: comp.arch.fpga > > Hi, > I've almost finished the RTL for the design. > The question I have is how do I know how large my design is before selecting a FPGA? > If you already have the RTL, the easiest is to let the synthesis tools tell you ... both the Xilinx and Altera tools have teh option of "pick a device". If the resulting device is very full, you may want to pick one size larger just in case you need to change your design in the future. This applies to some applications, but not to all. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 62071
You can check out my site http://www.c-nit.net/ Sumit "DGW" <chippa11@hotmail.com> wrote in message news:<3f8cb95a$0$21654$afc38c87@news.optusnet.com.au>... > I am urgently in search of a simple project that will demonstrate on the old > Xilinx Spartan XCS10. Any intro to medium sized project that can perform > functions on the demo board Digilab XLA5 at > http://www.digilentinc.com/Catalog/digilab_xla.html with the LEDs and 7 SEG > displays being utilized would be desirable. Examples may include simple > timers, counters, traffic light controller, etc etc. I know this is a long > shot, but I am desperate!! The files would need to be able to run on Xilinx > Foundation 4.2i or equiv if possible. Schematic design entry would be > preferrable over VHDL but not essential. Apologies to the experts in this NG > and if I am looking in the wrong places can anyone suggest where else to > look/ask/beg? A negotiated fee can be arranged through Kasamba.com. Anyone > genuinely interested or that can help please email me direct. > > Kind Regards (and apologies for being of no help to anyone in a NG!!) > > DArticle: 62072
ram wrote: >Did you install the service packs >I had some similar problem where my earlier synthesised design gave me >error after re installation.I found that i didnt load the service >packs. > > The problem I had had absolutely nothing to do with service packs. It was entirely caused by either voltage levels or timing differences between different parallel port chips in the motherboards. I have found motherboards that work fine in these applications, and I will just hang on to them until they die. JonArticle: 62073
I am trying to construct a 6x6 signed multiplier using the Virtex II block multipliers. I know that the V-II multipliers are inherently a 2's complement signed multiplier. However, my question is - by how much should I sign-extend the inputs? Example: Input A - 6 bit Input B - 6 bit Output B- 12 bit Should I connect the remaining ports of the multiplier input (A(7:18)) to A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension of the inputs is done till the width of the output. Is this enough or should I do it till the physical width of the multiplier? Thanks AnilArticle: 62074
Its all in the options. Right Click "Post-PAR Static Timing" and choose your report options. For analyzing specific paths - launch the "Timing Analyzer". Its much better in 6.1! "Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0310122152.8de177d@posting.google.com... > Hi, > > I am using ISE5.1i...XST synthesis tool. > > At the end of synthesis, XST generates defualt timing report for 1 or > 2 paths. > > How can i generate a timing report after synthesis for more than 100 > paths? > > ie., as like .twr after Place and route. > > And How can i measure the time dealy between 2 specific points... > Points could be FF,mux or any logic > > Thanks in advance. > > Regards, > Muthu
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