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Peter Alfke <peter@xilinx.com> wrote in message news:<3F71C1CB.D1576A6@xilinx.com>... > rider wrote: > > > 2)I have a 20MHz clock in my design that is used in some flip flops in > > the design. Most of the circuit is combinational and with about 18 > > combinational clocks. > That is a scary statement. > Are you really using 18 clocks driven by combinatorial logic? > You must be either very inexperienced, very brave, or very smart. Or > perhaps all three. > Normal humans stay away from such design methodologies, and use > synchronous logic with a minimum of global clocks (preferrably only one). > That's better for your health, your sleep, and your sanity... > Peter Alfke Peter! Thanks for pointing out the issue. You are right about the synchronous clock issue. I know its not good to use asynchronous designs, but i have a different problem at hand. I am actually doing reverse engineering of a board made in probably 1980. It has more than 200 I/Os and over 180 TTL ICs. I have a rough schematic of it and no other info. So, I thought it wouldn't be practical to start tracing the boards functionality and make it SYNCHRONOUS ...and it may never be possible i feel...so i had to go with combinatorial clocks which the design is already using.. Now i know synchronous design has its advantages, but does that mean that asynchronous design will never work..in discrete ICs or in FPGA? Please comment.. RiderArticle: 60951
I just received some more complete benchmark info on Linux vs. Windows XP using ISE 6.1i. The average runtime on Linux is 18% faster than Windows. The best we saw is 43% faster. Also, one of our application engineers tried a customer project that uses a XC2V1000, via ISE 6.1i. His quote: > This was done on a quad Opteron 844 multiprocessor server, hosted by > 64-bit SuSE Linux Enterprise Server (SLES) 8. And it was wicked fast. > On this same system, I was also able to run four concurrent ISE 6.1i > environments, driving them all over SSH via X to my Linux laptop. Each > one had gigabytes and processor power to spare, I could literally work > four ISE jobs at one time. > > Thought you might enjoy this information -- ISE 6.1i is a great tool, > and it runs on 64-bit Linux! Note that this is not a configuration that we officially support, and of course he is running ISE 6.1i which is a 32 bit application. Steve Steve Lass wrote: > Jim Granville wrote: > >> Steve Lass wrote: >> >> >>> Our limited testing has show Linux to be about 10% faster than Windows >>> running PAR. Linux >>> also uses less memory. The average is about 6% less and a few really >>> big designs that run out >>> of memory on Windows XP run fine under Linux. >>> >>> Steve >>> >> >> >> Do they have the same ceiling ? >> > Yes, both Windows XP and Linux can address 3G. As far as I know, > Windows 2000 will > only address 2G. > >> ISTR comments on (some versions?) of windows only being able to >> access 2GB RAM, because MS decided the other 2GB was for them, not >> for you. ( and who would want > 2GB anyway.... :) >> >> Any tests of Linux/AMD 64 bit CPUs P&R ? >> > Not yet. > > Steve > >> >> -jg >> >> >Article: 60952
"T. Irmen" <tirmen@gmx.net> wrote in message news:<bkup03$5a7$1@nets3.rz.RWTH-Aachen.DE>... > Hi , > > my question is about using/modifiying ChipScope Pro: > > I have a direct access to the jtag pins through my own device driver. Now I > wanna use this pins with the chipscope pro software. I thought about adding > a filter driver ontop of the xilinx driver and redirect all access to my pci > card. > > But before I try this workaround, I wanna ask some guys who might have been > done such crazy things. crazy things are fun, but in your case it want help :( xilinx uses kernel driver that bypasses IO virtualization, so request from chipscope are executed to hardware directly (executing at x86 ring 0) you can not intercept that. choices are: 1 external hardware that wraps Xilinx Cable III to your hardware 2 internal PCI board that emulates a LPT device and Cable III and rewraps to you adapter 3 fake kernel driver that you use to replace xilinx driver, you need full disassembly and RE for that 4 fake communication DLL again full disassembly and RE needed. 5 intercept dll, it exposes xilinx DLL entry points and call xilinx dll (that you have renamed) part of the calls are re routed to your dll that then talks to your hardware 6 you install windows in BOCHS PC simulator, install chipscope in windows that runs in bochs, and you use customized BOCHS (rewrite and recompile!) to reroute the hardware access to your device. FUN! anttiArticle: 60953
rider wrote: > I/Os and over 180 TTL ICs. I have a rough schematic of it and no other > info. So, I thought it wouldn't be practical to start tracing the > boards functionality and make it SYNCHRONOUS ...and it may never be > possible i feel...so i had to go with combinatorial clocks which the > design is already using.. Make sure there are no reports of "flakiness" with the old design. But say we assume that the TTL designers got it right, and that all of the logic races were skewed in the right direction for reliable operation. Now you change from TTL to cmos/FPGA and a new set of races are on. I expect that the time you save by skipping a redesign will be more that used up by debugging logic races. > Now i know synchronous design has its advantages, but does that mean > that asynchronous design will never work..in discrete ICs or in FPGA? An asynchronous design can work, but it is *very* difficult to prove that that it will always work over time and environment. Even the simplest case of building a reliable d-flop primitive is non-trivial. It a simple task to prove reliablility on a synchronous design. -- Mike TreselerArticle: 60954
Jim Granville wrote: > Do they have the same ceiling ? Steve Lass <lass@xilinx.com> writes: > Yes, both Windows XP and Linux can address 3G. As far as I know, > Windows 2000 will > only address 2G. Running 64-bit Linux on an AMD64 processor (Opteron or Athlon 64) allows 32-bit Linux applications to access just under 4G. I haven't tried ISE 6.1i on an AMD64 yet, but I expect that it should be able to P&R larger designs than on 32-bit CPUs. None of my designs to date have needed more than 1.5G.Article: 60955
"Peter Alfke" <peter@xilinx.com> ha scritto nel messaggio news:3F6F1A16.EC328D4F@xilinx.com... > Lorenzo, you must be pretty smart if you can solve the > "worst nightmare > ever invented" in a mere ten minutes... :-) Touche`. :) -- LorenzoArticle: 60956
"Valeria Dal Monte" <aaa@bbb.it> ha scritto nel messaggio news:9qkbb.335067$Ny5.10649409@twister2.libero.it... > Some days ago Xilinx did workshops in many european > states. > Why Italy was excluded? Well, if you think that some multinationals put Italy into their SEMEA division (South Europe, Middle Europe and Africa), you can guess. We are considered just like Bulgaria or Libia and, with all the respect for these countries, I think we could deserve a little more. -- LorenzoArticle: 60957
"rickman" <spamgoeshere4@yahoo.com> ha scritto nel messaggio news:3F6E9C13.3B65F43E@yahoo.com... > [...] just makes the vendor look bad to > engineers. [...] Vendors look always bad to engineers. They shave, wear the tie in the summer and look happy, and this makes look us ugly. :-) -- LorenzoArticle: 60958
I remember the 70's well. :-) The TTL logic we used was slow by today's standards, with output delays of 25 ns and gentle rise and fall times. But the interconnect was fast, just wires, at 1 to 2 ns per foot. Now, in FPGAs, you have very fast logic, with extremely short transition times of <1ns, but the FPGA-internal interconnects are comparatively slow. It is now fairly normal to spend as much time travelling in the on-chip interconnects, as propagating through the logic. In the old TTL/MSI days, the logic and the flip-flops were very much slower than the interconnect. That means: The slow logic used to tolerate and swallow up interconnect delays, and the transitions were so slow that there were hardly any transmission-line effects. Now the logic is so fast and unforgiving, that the interconnect delays can no longer be ignored, and almost any pc-board trace must be treated as a transmission line. These "cultural differences" may bite you in your translation effort. So, beware of decoding glitches on the clock lines, of uncontrolled clock distribution delay differences, and hold time issues. And crank the chip-output drivers down to the weakest drive strength! You do not need speed; speed is your enemy, but the enemy is very much alive... Have fun! Peter Alfke ========================== rider wrote: > >. You are right about the synchronous > clock issue. I know its not good to use asynchronous designs, but i > have a different problem at hand. I am actually doing reverse > engineering of a board made in probably 1980. It has more than 200 > I/Os and over 180 TTL ICs. I have a rough schematic of it and no other > info. So, I thought it wouldn't be practical to start tracing the > boards functionality and make it SYNCHRONOUS ...and it may never be > possible i feel...so i had to go with combinatorial clocks which the > design is already using.. > > Now i know synchronous design has its advantages, but does that mean > that asynchronous design will never work..in discrete ICs or in FPGA? > Please comment.. > > RiderArticle: 60959
dgleeson-2@utvinternet.com (Denis Gleeson) wrote in message news:<184c35f9.0309250354.763cf662@posting.google.com>... > Hello All > > OK Im a bit confused. > > the verilog code > > always @(posedge CLK or posedge CLR) > begin > if (CLR) > Q <= 20'b0; > else > if (CE) // Is counter Enabled. > begin > Q<=Q+1; > end > end > > produces a ripple counter? Yes, No? Looks like a synchronous counter to me. > When I look at my simulation results I see glitches in the count output > leading me to assume that I have implemented a ripple counter. What simulator are you using? What's in your test bench? > IS it possible to remove the glitches with a synchronous Binary counter? > If yes what is the verilog code? You wrote it. -aArticle: 60960
Hi Rider,
As others have said, you'll probably find 2) quite tricky. Why
not synchronously clock the whole thing a lot faster, say 100MHz, and
make synchronous models of the slow logic and FFs? This way you
overcome the hideous skew problems? The old TTL switches slowly so any
10ns latency due to the 100MHz clock won't matter. Modern FPGAs have
many orders of magnitude more logic than TTL so the extra gates aren't
a problem.
Just an idea, Syms.
shabana_rizvi@yahoo.com (rider) wrote in message news:<ca3a68c8.0309232334.15e2561a@posting.google.com>...
> Hi !
>
> Thanks for the great help offered by the group to our FPGA issues.
> This time the queries are:
>
> 1) I am planning to use a LM317(National Semi) Regulator to power my
> board having Spartan2 XC2S150 and some other TTL Ics. Would this
> regulator be able to provide the required POS current [power on surge
> current] for the FPGA? What current rating is recommended? 2A or more?
> If this is not good, which regulator would be OK?
>
> 2)I have a 20MHz clock in my design that is used in some flip flops in
> the design. Most of the circuit is combinational and with about 18
> combinational clocks. What bypass capacitor ratings would be OK for my
> design .01uf would be OK?
>
> 3)In XST 5.1i , there is a synthesis option which says "Add I/O
> buffers". Does that mean that if i check this option, the XST would
> automatically insert I/O buffers[IBUF,OBUF,IBUFG,OBUFT etc] into my
> top-level module ports and i don't have to instantiate these I/O
> buffers into my HDL code?
>
> Thanks
> Rider
Article: 60961Hi Antti, > 5 intercept dll, it exposes xilinx DLL entry points and call xilinx > dll > (that you have renamed) part of the calls are re routed to your dll > that then talks to your hardware that sounds good to me. I never thought of that way. Isn´t it possible to stack a filter onto xilinx kernel driver? Do you know which Xilinx DLL I have to deal with? :-) thomasArticle: 60962
Hi, I have a design that was compiled in Quartus II 2.0 (SP2) and used 22,000 logic elements on the APEX20K1500E device. I compiled the same design in Quartus II 2.2 (SP2) and it takes 42,000 logic elements !! Has anyone seen such strange behavior with Quartus II 2.2 ? If so, how is this bug fixed ? Thanks, Prashant PS : Also, in the summary report, Quartus II 2.0 shows 85/493 pins used, while Quartus II 2.2 shows 85/488 pins, for the same device.Article: 60963
James Williams wrote: > What part of it can be commented out. Does the PC care that it is a plug > and play connection? > > Will it fit on a CPLD 95xxx? > > Regards, > > James > > > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0309242225.6c35065f@posting.google.com... > >>Jon Elson <jmelson@artsci.wustl.edu> wrote in message > > news:<3F7208C4.3050506@artsci.wustl.edu>... > >>>James Williams wrote: >>> >>> >>>>Is there one with the IEEE 1284 Core VHDL that is in english? >>>> >>>> >>> >>>I poked around a while and found the VHD file, which seems readable. >>>I haven't tried to UNDERSTAND it yet, however - that is different. >>> >>> > > http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd > >>good, come alone and you all will learn japanese as god as I ;) >> >>I dont understand nothing in japanese. >>And this is how I read japanese HDL/FPGA pages: >>1 check pictures >>2 check all hyperlinks, even if page is japanese the línks may have >>english page names :) >>3 download all HDL files and all archive files, check whats inside >> >>the link what you found seems to be full IEEE1284 peripheral core with >>plug and play support (there is screenshot of the plug and play >>enumeration >>so I assume it is working and verified on FPGA) >> >>the design does synthesise out of box for >>Xilinx XST 256 Slices >>or 60% of XC95 144 >>for Actel APA075 its 25% >> >>the design is larger than commercial IEEE1284 cores, but it has >>plug and play enumaration built in (what you can easily comment out if >>needed) >> >>antti > > > look out our Chameleon POD based Parallel port. We have designed on it 1284 EPP controller, it works fine, and is fully tested in your ' OCDemon Raven JTAG ' configuration. Our EPP controller core is very small and can be mapped on a 64 Flip-Flops device (ex: Xilinx Coolrunner XCR3064XL or other CPLD) Contact me if you want pur EPP controller core, I can give you the VHDL source if you need. Laurent Amontec Team www.amontec.com _____________________________________ We provide new low cost solutions for FPGA Download and Processor Debug (parallel port and USB support) ------------ And now a word from our sponsor ---------------------- For a quality mail server, try SurgeMail, easy to install, fast, efficient and reliable. Run a million users on a standard PC running NT or Unix without running out of power, use the best! ---- See http://netwinsite.com/sponsor/sponsor_surgemail.htm ----Article: 60964
That is the title of my keynote address at the FPGA Developers' Forum, Oct 21/22, in London. If you can make the place and the date, it would be nice to meet you there. Below is the official invitation (not in my words, witness the English spelling!). Peter Alfke "This is your chance to meet some of the world's top field-programmable gate array (FPGA) developers at one of Europe's leading FPGA events, taking place in London on the 21st and 22nd of October 2003. This event is supported by Mentor Graphics and Xilinx. The IEE has assembled a world class series of speakers from organisations including Xilinx, Celoxica, QinetiQ, NASA, Semico Research and Mentor Graphics to address today's most pressing issues in FPGA specification, applications, design and development. Day one features world-leading experts sharing their experience in implementing complex systems using FPGA technologies and will address areas such as technology, tools, hardware and software developments. Day two has leading researchers sharing their experiences of using FPGAs in a range of areas including nanotechnology, software radio, aerospace and image processing." For information on how to register, and full programme details, please visit: http://conferences.iee.org/fpga/Article: 60965
Hi All
I have a Nios Development Board that has a crystal osciallating at 50MHz.
This is correct as I have seen the waveform and measured the frequency on an
osilloscope.
I am trying to implement USB Prototcol, for which I need a clock speed of
48MHz. How can I reduce the clock speed from 50 to 48. I have written a code
that reduces a given speed to any speed, however it has its limitations.
The code is presented below. This code is fully generic, thus user only has
to give the current clock speed and the wanted clock speed. This code works
fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz.
However it does not work for 30Mhz and 48Mhz as the result is a fraction and
my code can't handle it.
How can i fix this. How can I generate a clock of 48Mhz given that the
crystal is 50Mhz.
Pls Advice (Aplogoies in advance as the code does not have any comments, but
it is very self-explanatory..)
Regards
=======================================================
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
entity slow_clk is
generic (
Clock_Speed : integer := 50000000;
New_ClkSpeed: integer := 50000000
);
port (
clock : in std_logic;
slow_clock : out std_logic
);
end entity slow_clk;
architecture behavioural of slow_clk is
constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2);
signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / 2);
signal sig_TmpClk : std_logic;
begin
slow_clock <= sig_TmpClk;
process is
begin
wait until rising_edge (clock);
if main_cnt = con_StopCnt then
sig_TmpClk <= not sig_TmpClk;
main_cnt <= 1;
end if;
else
main_cnt <= main_cnt + 1;
end if;
end process;
end architecture behavioural;
=======================================================
Article: 60966In the spirit of friendly competition let me tell you that Xilinx Virtex-II hs no problem with this. You just tell the DCM to multiply the 50 MHz by 24 and simultaneously divide it by 25 and, voila, you have a 48 MHz output. Peter Alfke, Xilinx Applications ===================== SneakerNet wrote: > > Hi All > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > This is correct as I have seen the waveform and measured the frequency on an > osilloscope. > > I am trying to implement USB Prototcol, for which I need a clock speed of > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a code > that reduces a given speed to any speed, however it has its limitations. > The code is presented below. This code is fully generic, thus user only has > to give the current clock speed and the wanted clock speed. This code works > fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz. > However it does not work for 30Mhz and 48Mhz as the result is a fraction and > my code can't handle it. > > How can i fix this. How can I generate a clock of 48Mhz given that the > crystal is 50Mhz. > Pls Advice (Aplogoies in advance as the code does not have any comments, but > it is very self-explanatory..) > > Regards > ======================================================= > LIBRARY IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > > entity slow_clk is > generic ( > Clock_Speed : integer := 50000000; > New_ClkSpeed: integer := 50000000 > ); > port ( > clock : in std_logic; > slow_clock : out std_logic > ); > end entity slow_clk; > > architecture behavioural of slow_clk is > constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2); > signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / 2); > signal sig_TmpClk : std_logic; > > begin > slow_clock <= sig_TmpClk; > > process is > begin > wait until rising_edge (clock); > if main_cnt = con_StopCnt then > sig_TmpClk <= not sig_TmpClk; > main_cnt <= 1; > end if; > else > main_cnt <= main_cnt + 1; > end if; > > end process; > > end architecture behavioural; > =======================================================Article: 60967
This is from memory since work doesn't have access to newsgroups so here goes. We have a Stratrix development board with the NIOS software package. Along with that is FS2 debugger. I have worked through the enclosed tutorials both the HW and SW. All was well and the debugger worked fine. I then wanted to add my own hardware into the PGA. I created a new project popped open Quartus 3.0 and SOPC builder creating a NIOS based system pretty much if not identical to the one in the tutorials. I used the germs_monitor.c. Popped open two SDK shells, one for nr -t -r and the other to compile and down load the C code. nd -d hello_nios.c and nb hello_nios.out following the tutorial. Well I get messages that it (OCI?) can not get the com1 port but the debugger window pops up. No green bar in the source code which indicates that communications is down. I have yet to get this setup, Stratix board and debugger to work on anything other than the tutorials. While in the SDk shell I did move to my project dir. Anybody out there have similar experiences? Thanks JerryArticle: 60968
"Peter Alfke" <peter@xilinx.com> wrote in message news:3F737316.F7015B6A@xilinx.com... > In the spirit of friendly competition let me tell you that Xilinx > Virtex-II hs no problem with this. You just tell the DCM to multiply the > 50 MHz by 24 and simultaneously divide it by 25 and, voila, you have a > 48 MHz output. > Peter Alfke, Xilinx Applications > ===================== And the Stratix or Cyclone Nios Development Board that was mentioned should be able to implement a similar frequency ratio with the Altera PLLs. Since, after all, that's the silicon he's using. > SneakerNet wrote: > > > > Hi All > > > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > > This is correct as I have seen the waveform and measured the frequency on an > > osilloscope. > > > > I am trying to implement USB Prototcol, for which I need a clock speed of > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a code > > that reduces a given speed to any speed, however it has its limitations. > > The code is presented below. This code is fully generic, thus user only has > > to give the current clock speed and the wanted clock speed. This code works > > fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz. > > However it does not work for 30Mhz and 48Mhz as the result is a fraction and > > my code can't handle it. > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > crystal is 50Mhz. > > Pls Advice (Aplogoies in advance as the code does not have any comments, but > > it is very self-explanatory..) > > > > Regards <code snipped>Article: 60969
I find your tone offensive Austin. I am simply trying to understand the issue being discussed by yourself as well as others. On my board there will be no traces that are near 12" much less 24" and the power supply will not be 3.6 volts. So what you are now talking about is not a typical board design, but rather a *bad* board design. That is not what you said. Your statements, as well as others, was that *every* board needs to be simulated. I agree that clock signals are very sensitive to signal integrity, but most data lines, that are not excessively long, will do no hard to most chips and SI issues will only add to the setup time. So if my traces are 6" and under and my Vccio is 3.3 volts or less, is it likely that a data trace will be at issue if it is not simulated? As I said, this is the first time I have heard anyone say that it can be an issue, *especially* an issue of doing damage to a chip. Ringing has been an accepted part of digital logic design since logic was invented. It is a problem, not because it exists, but only if it creats a malfunction. It can ring for an hour and I won't care if I have two hours of settling time on my bus. If you don't wish to discuss this politely, then please feel free to ignore my post. Austin Lesea wrote: > > Rick, > > Get off that horse: 'typical' ringing is not the issue here. > > Have said it a number of times: overshoot and undershoot is bad (period), and is > a sign of a bad board design. The fact that if you have > > 1) 85C Tj AND > 2) you have a power supply at 3.6 volts AND > 3) you have crappy SI over long t-lines (which store more energy -- like 12 - 24") > > MAY lead to exceeding the Abs Max spec. > > The point is that you have to simulate to get good SI, so do so. While you are at > it, if the SI is terrible, fix it. If you can't fix it, then make sure you are > within the Abs Max specs. > > Austin > > rickman wrote: > > > Austin Lesea wrote: > > > > > > Rick, > > > > > > Fight it as long as you can, but everyone else is using the more advanced > > > tools, and simulating everything (at the companies where they want to be > > > successful on the first pcb turn -- as for the others, I don't hear from > > > them often anymore....). > > > > Funny. But I doubt it is very accurate. I have worked at some of the > > larger companies making telecom test equipment and I have yet to meet a > > board designer who simulates all of the traces. The ones I spoke with > > only simulate the clock lines or other signal lines when the timing is > > tight with no time for settling. > > > > Like I said, this is the first time I have heard a chip maker claim that > > typical ringing and undershoot can cause chip damage. Of course an > > absurdly designed trace and create excessive swings. But the typical > > amount of ringing is normally listed in data sheets as being within spec > > for chips. > > > > > And yes, if you do not pay attention now, you will cause ground bounce (50 - > > > 60 mA of reflection current per IO is possible), > > > > Under what conditions is this "possible"? I would expect this to be an > > extreme case. The analyis listed here indicated much lower currents > > (~35 mA) and only for the brief time (< 1 ns) of the overshoot. If the > > device can't handle these low currents without ground bounce, how can it > > possibly provide the much larger currents (> 55 mA) for the initial > > level change without ground bounce? > > > > > and with the Virtex II Pro, > > > and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max > > > data sheet limits if you do not pay attention to what you are doing. And > > > that will cause a reduction in the 20 year projected lifetime. Below 3.0V, > > > there are no reliability issues to consider, as the clamp diodes are > > > sufficient to protect the IOs. Smaller, faster, less expensive technology > > > from the foundries has some drawbacks: leakage current, and IO robustness > > > at voltages greater than 3.75 volts being two of them. > > > > > > The new tools allow for extraction of all pcb parameters, and easy > > > simulation of all tracks/traces. You can also create a design that is > > > correct by construction: use DCI or series or parallel termination, and > > > make 50 ohm (or whatever) traces. Then you do not have to simulate > > > everything. > > > > So the DCI in the S3 chips will allow matching of the chip IO impedance > > to the trace, right? > > > > > Or use a standard: HSTL, SSTL, PCI. Then you also don't have to think. > > > But I also simulate to make sure I haven't missed anything. > > > > I only wish standards really did preclude the "thinking". I have worked > > with RS-232 and many others too long to beleive that. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60970
Austin Lesea wrote: > > Last post: > > See below, > > Austin > > rickman wrote: > > > Symon wrote: > > > > > > Hi Rick, > > > OK, I suppose 'MUST' isn't strictly accurate, you might not care > > > whether the design works or not! How about 'SHOULD' instead? ;-) Those > > > signals bouncing back and forth may not affect the circuits functional > > > operation, but what are you gonna do when it happens on a 5 inch, 32 > > > bit data bus and you can't pass the CE/FCC mark tests? Sell it in > > > Elbonia, I guess! > > > > Is there a good market there? If a 5 inch 32 bit data bus without > > termination precludes passing CE/FCC RFI tests, then no PC would ever be > > sold. Few RFI issues are solved purely at the PC board level. In US > > commercial markets, the requirements are very different than consumer > > markets as well. > > Yes, you can sell garbage. I don't think that we are talking about that > here: even game toys have to have just about every government and safety > lab certification known.... Thank you for that comment Austin. You are the first person to ever call my work garbage. > > > As for ground bounce, if those diodes are dumping energy, be sure > > > you've decoupled the Rx IC as well as the Tx one! Generally, it's > > > better not to have to rely on the diodes, don't you think? You end up > > > trading decoupling capacitors for termination resistors. > > > > That is assuming that the diodes would be triggered. I seem to recall > > that the basic analysis done here showed that this was unlikely. > > They are triggered at the receive end. Remember the low drive impedance, > high terminate impedance t-line case tries to as much as double the voltage > at the receive end. Remember Howard running across the room with his > pointer and banging into the wall (if you have been to one of his great > performances)? Instructive. > > > > > > > > I'm not saying simulate every trace. Simulate one, and layout the > > > rest accordingly, as I think Austin says in a parallel post. Check the > > > PCB layout very carefully, watching out for traces that don't comply > > > with your SI design. I like Austin's idea of adopting a standard > > > (HSTL, SSTL, PCI), makes it easy. > > > > That is the part I am not clear about. These traces are all individual > > circuits. If you have the luxury of a lot of open board space to route > > straight lines here and there, then sure, you can make each one very > > similar. On a small, tight board it will be very difficult to make them > > that similar. If the signal is critical enough to require a simulation, > > then I expect I would need to simulate each of them. > > Yes. That is the part that is not practical and I don't believe that it is required for most signals. Of course, the sensitivity of the Spartan 3 chips seem to place new boundries on ringing and SI. According to what you are saying, signal ringing can do damage to these chips while most chips in the past have not been that sensitive to it. > > I am surprized that the Spartan 3 chips are so sensitive to over and > > undershoot that this has become a major issue. I have seen lots of high > > speed boards and none had FPGAs or any other chips that needed this > > degree of analysis to prevent damage. > > Get off the horse. It is tired already. See my other post. If you are > going to have really bad SI, at 3.6V Vcco, AND 85C Tj, then you may have to > consider the abs max specs.....so do a good SI job, and you will never get > there. As I said in my other posts, I have been reading absolute max specs for years and many have specific exclusions for the brief time of over (or under) voltage due to ringing. A couple of ns of overvoltage has never fried a chip in any lab that I have worked in. > In previous families, there were Abs Max specs, and you could go past them, > too, with poor SI. This is only different because the numbers are tighter, > and the Vccint is now 1.2 volts, and bad SI will make the design fail to > function a long time before any IO will fail. Why not encourage designers > to be successful (hey, what a concept! if the design works, then we sell > more chips!). I understand. But your comments seem to be self contraditory. First you tell me the issue is SI which is common to all boards and then you say the issue is the extreme sensitivity of the new Spartan 3 chips to SI. SI is always relative. In the past the threshold of failure had to do with delayed settling or double clocking of edge signals. Now these new chips are much more sensitive to a new issue, SI induced failure. That is all we had to say and admit. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60971
Ppl Ppl Rather than fighting over which product is better, why not someone help me with the solution.. "John_H" <johnhandwork@mail.com> wrote in message news:LkLcb.12$Cr.9187@news-west.eli.net... > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3F737316.F7015B6A@xilinx.com... > > In the spirit of friendly competition let me tell you that Xilinx > > Virtex-II hs no problem with this. You just tell the DCM to multiply the > > 50 MHz by 24 and simultaneously divide it by 25 and, voila, you have a > > 48 MHz output. > > Peter Alfke, Xilinx Applications > > ===================== > > And the Stratix or Cyclone Nios Development Board that was mentioned should > be able to implement a similar frequency ratio with the Altera PLLs. Since, > after all, that's the silicon he's using. > > > SneakerNet wrote: > > > > > > Hi All > > > > > > I have a Nios Development Board that has a crystal osciallating at > 50MHz. > > > This is correct as I have seen the waveform and measured the frequency > on an > > > osilloscope. > > > > > > I am trying to implement USB Prototcol, for which I need a clock speed > of > > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a > code > > > that reduces a given speed to any speed, however it has its limitations. > > > The code is presented below. This code is fully generic, thus user only > has > > > to give the current clock speed and the wanted clock speed. This code > works > > > fine as I am using this code to reduce the clock speed to 12.5MHz and > 25Mhz. > > > However it does not work for 30Mhz and 48Mhz as the result is a fraction > and > > > my code can't handle it. > > > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > > crystal is 50Mhz. > > > Pls Advice (Aplogoies in advance as the code does not have any comments, > but > > > it is very self-explanatory..) > > > > > > Regards > > <code snipped> > >Article: 60972
"SneakerNet" <nospam@nospam.org> wrote in message news:<zQJcb.159026$JA5.3914623@news.xtra.co.nz>... > Hi All > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > This is correct as I have seen the waveform and measured the frequency on an > osilloscope. > > I am trying to implement USB Prototcol, for which I need a clock speed of > 48MHz. How can I reduce the clock speed from 50 to 48. <snip> [ ahem ] "Use the PLL on your Nois development board's Altera chip." Please see the altera documentation on the altpll megafunction http://www.altera.com/literature/ug/ug_altpll.pdf (Better response?)Article: 60973
"John_H" <johnhandwork@mail.com> wrote in message news:6c803f5f.0309251724.4394c459@posting.google.com... > "SneakerNet" <nospam@nospam.org> wrote in message news:<zQJcb.159026$JA5.3914623@news.xtra.co.nz>... > > Hi All > > > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > > This is correct as I have seen the waveform and measured the frequency on an > > osilloscope. > > > > I am trying to implement USB Prototcol, for which I need a clock speed of > > 48MHz. How can I reduce the clock speed from 50 to 48. > > <snip> > > > [ ahem ] > > "Use the PLL on your Nois development board's Altera chip." > Please see the altera documentation on the altpll megafunction > > http://www.altera.com/literature/ug/ug_altpll.pdf > > (Better response?) A lot better. at least this answer was specific to my question ;o) ThanksArticle: 60974
> thank you for your explanation ; now i will have no more regret to use > all those registers ! Heh yeah, registers are "free." If your design can handle the register delays, use them as often as you can, it'll make your routing easier. I throw in registers without thinking about it. I'm sure if I ever work for an ASIC company, I'll have to unlearn that habit. Also the LUTs can be used as 1-bit wide shift registers that can be 1-16 "registers" deep. They're called SRL16s. Very handy for adding delay to signals to make them line up with other signals, clock cycle wise. Regards, Vinh
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