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"Subroto Datta" <sdatta@altera.com> wrote [...] Thank you *very* mutch!Article: 62126
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3F8DBF2B.2595@designtools.co.nz>... > etrac wrote: > > > > Hi, > > We have found the problem and this might interest somebody here so I > > explain the reasons of the voltage falling : It was simply because we > > put too many bypassing capacitors around the FPGA ! The virtex II > > datasheet is asking for many capacitors to have good linearity in the > > fpga voltages, but our power supply was not enough strong to support > > the current when we power on the board. > > > > Etrac. > > > > etrac wrote: > > > > > > > > > We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power > > > > > seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO > > > > > are asking too much current (> 1.5A) for a long time. This occurs > > > > > approximatively 1 second after the power is on. > > > > > We have a current limitation power supply, so the VccAux/VccO voltage > > > > > fall at nearly 1.5V, that is to say that the FPGA needs very much than > > > > > 1.5A .. > > This does not quite 'gel' - you are saying lowering the Total C alone > solved the issue ? > > That suggests a dV/dT limit, but times in the order of 1 second ? > It may be a power-sequencing effect, which total C would affect. > > -jg Our power supply is current limited (2 Amps), and at poweron capacitors were asking too many current for the power supply. So we were in overcurrent mode. That was the same problem with our laboratory power supplies, with a current limitation .. EtracArticle: 62127
I bought the ISPLever product which comes with both synplify and Leonardo, in used to use Leonardo most of the time as a prefered the layout of it. However when i got errors in my code i would use both as the majority of the time they would word the cause of the error differently. We now have a full license for Leonardo whcih does alot more than synplify, so i use Leonardo all the time. Regards, Matt "David Brown" <david@no.westcontrol.spam.com> wrote in message news:bn0j25$91g$1@news.netpower.no... > I'm using the downloadable version of ispLever for a verilog project on a > Lattice Mach 4 CPLD chip. The software has both Synplify and Leonardo > Spectrum available for synthesis. I can build the code (so far, anyway) > with either tool. Is there any reason why I should choose one over the > other? > > -- > David > > "I love deadlines. I love the whooshing noise they make as they go past." > Douglas Adams > >Article: 62128
I'm using the downloadable version of ispLever for a verilog project on a Lattice Mach 4 CPLD chip. The software has both Synplify and Leonardo Spectrum available for synthesis. I can build the code (so far, anyway) with either tool. Is there any reason why I should choose one over the other? -- David "I love deadlines. I love the whooshing noise they make as they go past." Douglas AdamsArticle: 62129
Hi, I am facing the same problem. I have a design in XC2S400E which is working well in ISE 5.1 sp3 and met all timing requirements. When I moved to 5.2 it failed to give required timing. I did not worry b'coz I knew that they are coming up with 6.1. Now when I synthesized/implemented my design in 6.1 (latest sp), it is giving the same result as in 5.2 (i.e. it is unable to meet the performance of 5.1). Now I am sticking with 5.1i since I have already used it for many months, and also given my product to some customers (I need to support them!!!). My gut feeling is that when they changed from 5.1 to 5.2 something has gone wrong in the tool software, and when they upgraded to 6.1 since they used 5.2 (i assume! ) as base version, the problem continued to exist even in 6.1. This is a clue to Xilinx people (anybody here?) so that they can findout the cause of this problem. Could anybody give assurance that atleast next versions will be free from critical problems like these? Regards, Nagaraj CS "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<bmp871$22k$1@news.storm.ca>... > Hi all, > > I have updated my Xilinx software to 6.1 a few days ago and it > looks like I am in for a ride; the design that worked well under > the previous version (5.2 with all service packs) wouldn't even > go through PAR anymore!! I managed to work around this > by setting thr effort level to maximum for the place&route but > when I program the FPGA (XC2V4000-5) with this new bitstream > my board doesn't work anymore!!? > Anybody having similar problems? > I guess I shoild have known better: the service pack for this latest > software creation arrived before the CD with the software did! > In my humble oppinion the best software from Xilinx was 4.2, > it's all downhill from there; it seems that a nice GUI is valued more than > a decent and consistent PAR algorithm these days. > --- > jakabArticle: 62130
"Rene Tschaggelar" <none@none.none> wrote in message news:65d1183ec9a699ea0d4f9acbd7c3a815@news.teranews.com... > Dieter Keldenich wrote: > > Hi, > > > > does anybody have experience in using Altium DXP for designing Xilinx FPGA? > > Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) for > > using them in DXP? > > DXP is not supported by Xilinx, what are the risks in using it? I evaluated DXP but unfortunately it expired before I got to the FPGA/VHDL part, from what I hear from others it is a decent tool, again , I don't have specifics. > > You should ask this question on the altium forums, > available at the altium website. I think this si a valid question in this newsgroup, instead of lecturing people maybe you should try to help them! It would fit more with the spirit of this newsgroup! > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net >Article: 62131
Thomas Stanka wrote: > > Xpost 2 cae and caf, no Fup. > > Hallo, > > "Geoffrey Mortimer" <me@privacy.net> wrote: > > Anyone have any experience of BGA's (especially fine pitch types) in high > > vibration environments? Is there a more appropriate newsgroup for this > > topic? > > Actually that's a very hot topic as BGA seems to get usual in the > world of FPGAs and ASICs. I know that our mechanical engineers > allready research on this topic, as we are very likely to have some > fine pitch BGA in a high vibration environment in future. > I would guess, that you should ask in some mechanical newsgroups as > well. > A big problem using FBGA is the test, wether you connected all balls > proberly [1], as you have no chance of easy visual inspection. > > bye Thomas I recently saw a product that allows visual inspection of the solder balls on a mounted BGA. It is a fiber optic microscope and has tiny fiber probes that can run between the balls. I'll look for the info if anyone is interested. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62132
etrac wrote: > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3F8DBF2B.2595@designtools.co.nz>... > > etrac wrote: > > > > > > Hi, > > > We have found the problem and this might interest somebody here so I > > > explain the reasons of the voltage falling : It was simply because we > > > put too many bypassing capacitors around the FPGA ! The virtex II > > > datasheet is asking for many capacitors to have good linearity in the > > > fpga voltages, but our power supply was not enough strong to support > > > the current when we power on the board. > > > > > > Etrac. > > > > > etrac wrote: > > > > > > > > > > > We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power > > > > > > seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO > > > > > > are asking too much current (> 1.5A) for a long time. This occurs > > > > > > approximatively 1 second after the power is on. > > > > > > We have a current limitation power supply, so the VccAux/VccO voltage > > > > > > fall at nearly 1.5V, that is to say that the FPGA needs very much than > > > > > > 1.5A .. > > > > This does not quite 'gel' - you are saying lowering the Total C alone > > solved the issue ? > > > > That suggests a dV/dT limit, but times in the order of 1 second ? > > It may be a power-sequencing effect, which total C would affect. > > > > -jg > > Our power supply is current limited (2 Amps), and at poweron > capacitors were asking too many current for the power supply. So we > were in overcurrent mode. That was the same problem with our > laboratory power supplies, with a current limitation .. > > Etrac Isn't that a common mode during power on? Exactly what problem does this cause? Are you saying that the current causes a voltage foldback so that the rise is not monotonic? If so, your problem is not the capacitors, it is the foldback current limiting. I find it hard to imagine the caps on a board having more total capacitance than a power supply. But I guess you may be working with an on board DC/DC with 100 uF or less. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62133
Lorenzo Lutti wrote: > "Ljubisa Bajic" <eternal_nan@yahoo.com> ha scritto nel messaggio > news:9b0afb2c.0310190955.aa5708d@posting.google.com... > > >>It is incredible that in response to an inquiry about >>technical workshops you found it appropriate to insult >>some countries (in fact whole regions!; even >>continents!!), > > > Insult?! I have simply said that some multinationals consider Italy > (from a *business* point of view) just like countries that are > objectively far less industrialized than us. Italy is in the G8, Libia > and Poland aren't even in the G20. When I say we "deserve" better, I > mean that we could have a lot more technological resources to invest in > FPGA world. This is a fact, not an offense. > > I didn't mean to insult anyone! If I did so, I apologize to whoever > could have been offended. Probably the guilt is my bad english, I'm not > able to express all my thoughts exactly. :) > The G8 membership might distort the picture a bit. South of say Bolognia there is not much Technology anymore. A few Tomatoes and Olives plus lots of companies using the cheap labour for simple jobs. ReneArticle: 62134
jakab tanko wrote: > "Rene Tschaggelar" <none@none.none> wrote in message > news:65d1183ec9a699ea0d4f9acbd7c3a815@news.teranews.com... > >>Dieter Keldenich wrote: >>> >>>does anybody have experience in using Altium DXP for designing Xilinx >> FPGA? >>Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) >>for >>using them in DXP? >>>DXP is not supported by Xilinx, what are the risks in using it? >> > > I evaluated DXP but unfortunately it expired before I got to the FPGA/VHDL > part, from > what I hear from others it is a decent tool, again , I don't have specifics. > > >>You should ask this question on the altium forums, >>available at the altium website. > > > I think this si a valid question in this newsgroup, instead of lecturing > people > maybe you should try to help them! It would fit more with the spirit of this > newsgroup! Sorry about that. Well, I didn't come this far with DXP yet. Obviously this poster was not aware of the Altium groups. They are a definite must for every DXP user anyway. Perhaps a more knowledgeable DXP user knows an answer here. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 62135
Not necessarily. The RTL coding can strongly bias a designs suitability to a
particular architecture. This situation has improved slightly in the latest
generations because the architructures are starting to look more like one
another, but still the architecture of your design heavily influences how
that design maps into the underlying FPGA architecture. A not so obvious
example concerns arithmetic. The altera structure reduces the logic to 2
input arithmetic with an added add/subtract control where the Xilinx
architecture leaves you with a 4 input arithmetic function, making it treat
things like mux-add functions a bit differently.
Mike Treseler wrote:
> rickman wrote:
>
> > You can analyze the differences on paper all day, and you still won't
> > know how your design will do in either family of parts. The best thing
> > to do is to write your HDL to be generic and see how it fits.
>
> Well said.
>
> Working generic synth code cuts through
> technobabble like a knife. It tests
> the tools and the device from front to back
> and provides utilization and fmax benchmarks
> that you just can't get any other way.
>
> That said, I have noticed that Altera's
> ep1s series is much more Xilinx-like than
> ep20k.
>
> -- Mike Treseler
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 62136
I'm trying to use a subroutine (subprogram procedure) in my testbench to
(eventually) simulate processor reads and writes. When I compile and try to
simulate(Xilinx ISE 6.1i and Modelsim) I get "# ERROR: testbench.vhd(34):
Cannot drive signal in3 from this subprogram." Any idea why? Can it be
corrected?
Thanks
Dan
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT tb_subroutine
PORT( clk : IN std_logic;
reset : IN std_logic;
in1 : IN std_logic;
in2 : IN std_logic;
in3 : IN std_logic;
out1 : OUT std_logic;
out2 : OUT std_logic;
out3 : OUT std_logic
);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL reset : std_logic;
SIGNAL in1 : std_logic;
SIGNAL in2 : std_logic;
SIGNAL in3 : std_logic;
SIGNAL out1 : std_logic;
SIGNAL out2 : std_logic;
SIGNAL out3 : std_logic;
procedure set_in3
--subroutine
begin
in3 <= '1';
end procedure set_in3;
BEGIN
gen_clk : process(clk)
begin
if (clk = '0') then
clk <= '1' after 6.25 ns; --12.5 period = 80mhz
else
clk <= '0' after 6.25 ns;
end if;
end process;
uut: tb_subroutine PORT MAP(
clk => clk,
reset => reset,
in1 => in1,
in2 => in2,
in3 => in3,
out1 => out1,
out2 => out2,
out3 => out3
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
reset <= '1';
in1 <= '0';
in2 <= '0';
in3 <= '0';
wait for 50 ns;
reset <= '0';
wait for 50 ns;
in2 <= '1';
wait for 50 ns;
in1 <= '1';
wait for 50 ns;
set_in3; --call
subroutine
wait for 50 ns;
in3 <= '0';
in2 <= '0';
in1 <= '0';
wait for 50 ns;
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
Article: 62137
Actually, the SRL's are probably no good for that. They have a considerably
longer minimum pulse width than the regular flip-flops. I'm not privy to the
actual construction, but I'd be it is more akin to latches than to real
flip-flops. Your best resynchronizer will use the regular flip-flops,
floorplanned to use adjacent slices within a CLB and using the fast direct
connect route between the flip-flops.
Peter Alfke wrote:
> Metastability is unavoidable. Whether it hurts you depends on the clock
> and data frequencies and also on the technology used.
> I will not guarantee that SRL16s recover as fast from metastability as
> the "normal" flip-flops that I documented, since SRLs are implemented in
> a different circuit design. (Different might mean better or worse).
>
> Peter Alfke
> =================
> David R Brooks wrote:
> >
> > If I create a two-FF chain (with common clock), XST will likely pull
> > those two FFs into a SRL16. Is it permissible to use two bits of a
> > SRL16 as a synchroniser in this way? (It surely must be the
> > shortest-possible path between two FFs).
> >
> > Peter Alfke <peter@xilinx.com> wrote:
> >
> > :You should always be concerned about metastability, whenever
> > :asynchronous signals are being synchronized. Let me add some numbers to
> > :Phil Freidin's excellent comments:
> > :
> > :Metastability creates unpredictable additional settling delays (even
> > :oscillations can be considered delays to valid out). The probability of
> > :a specific max delay depends on the clock rate, the data rate, and the
> > :IC technology.
> > :
> > [snip]
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 62138Followup to: <belkb.1647$2O3.332@newssvr14.news.prodigy.com> By author: JoeG <JoeG@spam.net> In newsgroup: comp.arch.fpga > > I'm glad I didn't have access to the Inet during my college days, as my > efforts in class/homework would not have been as rewarding and industrious. > I *am* glad that I had access to the Internet at my university; it was both a great study tool and provided the opportunity for branching out in areas I would otherwise never have expected -- this is how I got involved with Linux, back when noone had heard of it. Like anything else it can be abused. Students asking people to do their homework for them figured back then... these days they tend to do it from anonymous yahoo accounts, however, which means that it's not just ignorance, but that they know they're cheating. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 62139
> > In Nios versions prior to 3.0, we had a different debug solution that > operated over serial port rather than JTAG. While I don't recommend > going backwards in terms of Nios CPU version, if its absolutely > essential that you use the GDB debugger with your ACEX device, you > might consider (temporarily) going back to Nios v2.2 to use the > non-JTAG debugging... this method operates over UART, and therefore > does not require the special JTAG enhancements which came out after > ACEX. If its possible to debug with your APEX device and then move to > a final test of your ACEX-based product with OCI turned off, this > would be the easiest solution. > Ooops! Just wanted to correct myself here- in Nios 3.0 (and later), you *can* use the old UART-based debug solution, allowing the use of GDB/Insight debugging in Flex & Acex-based Nios designs. The newer device families allow use of the OCI (JTAG-based) debug core as noted above, but the older devices can still be debugged using the serial port. Thanks to Mr. Sabater for pointing this out. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 62140
Is this info available yet? The latest datasheet does not seem to have it. (planning a $100 10Gs/sec sampling scope) Peter WallaceArticle: 62141
Followup to: <3F93E3DC.6753DCD4@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > I recently saw a product that allows visual inspection of the solder > balls on a mounted BGA. It is a fiber optic microscope and has tiny > fiber probes that can run between the balls. I'll look for the info if > anyone is interested. > A lot of people seem to do X-ray inspection, which I guess could be considered "visual" in some way. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 62142
Followup to: <d6ad3144.0310191907.619e5da3@posting.google.com> By author: jakespambox@yahoo.com (Jake Janovetz) In newsgroup: comp.arch.fpga > > > What do you mean by "memory performance?" Latency for sequential > > access? Latency for parallel accesses? Throughput for a single > > stream? THroughput for multiple streams sharing memory? THroughput > > for multiple streams from independant memories? > > I don't think it matters. He just saying that FPGAs provide such an > abundance of functional units that memory performance (however you > call it -- the ability for a given system to provide data to the > function units) is limiting. He's got a 10,000 pound gorilla and he's > trying to feed it bananas with a teaspoon. > This is of course why FPGAs has extremely high speed onboard memory in small chunks that can be independently wired. The quantities are limited, of course, just like the caches on a CPU, but a lot of FPGA designs wouldn't be possible/practical without it. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 62143
Dan Kuechle wrote: > I'm trying to use a subroutine (subprogram procedure) in my testbench to > (eventually) simulate processor reads and writes. When I compile and try to > simulate(Xilinx ISE 6.1i and Modelsim) I get "# ERROR: testbench.vhd(34): > Cannot drive signal in3 from this subprogram." The procedure may be out of the scope of the signals it is trying to drive. Related thread: http://groups.google.com/groups?q=vhdl+procedure+scope+wiggling -- Mike TreselerArticle: 62144
Sorry - newbie here so not the most brain draining question. I want to test if a previous design works on a board that I have. The previous design was done for a similar board. What I want to know - Can I just take the .bit file and send it down via IMPACT? That way eliminating any Xilinx different version conflict between my software and the software it was designed on? Basically to see if this design is working fine on my board - a previously simulated and synthesized .bit file ONLY is all I need to demonstrate the working project fully???? Regards DArticle: 62145
If you want to make a general purpose subprogram for
testbenches and put it in a pacakge, you must have
all of the IO on the subprogram interface. As a
general rule of thumb for subprogram IO class
use the following:
Inputs:
------
From UUT: Make them signals
In general:
If you use signal property ('event) must be a signal,
otherwise make it a variable.
Outputs, InOuts:
----------------
To UUT: Make it a signal
To process/other subprogram: variable (so value updates immediately)
For synthesis:
usually used directly in architecture, so make it a signal
You can cheat temporarily by putting the subprogram declaration
in the process, but once you have more than one test architecture
this means you will have to multiple copies of your testbench.
Cheers,
Jim Lewis
p.s. We have are offering our Comprehensive VHDL Introduction
class in Huntsville, AL next week and we cover stuff just like
the above. Details are at:
http://www.synthworks.com/public_vhdl_courses.htm
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Dan Kuechle wrote:
> I'm trying to use a subroutine (subprogram procedure) in my testbench to
> (eventually) simulate processor reads and writes. When I compile and try to
> simulate(Xilinx ISE 6.1i and Modelsim) I get "# ERROR: testbench.vhd(34):
> Cannot drive signal in3 from this subprogram." Any idea why? Can it be
> corrected?
>
> Thanks
>
> Dan
>
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.ALL;
> USE ieee.numeric_std.ALL;
>
> ENTITY testbench IS
> END testbench;
>
> ARCHITECTURE behavior OF testbench IS
> COMPONENT tb_subroutine
> PORT( clk : IN std_logic;
> reset : IN std_logic;
> in1 : IN std_logic;
> in2 : IN std_logic;
> in3 : IN std_logic;
> out1 : OUT std_logic;
> out2 : OUT std_logic;
> out3 : OUT std_logic
> );
> END COMPONENT;
>
> SIGNAL clk : std_logic;
> SIGNAL reset : std_logic;
> SIGNAL in1 : std_logic;
> SIGNAL in2 : std_logic;
> SIGNAL in3 : std_logic;
> SIGNAL out1 : std_logic;
> SIGNAL out2 : std_logic;
> SIGNAL out3 : std_logic;
>
> procedure set_in3
> --subroutine
> begin
> in3 <= '1';
> end procedure set_in3;
>
> BEGIN
>
> gen_clk : process(clk)
> begin
> if (clk = '0') then
> clk <= '1' after 6.25 ns; --12.5 period = 80mhz
> else
> clk <= '0' after 6.25 ns;
> end if;
> end process;
>
> uut: tb_subroutine PORT MAP(
> clk => clk,
> reset => reset,
> in1 => in1,
> in2 => in2,
> in3 => in3,
> out1 => out1,
> out2 => out2,
> out3 => out3
> );
>
> -- *** Test Bench - User Defined Section ***
> tb : PROCESS
> BEGIN
> reset <= '1';
> in1 <= '0';
> in2 <= '0';
> in3 <= '0';
> wait for 50 ns;
> reset <= '0';
> wait for 50 ns;
> in2 <= '1';
> wait for 50 ns;
> in1 <= '1';
> wait for 50 ns;
> set_in3; --call
> subroutine
> wait for 50 ns;
> in3 <= '0';
> in2 <= '0';
> in1 <= '0';
> wait for 50 ns;
>
> END PROCESS;
> -- *** End Test Bench - User Defined Section ***
>
> END;
>
>
Article: 62147"DGW" <chippa11@hotmail.com> wrote in message news:3f943a26$0$21654$afc38c87@news.optusnet.com.au... > Sorry - newbie here so not the most brain draining question. I want to test > if a previous design works on a board that I have. The previous design was > done for a similar board. How similar? > What I want to know - Can I just take the .bit > file and send it down via IMPACT? That way eliminating any Xilinx different > version conflict between my software and the software it was designed on? > Basically to see if this design is working fine on my board - a previously > simulated and synthesized .bit file ONLY is all I need to demonstrate the > working project fully???? Generally, the bit file has to be originally generated for the same Xilinx device in the same package and your board should be using the same pins. If the device is different IMPACT will probably simply refuse to load the file, which is not more than a frustration. If, however, your new board uses pins differently you might end up having to deal with a much bigger problem. /Mikhail P.S. This question has nothing to do with comp.lang.vhdl, so I am not replying there...Article: 62148
Hi Rene, I do not find any Altium- or DXP-group here on my news server. Also on www.altium.com, I only find an info, that there will come up a forum soon. Where can I find the altium group? thanks in advance Dieter "Rene Tschaggelar" <none@none.none> schrieb im Newsbeitrag news:a91788f472d3dfa287e0664cd79fe203@news.teranews.com... > jakab tanko wrote: > > "Rene Tschaggelar" <none@none.none> wrote in message > > news:65d1183ec9a699ea0d4f9acbd7c3a815@news.teranews.com... > > > >>Dieter Keldenich wrote: > >>> > >>>does anybody have experience in using Altium DXP for designing Xilinx > >> FPGA? > >>Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) > >>for > >>using them in DXP? > >>>DXP is not supported by Xilinx, what are the risks in using it? > >> > > > > I evaluated DXP but unfortunately it expired before I got to the FPGA/VHDL > > part, from > > what I hear from others it is a decent tool, again , I don't have specifics. > > > > > >>You should ask this question on the altium forums, > >>available at the altium website. > > > > > > I think this si a valid question in this newsgroup, instead of lecturing > > people > > maybe you should try to help them! It would fit more with the spirit of this > > newsgroup! > > Sorry about that. > Well, I didn't come this far with DXP yet. > Obviously this poster was not aware of the Altium groups. > They are a definite must for every DXP user anyway. > Perhaps a more knowledgeable DXP user knows an answer here. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net >Article: 62149
In article <d6ad3144.0310191907.619e5da3@posting.google.com>, Jake Janovetz <jakespambox@yahoo.com> wrote: >> What do you mean by "memory performance?" Latency for sequential >> access? Latency for parallel accesses? Throughput for a single >> stream? THroughput for multiple streams sharing memory? THroughput >> for multiple streams from independant memories? > >I don't think it matters. He just saying that FPGAs provide such an >abundance of functional units that memory performance (however you >call it -- the ability for a given system to provide data to the >function units) is limiting. He's got a 10,000 pound gorilla and he's >trying to feed it bananas with a teaspoon. It matters ALOT. Latency and large memory, you're fucked. Overlapping latency is not so bad. Streaming access from multiple banks? If it's predictible enough, you can be running those pins at 266 MHz DDR at full rate all the time. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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