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Matt,
This may be due to a failure in finding the Quartus Web Edition License.
If you open Quartus and open the Tools->License Setup, it should say that
you have a Quartus Web Edition License. If you do not see this, the
compilation failure is due to the inability to find the license.
Typically this is seen if you have a license tied to the NICID, and you are
not connected to the network. Please make sure that you are connected to the
network when you invoke Quartus. WindowsXP and Windows2000 have the side
effect of hiding the NICID from the application if you are not connected to
the network.
You can find more information in the app note
http://www.altera.com/literature/an/an229.pdf pgs's 14-20 on this topic.
Hope this helps.
- Subroto Datta
Altera Corp.
"Matt Ettus" <matt@ettus.com> wrote in message
news:e8fd79ea.0304121251.2fe07403@posting.google.com...
> I have a laptop running Windows XP Personal. For some reason,
> Altera's Quartus II Free web version does not run properly. Whenever
> I try to compile something, I get the message:
>
> Design test_proj: Full compilation was unsuccessful. 1 error, 0
> warnings.
>
> There is no more info. The error message is not clickable. Altera's
> online tech support has been unable to help beyond pointing me to
> appnotes that don't apply.
>
> I don't think the problem is me, because I was able to get the tools
> to install on another machine. Unfortunately, that was not my
> machine. My only windows machine is this laptop.
>
> Is there anyone who can help? If you're in the bay area, I'd trade
> you a nice lunch for getting this to work on my machine.
>
> Thanks
> Matt
Article: 54526Garrett Mace wrote: > But do you think a roll-your-own USB cable might be even simpler? > USB microcontrollers are awfully easy to come by now. One MCU + a few > passives and it's done. Probably so for most FPGA users. I prefer to use Ethernet because I work both from PC and from Unix WS. My hardware has a logic more than just a hardware port otherwise it is not easy to keep up with faster TCK clocking. (> 1MHz) Note: TCK 1MHz means you need to update the port at 2MHz rate. The real speed up is depending upon software and the protocol between the host and your pod. I started writing a JTAG class library to communicate to my JTAG registers. And later I added software to program Xilinx FPGAs. Xilinx has a nice documentation about such. Anyway, if you can get 1MHz *sustained* TCK clocking, it would be good enough even for 6 million gate FPGA (XC2V6000). I have another idea to achieve higher TCK clocking but I'm happy about the current speed for now. Aki-Article: 54527
module test; reg a; initial begin //non blocking assignment #0 a<=0; #10 a<=1; #20 a<=0; end initial begin #100 $stop; end endmodule From the code above, I expect that "a" will change from 1 to 0 at t=20, instead I got it changes at t=30, so the simulator treat it as though my code is a blocking assignment. Why is that? Thanks in advance!Article: 54528
HI, xapp644 has given you a completed answer. Regards, SeyiorArticle: 54529
I have been looking at the XCR3032XL and XCR3064XL for an application where I will be pushing on the density. To make the design fit, I will need to use all three modes of the macrocells for most of the pins. The basic function will be a bidirectional combinatorial signal path. But there aren't enough spare macrocells to provide a few internal control registers. So I am looking hard at the data sheet to see if I can use the register along with the combinatorial logic. In a sense this is time multiplexed. All of the outputs will be disabled while the registers are being loaded. This will be done though two inputs and the macrocell PLA. Then when the registers contain the data, an enable input will be toggled to enable the outputs that will be used in this mode. When operating, the macrocell logic will be on the output on some cells, and the pin will be an input on the others. In both cases the register will need to be fed back to the routing array to steer the inputs to the outputs. The role of input and output are reversed depending on the steering data. From what I can see in the diagrams, the muxes and the data paths required exist. But they don't provide any info on the control bits for this. Has anyone done this before? Can you feed the combinatorial logic to the pin tristate buffer while feeding the register as well as the pin input to the internal routing? Maybe I need to install the Webpack and see if it will allow me to program this. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54530
I use synplify to try to generate a black box that has to be integrated in future design as a black box ( in edif ). This edif will be used as a part of a design but not necessarly in synplify ( XST for example ) But this module has tri states busses and I have some diferent behavior on different busses. Often the tristate bus is driven by a BUFE instead of a BUFT and I tried a lot of changes without having the right BUFT in output. Can you tell me if there are reasons to have a BUFE instead of a BUFT and how to reach a full Tristate bus outside of my box ? RegardsArticle: 54531
On Fri, 11 Apr 2003 10:55:15 -0700, Mike Treseler <tres@fluke.com> wrote: >Martin Thompson wrote: > >> I'm just about to start down the Xilinx road and has thought of doing >> a similar thing myself (I've been spoiled by Altera's LPM_RAM, which >> does a similar thing for you). Don't suppose you can share the code >> with us to save reinventing the wheel (probably square to start with >> in my case :-) > >If you have synthesis available, you can infer LPM RAM with brand A or X: > >here's an example: > >http://groups.google.com/groups?q=vhdl+address_q+lpm Lack of labels to attach LOCs and RLOCs has stopped me from using this method in the past. Do you know of a workaround? Thanks, Allan.Article: 54532
Does somebody know any ready hardware systems for raytracing acceleration ? How much can it cost?Article: 54533
Matt Check your computer with 'Time and Date' setting. Hope it solves the problem. Seung "Subroto Datta" <sdatta@altera.com> wrote in message news:<qF4ma.762$HM6.519@newssvr16.news.prodigy.com>... > Matt, > > This may be due to a failure in finding the Quartus Web Edition License. > If you open Quartus and open the Tools->License Setup, it should say that > you have a Quartus Web Edition License. If you do not see this, the > compilation failure is due to the inability to find the license. > > Typically this is seen if you have a license tied to the NICID, and you are > not connected to the network. Please make sure that you are connected to the > network when you invoke Quartus. WindowsXP and Windows2000 have the side > effect of hiding the NICID from the application if you are not connected to > the network. > > You can find more information in the app note > http://www.altera.com/literature/an/an229.pdf pgs's 14-20 on this topic. > Hope this helps. > > - Subroto Datta > Altera Corp. > > "Matt Ettus" <matt@ettus.com> wrote in message > news:e8fd79ea.0304121251.2fe07403@posting.google.com... > > I have a laptop running Windows XP Personal. For some reason, > > Altera's Quartus II Free web version does not run properly. Whenever > > I try to compile something, I get the message: > > > > Design test_proj: Full compilation was unsuccessful. 1 error, 0 > > warnings. > > > > There is no more info. The error message is not clickable. Altera's > > online tech support has been unable to help beyond pointing me to > > appnotes that don't apply. > > > > I don't think the problem is me, because I was able to get the tools > > to install on another machine. Unfortunately, that was not my > > machine. My only windows machine is this laptop. > > > > Is there anyone who can help? If you're in the bay area, I'd trade > > you a nice lunch for getting this to work on my machine. > > > > Thanks > > MattArticle: 54534
"Alex Gibson" <alxx@ihug.com.au> wrote in message news:<b6s4rb$8qi$1@lust.ihug.co.nz>... > "Neeraj Varma" <neeraj@cg-coreel.com> wrote in message > news:b6rva4$8dlcv$1@ID-159439.news.dfncis.de... > > The best place is to look is the respective distributor Websites....where > > they have given prices for low quantities... > > > > For Xilinx you can check www.insight.memec.com or www.avnet.com > > > > I've never seen the price of any fpga chips on any distributor website Check also: http://www.plis.ru/ The site (offical xilinx?) is in written in russion, but the prices are in USD. Just type the partnr. I found the prices are a good indication. Bye, R_edArticle: 54535
Wallace tree multipliers only make sense where fast adders cost more than minimum area adders. For FPGAs with built in
fast carry logic, this is not the case. I have a more detailed discussion on this on the multipliers page on my website.
john jakson wrote:
> boothmultipler@hotmail.com (booth multiplier) wrote in message news:<24160f43.0304111147.72b80b4d@posting.google.com>...
> > Dear All,
> > I have found a technique to reduce the area and the delay of Booth
> > Multipliers by %10. This technique can be applied on any multiplier
> > implementation which uses the Modified Booth Algorithm.
> > I wonder which companies could benefit from such an
> > improvement.Which companies would like to have it?
> > Can anybody help me to contact them?
> >
> > Thanks
>
> This is a much explored area and is thought to be completely
> understood.
>
> The Wallace structure is also well known and handily beats the Booth
> algorithm by larger & larger margins as the arrays get bigger. If
> anyone was really after speed, they would already be using Wallace
> despite its irregular structure.
>
> Wallace multiplication times can approach O(logN) times.
> Booth multiplication times generally follow O(N) times.
>
> Perhaps you should outline the idea and see if others will salute it,
> or perhaps you have reinvented one of the minor variations covered in
> many texts.
>
> I doubt that either Booth or Wallace recieved any fortune, but their
> names are immortalized here, perhaps yours will too.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54536This is a site of official distributor of xilinx in Russian Federation, Ukraine and Belarus (tel.:+70957875940, fax:+70957875935) > > http://www.plis.ru/ > > The site (offical xilinx?) is in written in russion, but the prices > are in USD. Just type the partnr. I found the prices are a good > indication. > > Bye, > R_edArticle: 54537
"Subroto Datta" <sdatta@altera.com> wrote in message news:<qF4ma.762$HM6.519@newssvr16.news.prodigy.com>... > Matt, > > This may be due to a failure in finding the Quartus Web Edition License. > If you open Quartus and open the Tools->License Setup, it should say that > you have a Quartus Web Edition License. If you do not see this, the > compilation failure is due to the inability to find the license. No, that's not it. Quartus finds the license just fine. It doesn't pop up one of those "no license found" dialogs. Plugging my machine into the network doesn't help. > Typically this is seen if you have a license tied to the NICID, and you are > not connected to the network. Please make sure that you are connected to the > network when you invoke Quartus. WindowsXP and Windows2000 have the side > effect of hiding the NICID from the application if you are not connected to > the network. Yeah. Since I have 2 network cards, nothing in that appnote on licensing works. So I just applied for a license for the ffffffff0000 MAC which is what gets reported to the software. It seems to work. How stupid is it to tie free software to a specific nic card? I've applied for and gotten 6+ licenses. There's no limit, so what does it accomplish? All it does is piss your users off. > You can find more information in the app note > http://www.altera.com/literature/an/an229.pdf pgs's 14-20 on this topic. > Hope this helps. That's the appnote that tech support keeps pointing me to. But it doesn't help. I would like to be able to bring my laptop over to Altera (which is down the street from me), and have somebody figure this out. I've gotten emails from a bunch of people who were having the same problems as me, and who gave up on Altera tools (and parts too). Matt > > - Subroto Datta > Altera Corp. > > "Matt Ettus" <matt@ettus.com> wrote in message > news:e8fd79ea.0304121251.2fe07403@posting.google.com... > > I have a laptop running Windows XP Personal. For some reason, > > Altera's Quartus II Free web version does not run properly. Whenever > > I try to compile something, I get the message: > > > > Design test_proj: Full compilation was unsuccessful. 1 error, 0 > > warnings. > > > > There is no more info. The error message is not clickable. Altera's > > online tech support has been unable to help beyond pointing me to > > appnotes that don't apply. > > > > I don't think the problem is me, because I was able to get the tools > > to install on another machine. Unfortunately, that was not my > > machine. My only windows machine is this laptop. > > > > Is there anyone who can help? If you're in the bay area, I'd trade > > you a nice lunch for getting this to work on my machine. > > > > Thanks > > MattArticle: 54538
Not sure how I can check that. I am using WinXP personal which doesn't have an administrator, to my knowledge. Thanks Matt "cfk" <cfk_alter_ego@pacbell.net> wrote in message news:<xx%la.643$rs4.412@newssvr16.news.prodigy.com>... > Dear Matt: > Usually when something like this happens to me, its a file permission > thing. windowsXP, like NT has users/groups with file permissions. You may be > up agin either the fact that you did not install the software as > administrator (or local administrator) and windows is thwarting your efforts > to write files into certain directories. Or, you have a read-only attribute > on a file that Quartus needs to write to. I would study the settings on your > computer relating to users and groups and also ensure you have write > permission to all of the pertinent files in your Quartus installation. > > CharlesArticle: 54539
Dear Matt:
In XP, under Start->Settings->Control Panel you will find an number of
interesting proglets. One of these is User Accounts which controls the file
permissions of the administrator and other users/groups defined for your XP
system. There are a number of interesting books on XP, one is "Windows XP
Inside OUT" by Ed Bott from Microsoft Press. It is available from
amazon.com. I am sure there are others, perhaps obtaining one will help
you.
Charles
"Matt Ettus" <matt@ettus.com> wrote in message
news:e8fd79ea.0304130956.3da9f0c4@posting.google.com...
> Not sure how I can check that. I am using WinXP personal which
> doesn't have an administrator, to my knowledge.
>
> Thanks
> Matt
>
> "cfk" <cfk_alter_ego@pacbell.net> wrote in message
news:<xx%la.643$rs4.412@newssvr16.news.prodigy.com>...
> > Dear Matt:
> > Usually when something like this happens to me, its a file
permission
> > thing. windowsXP, like NT has users/groups with file permissions. You
may be
> > up agin either the fact that you did not install the software as
> > administrator (or local administrator) and windows is thwarting your
efforts
> > to write files into certain directories. Or, you have a read-only
attribute
> > on a file that Quartus needs to write to. I would study the settings on
your
> > computer relating to users and groups and also ensure you have write
> > permission to all of the pertinent files in your Quartus installation.
> >
> > Charles
Article: 54540I had exactly the same problem. After I setting the PC time correctly that probelm has gone. To set time double click time display on the right-bottom corner. You can set a user account as administrator using a utility 'User Account' in control pannel. Seung matt@ettus.com (Matt Ettus) wrote in message news:<e8fd79ea.0304130956.3da9f0c4@posting.google.com>... > Not sure how I can check that. I am using WinXP personal which > doesn't have an administrator, to my knowledge. > > Thanks > Matt > > "cfk" <cfk_alter_ego@pacbell.net> wrote in message news:<xx%la.643$rs4.412@newssvr16.news.prodigy.com>... > > Dear Matt: > > Usually when something like this happens to me, its a file permission > > thing. windowsXP, like NT has users/groups with file permissions. You may be > > up agin either the fact that you did not install the software as > > administrator (or local administrator) and windows is thwarting your efforts > > to write files into certain directories. Or, you have a read-only attribute > > on a file that Quartus needs to write to. I would study the settings on your > > computer relating to users and groups and also ensure you have write > > permission to all of the pertinent files in your Quartus installation. > > > > CharlesArticle: 54541
Matt,
The problem of detecting the correct NIC card, when multiple cards are
present has been fixed in Quartus II 3.0, to be released end of June. Based
on user feedback Altera has made changes to licensing in Quartus II 3.0, to
allow licenses not to be tied to a NIC card. Feel free to contact me, if
you need additional information.
- Subroto Datta
Altera Corp
"Matt Ettus" <matt@ettus.com> wrote in message
news:e8fd79ea.0304130955.2b1efb15@posting.google.com...
> "Subroto Datta" <sdatta@altera.com> wrote in message
news:<qF4ma.762$HM6.519@newssvr16.news.prodigy.com>...
> > Matt,
> >
> > This may be due to a failure in finding the Quartus Web Edition
License.
> > If you open Quartus and open the Tools->License Setup, it should say
that
> > you have a Quartus Web Edition License. If you do not see this, the
> > compilation failure is due to the inability to find the license.
>
> No, that's not it. Quartus finds the license just fine. It doesn't
> pop up one of those "no license found" dialogs. Plugging my machine
> into the network doesn't help.
>
> > Typically this is seen if you have a license tied to the NICID, and you
are
> > not connected to the network. Please make sure that you are connected to
the
> > network when you invoke Quartus. WindowsXP and Windows2000 have the side
> > effect of hiding the NICID from the application if you are not connected
to
> > the network.
>
> Yeah. Since I have 2 network cards, nothing in that appnote on
> licensing works. So I just applied for a license for the ffffffff0000
> MAC which is what gets reported to the software. It seems to work.
>
>
> How stupid is it to tie free software to a specific nic card? I've
> applied for and gotten 6+ licenses. There's no limit, so what does it
> accomplish? All it does is piss your users off.
>
> > You can find more information in the app note
> > http://www.altera.com/literature/an/an229.pdf pgs's 14-20 on this topic.
> > Hope this helps.
>
> That's the appnote that tech support keeps pointing me to. But it
> doesn't help.
>
> I would like to be able to bring my laptop over to Altera (which is
> down the street from me), and have somebody figure this out. I've
> gotten emails from a bunch of people who were having the same problems
> as me, and who gave up on Altera tools (and parts too).
>
> Matt
>
> >
> > - Subroto Datta
> > Altera Corp.
> >
> > "Matt Ettus" <matt@ettus.com> wrote in message
> > news:e8fd79ea.0304121251.2fe07403@posting.google.com...
> > > I have a laptop running Windows XP Personal. For some reason,
> > > Altera's Quartus II Free web version does not run properly. Whenever
> > > I try to compile something, I get the message:
> > >
> > > Design test_proj: Full compilation was unsuccessful. 1 error, 0
> > > warnings.
> > >
> > > There is no more info. The error message is not clickable. Altera's
> > > online tech support has been unable to help beyond pointing me to
> > > appnotes that don't apply.
> > >
> > > I don't think the problem is me, because I was able to get the tools
> > > to install on another machine. Unfortunately, that was not my
> > > machine. My only windows machine is this laptop.
> > >
> > > Is there anyone who can help? If you're in the bay area, I'd trade
> > > you a nice lunch for getting this to work on my machine.
> > >
> > > Thanks
> > > Matt
Article: 54542Ray Andraka <ray@andraka.com> wrote in message news:<3E99A0E9.95868F7B@andraka.com>... > Wallace tree multipliers only make sense where fast adders cost more than minimum area adders. For FPGAs with built in > fast carry logic, this is not the case. I have a more detailed discussion on this on the multipliers page on my website. > Yes ofcourse, from FPGA pt of view it would be Booth based and ripple adder based. However the post did go to other NGs where FPGAs are not relevant, and the last time I built an ASIC MAC, the multiplier was definitely a Wallace design. Since it was back in the 0.8u days the adder delays were dominant over wires by a long shot. In a previous Wallace design I even had to do the wiring and cell placement by hand in 1 layer of metal plus poly & dif, those were the days. These days 0.18u and less, with interconnects being very slow relative to cell delays, I am not so sure Wallace would beat Booth anymore unless I sat down & redid it both ways. Then again if Xilinx had no fast carry path in CLB, the same situation might arise there. In the end to mr Booth.multiplier, I think the ASIC guys already know what they are doing and there is likely to be more impact from circuit layout related decisions than any tweaking of the Booth algorithm. JohnArticle: 54543
"Svjatoslav Lisin" <netbreaker666@mail.ru> wrote in message news:<b7bh5l$b1t$1@news.wplus.spb.ru>... > Does somebody know any ready hardware systems for raytracing acceleration ? > How much can it cost? Doesn't nVidia, ATI, etc have this problem licked to death. Buy the latest nVidia card for PC, and that should do several orders better than anything else you could build yourself. JJArticle: 54544
john jakson wrote: > > "Svjatoslav Lisin" <netbreaker666@mail.ru> wrote in message news:<b7bh5l$b1t$1@news.wplus.spb.ru>... > > Does somebody know any ready hardware systems for raytracing acceleration ? > > How much can it cost? > > Doesn't nVidia, ATI, etc have this problem licked to death. Buy the > latest nVidia card for PC, and that should do several orders better > than anything else you could build yourself. Video cards don't support hardware acceleration for raytracing. OpenGL, movies and simple shading of polygons, yes, raytracing no. -- Ken TylerArticle: 54545
Ken wrote: > > john jakson wrote: > >>"Svjatoslav Lisin" <netbreaker666@mail.ru> wrote in message news:<b7bh5l$b1t$1@news.wplus.spb.ru>... >> >>>Does somebody know any ready hardware systems for raytracing acceleration ? >>>How much can it cost? >> >>Doesn't nVidia, ATI, etc have this problem licked to death. Buy the >>latest nVidia card for PC, and that should do several orders better >>than anything else you could build yourself. > > > Video cards don't support hardware acceleration for raytracing. OpenGL, > movies and simple shading of polygons, yes, raytracing no. > I'm not really aware of the specifics of the newer cards, but if you were willing to get your hands dirty, I bet you could convince a Geforce 3+ to do some work for you in pre-processing/animation work. (I'm referring to the vertex pipeline/transformation instructions.) It's probably not worth it, though. JasonArticle: 54546
How can I manage a complex design with many files that use components and packages from different files ? (Consider that the same package may be used by different files at the different level of hierarchy) Thanks for the help, Andrea "Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio news:jGUla.1187$j34.90@newssvr19.news.prodigy.com... > Andrea, > > At present the command to generate symbols for entities in a file, expects > that the VHDL file does not refer any other source files. Therefore you are > not doing anything wrong, when these errors are seen. If you cut the package > and paste it into the logic vhdl file, then it creates a symbol for the > block without any problem. This issue will be resolved in a future version > of the software. > > - Subroto Datta > Altera Corp. > > > "AP" <nospam@nospam.com> wrote in message > news:b78j1s$5id$1@lacerta.tiscalinet.it... > > "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> ha scritto nel messaggio > > news:d2Ela.721$KF1.80637@amstwist00... > > > Hi Andrea, > > > > > > > I'm new to Quartus II, and I'm tring to compile a simple test design. > > > > I have 2 vhd source files: aaa_pkg.vhd and aaa.vhd. > > > > The first contains a package declaration and body, the second use > > function > > > > defined inside aaa_pkg via the use clause : > > > > library my_lib; > > > > use my_lib.aaa_pkg.all; > > > > > > > > When I compile the design Quartus II give me error like this: > > > > "VHDL Use Clause error at aaa.vhd(13): design library my_lib does > > not > > > > contain primary unit aaa_pkg" > > > > > > > > How can I create my own libraries, and how can Quartus II see them ? > > > > > > Assuming that you're using version 2.2 (the versions before that have a > > > different menu structure) do the following: > > > > > > From the Project menu, select "Add/remove files in project" and add both > > > files. Then make sure that aaa_pkg.vhd is the topmost one. You can do > this > > > by selecting aaa_pkg.vhd in the list and then hitting the 'Up' button a > > few > > > times. > > > > > > If that doesn't work, just give another shout. > > > > > > Best regards, > > > > > > > > > Ben > > > > > > > > > > > > > > > > Hi Ben, > > > > I tried your suggestions but I cannot solve all my problems. > > The situation is the following (with Quartus II v2.2): > > > > * aaa.vhd is inside Quartus II project directory. > > * aaa_pkg.vhd is inside my_lib directory under project directory. > > > > I can do 'start analysis and synthesis' with success but I cannot create > > symbol from aaa.vhd file. > > The first error message I get is: > > "VHDL Use Clause error at aaa.vhd(13): design library my_lib does not > > contain primary unit aaa_pkg" > > Also the command 'Analyze current file' on aaa.vhd gives me the same > error. > > > > I cannot solve the problem of define and use a library for packages and > > components. > > > > Thanks in advance, > > Andrea > > > > > >Article: 54547
Hi,
1) I tried synthesizing a VHDL code consisting of components that
does multiplication.But the synthesizing took a longer time to
complete. I modified the same code by replacing the components for
multiplication by the standard library function ( NUMERIC_STD '*' for
multiplication) .I find that the latter synthesizes very soon.Why is
it so? I have placed the code for reference
2) Is there any way that i can include my components in to a
package so that the code synthesizes very quickly.
Bye
Prasanth
**********************************************************
VHDL CODE
*********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity vmul is
port(
n0 :in std_logic_vector(3 downto 0);
n1 :in std_logic_vector(3 downto 0);
n2 :in std_logic_vector(3 downto 0);
n3 :in std_logic_vector(3 downto 0);
n4 :in std_logic_vector(3 downto 0);
n5 :in std_logic_vector(3 downto 0);
n6 :in std_logic_vector(3 downto 0);
n7 :in std_logic_vector(3 downto 0);
n8 :in std_logic_vector(3 downto 0);
n9 :in std_logic_vector(3 downto 0);
m0 :in std_logic_vector(3 downto 0);
m1 :in std_logic_vector(3 downto 0);
m2 :in std_logic_vector(3 downto 0);
m3 :in std_logic_vector(3 downto 0);
m4 :in std_logic_vector(3 downto 0);
m5 :in std_logic_vector(3 downto 0);
m6 :in std_logic_vector(3 downto 0);
m7 :in std_logic_vector(3 downto 0);
m8 :in std_logic_vector(3 downto 0);
m9 :in std_logic_vector(3 downto 0);
o1 :out std_logic_vector(79 downto 0)
);
end vmul;
architecture behav_vmul of vmul is
component mul port(
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : buffer STD_LOGIC_VECTOR (7 downto 0)
);
end component;
signal b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16,b17,b18,b19,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t16,t17,t18,t19,t20:std_logic_vector(7
downto 0);
signal t12,t13,t14,t15:std_logic_vector(7 downto 0);
signal o6t:std_logic_vector(7 downto 0);
signal q1,q2,q3,q4,q5,q6:std_logic_vector(7 downto 0);
signal w1,w2,w3,w4,w5,w6,w7:std_logic_vector(7 downto 0);
signal e1,e2,e3,e4,e5,e6,e7,e8:std_logic_vector(7 downto 0);
signal d0,d1,d2,d3,d4,d5,d6,d7,d8:std_logic_vector(7 downto 0);
signal z0,z1,z2,z3,z4,z5,z6,z7,z8,z9:std_logic_vector(7 downto 0);
signal c1,c2,c3,c4,c5,c6,c7,c8,c9:std_logic_vector(7 downto 0);
signal v2,v3,v4,v5,v6,v7,v8,v9:std_logic_vector(7 downto 0);
signal s2,s3,s4,s5,s6,s7,s8:std_logic_vector(7 downto 0);
signal y3,y4,y5,y6,y7,y8:std_logic_vector(7 downto 0);
signal f4,f5,f6,f7,f8:std_logic_vector(7 downto 0);
signal g5,g6,g7,g8:std_logic_vector(7 downto 0);
signal h6,h7,h8:std_logic_vector(7 downto 0);
signal k7,k8,l8:std_logic_vector(7 downto 0);
signal px0,px1,px2,px3,px4,px5,px6,px7,px8,px9,px10,px11,px12,px13,px14,px15:std_logic_vector(7
downto 0);
begin
v10:mul port map(m0(3 downto 0),n0(3 downto 0),t1);
v12:mul port map(m0(3 downto 0),n1(3 downto 0),t2);
v13:mul port map(m1(3 downto 0),n0(3 downto 0),t3);
v17:mul port map(m0(3 downto 0),n2(3 downto 0),t6);
v18:mul port map(m1(3 downto 0),n1(3 downto 0),t7);
v110:mul port map(m2(3 downto 0),n0(3 downto 0),t9);
v114:mul port map(m0(3 downto 0),n3(3 downto 0),t12);
v115:mul port map(m1(3 downto 0),n2(3 downto 0),t13);
v116:mul port map(m2(3 downto 0),n1(3 downto 0),t14);
v117:mul port map(m3(3 downto 0),n0(3 downto 0),t15);
a1:mul port map(m0(3 downto 0),n4(3 downto 0),t16);
a2:mul port map(m1(3 downto 0),n3(3 downto 0),t17);
a3:mul port map(m2(3 downto 0),n2(3 downto 0),t18);
a4:mul port map(m3(3 downto 0),n1(3 downto 0),t19);
a5:mul port map(m4(3 downto 0),n0(3 downto 0),t20);
a6:mul port map(m0(3 downto 0),n5(3 downto 0),q1);
a7:mul port map(m1(3 downto 0),n4(3 downto 0),q2);
a8:mul port map(m2(3 downto 0),n3(3 downto 0),q3);
a9:mul port map(m3(3 downto 0),n2(3 downto 0),q4);
a10:mu1 port map(m4(3 downto 0),n1(3 downto 0),q5);
a11:mu1 port map(m5(3 downto 0),n0(3 downto 0),q6);
a12:mul port map(m0(3 downto 0),n6(3 downto 0),w1);
a13:mul port map(m1(3 downto 0),n5(3 downto 0),w2);
a14:mul port map(m2(3 downto 0),n4(3 downto 0),w3);
a15:mul port map(m3(3 downto 0),n3(3 downto 0),w4);
a16:mul port map(m4(3 downto 0),n2(3 downto 0),w5);
a17:mul port map(m5(3 downto 0),n1(3 downto 0),w6);
a18:mul port map(m6(3 downto 0),n0(3 downto 0),w7);
bo1:mul port map(m0(3 downto 0),n7(3 downto 0),e1);
bo2:mul port map(m1(3 downto 0),n6(3 downto 0),e2);
bo3:mul port map(m2(3 downto 0),n5(3 downto 0),e3);
bo4:mul port map(m3(3 downto 0),n4(3 downto 0),e4);
bo5:mul port map(m4(3 downto 0),n3(3 downto 0),e5);
bo6:mul port map(m5(3 downto 0),n2(3 downto 0),e6);
bo7:mul port map(m6(3 downto 0),n1(3 downto 0),e7);
bo7a:mul port map(m7(3 downto 0),n0(3 downto 0),e8);
bo8 :mul port map(m0(3 downto 0),n8(3 downto 0),d8);
bo9 :mul port map(m1(3 downto 0),n7(3 downto 0),d0);
bo10:mul port map(m2(3 downto 0),n6(3 downto 0),d1);
bo11:mul port map(m3(3 downto 0),n5(3 downto 0),d2);
bo12:mul port map(m4(3 downto 0),n4(3 downto 0),d3);
bo13:mul port map(m5(3 downto 0),n3(3 downto 0),d4);
bo14:mul port map(m6(3 downto 0),n2(3 downto 0),d5);
bo15:mul port map(m7(3 downto 0),n1(3 downto 0),d6);
bo16:mul port map(m8(3 downto 0),n0(3 downto 0),d7);
u5:bintobcd port map( px5,o1(35 downto 32),b9);
z0<=m0*n9;
z9<=m1*n8;
z1<=m2*n7;
z2<=m3*n6;
z3<=m4*n5;
z4<=m5*n4;
z5<=m6*n3;
z6<=m7*n2;
z7<=m8*n1;
z8<=m9*n0;
-- x0:mul port map(m0(3 downto 0),n9(3 downto 0),z0);
-- x1:mul port map(m1(3 downto 0),n8(3 downto 0),z9);
-- x2:mul port map(m2(3 downto 0),n7(3 downto 0),z1);
-- x3:mul port map(m3(3 downto 0),n6(3 downto 0),z2);
-- x4:mul port map(m4(3 downto 0),n5(3 downto 0),z3);
-- x5:mul port map(m5(3 downto 0),n4(3 downto 0),z4);
-- x6:mul port map(m6(3 downto 0),n3(3 downto 0),z5);
-- x7:mul port map(m7(3 downto 0),n2(3 downto 0),z6);
-- x8:mul port map(m8(3 downto 0),n1(3 downto 0),z7);
-- x9:mul port map(m9(3 downto 0),n0(3 downto 0),z8);
c9<=m1*n9;
c1<=m2*n8;
c2<=m3*n7;
c3<=m4*n6;
c4<=m5*n5;
c5<=m6*n4;
c6<=m7*n3;
c7<=m8*n2;
c8<=m9*n1;
-- x10:mul port map(m1(3 downto 0),n9(3 downto 0),c9);
-- x20:mul port map(m2(3 downto 0),n8(3 downto 0),c1);
-- x30:mul port map(m3(3 downto 0),n7(3 downto 0),c2);
-- x40:mul port map(m4(3 downto 0),n6(3 downto 0),c3);
-- x50:mul port map(m5(3 downto 0),n5(3 downto 0),c4);
-- x60:mul port map(m6(3 downto 0),n4(3 downto 0),c5);
-- x70:mul port map(m7(3 downto 0),n3(3 downto 0),c6);
-- x80:mul port map(m8(3 downto 0),n2(3 downto 0),c7);
-- x90:mul port map(m9(3 downto 0),n1(3 downto 0),c8);
v9<=m2*n9;
v2<=m3*n8;
v3<=m4*n7;
v4<=m5*n6;
v5<=m6*n5;
v6<=m7*n4;
v7<=m8*n3;
v8<=m9*n2;
-- x21:mul port map(m2(3 downto 0),n9(3 downto 0),v9);
-- x31:mul port map(m3(3 downto 0),n8(3 downto 0),v2);
-- x41:mul port map(m4(3 downto 0),n7(3 downto 0),v3);
-- x51:mul port map(m5(3 downto 0),n6(3 downto 0),v4);
-- x61:mul port map(m6(3 downto 0),n5(3 downto 0),v5);
-- x71:mul port map(m7(3 downto 0),n4(3 downto 0),v6);
-- x81:mul port map(m8(3 downto 0),n3(3 downto 0),v7);
-- x91:mul port map(m9(3 downto 0),n2(3 downto 0),v8);
s2<=m3*n9;
s3<=m4*n8;
s4<=m5*n7;
s5<=m6*n6;
s6<=m7*n5;
s7<=m8*n4;
s8<=m9*n3;
-- x32:mul port map(m3(3 downto 0),n9(3 downto 0),s2);
-- x42:mul port map(m4(3 downto 0),n8(3 downto 0),s3);
--- x52:mul port map(m5(3 downto 0),n7(3 downto 0),s4);
-- x62:mul port map(m6(3 downto 0),n6(3 downto 0),s5);
-- x72:mul port map(m7(3 downto 0),n5(3 downto 0),s6);
-- x82:mul port map(m8(3 downto 0),n4(3 downto 0),s7);
-- x92:mul port map(m9(3 downto 0),n3(3 downto 0),s8);
y3<=m4*n9;
y4<=m5*n8;
y5<=m6*n7;
y6<=m7*n6;
y7<=m8*n5;
y8<=m9*n4;
-- x43:mul port map(m4(3 downto 0),n9(3 downto 0),y3);
-- x53:mul port map(m5(3 downto 0),n8(3 downto 0),y4);
-- x63:mul port map(m6(3 downto 0),n7(3 downto 0),y5);
-- x73:mul port map(m7(3 downto 0),n6(3 downto 0),y6);
-- x83:mul port map(m8(3 downto 0),n5(3 downto 0),y7);
-- x93:mul port map(m9(3 downto 0),n4(3 downto 0),y8);
f4<=m5*n9;
f5<=m6*n8;
f6<=m7*n7;
f7<=m8*n6;
f8<=m9*n5;
-- x54:mul port map(m5(3 downto 0),n9(3 downto 0),f4);
-- x64:mul port map(m6(3 downto 0),n8(3 downto 0),f5);
-- x74:mul port map(m7(3 downto 0),n7(3 downto 0),f6);
-- x84:mul port map(m8(3 downto 0),n6(3 downto 0),f7);
-- x94:mul port map(m9(3 downto 0),n5(3 downto 0),f8);
g5<=m6*n9;
g6<=m7*n8;
g7<=m8*n7;
g8<=m9*n6;
-- x65:mul port map(m6(3 downto 0),n9(3 downto 0),g5);
-- x75:mul port map(m7(3 downto 0),n8(3 downto 0),g6);
-- x85:mul port map(m8(3 downto 0),n7(3 downto 0),g7);
-- x95:mul port map(m9(3 downto 0),n6(3 downto 0),g8);
u12:bintobcd port map( px12,o1(63 downto 60),b16);
h6<=m7*n9;
h7<=m8*n8;
h8<=m9*n7;
-- x76:mul port map(m7(3 downto 0),n9(3 downto 0),h6);
-- x86:mul port map(m8(3 downto 0),n8(3 downto 0),h7);
-- x96:mul port map(m9(3 downto 0),n7(3 downto 0),h8);
k7<=m8*n9;
k8<=m9*n8;
-- x87:mul port map(m8(3 downto 0),n9(3 downto 0),k7);
-- x97:mul port map(m9(3 downto 0),n8(3 downto 0),k8);
l8<=m9*n9;
-- x98:mul port map(m9(3 downto 0),n9(3 downto 0),l8);
u15:bintobcd port map(px15,o1(75 downto 72),b19);
o1(79 downto 76)<= b19(3 downto 0);
p:process(t15)
begin
px0 <= (t12+t13)+(t14+t15)+b3;
end process;
p0:process(t20 )
begin
px1<=(t16+t17)+(t18+t19)+(t20+b4);
end process p0;
p1:process(q6)
begin
px2<=(q1+q2)+(q3+q4)+(q5+q6)+b5;
end process p1;
p2:process(w6)
begin
px3<=(w1+w2)+(w3+w4)+(w5+w6)+(b6+w7);
end process p2;
p3:process(e8)
begin
px4<=(e1+e2)+(e3+e4)+(e5+e6)+(e7+e8)+b7;
end process p3;
p4:process(d8)
begin
px5<=(d1+d2)+(d3+d4)+(d5+d6)+(d7+d8)+(b8+d0);
end process p4;
p5:process(z9)
begin
px6<= (z0+z1)+(z2+z3)+(z4+z5)+(z6+z7)+(z8+z9)+b9;
end process p5;
p6:process(c9)
begin
px7<= (b10+c1)+(c2+c3)+(c4+c5)+(c6+c7)+(c8+c9);
end process p6;
p7:process(v9)
begin
px8<= (b11)+(v2+v3)+(v4+v5)+(v6+v7)+(v8+v9);
end process p7;
p8:process(s8)
begin
px9<= (s2+s3)+(s4+s5)+(s6+s7)+(s8+b12);
end process p8;
p9:process(y8)
begin
px10<= (y3+y4)+(y5+y6)+(y7+y8)+b13;
end process p9;
p10:process(f8)
begin
px11<= (f4+f5)+(f6+f7)+(f8+b14);
end process p10;
p11:process(g8)
begin
px12<= (g5)+(g6+g7)+(g8+b15);
end process p11;
p12:process(h8)
begin
px13 <= (h6+h7)+(h8+b16);
end process p12;
p13:process(k8)
begin
px14 <= (k7)+(k8+b17);
end process p13;
p14:process(l8)
begin
px15 <= (l8+b18);
end process p14;
end behav_vmul;
Article: 54548Hi, I'm wondering if someone has managed to get the esential parts of Xilinx's ISE WebPack 5.2i to run under WINE (or some other form of Win32 emulation) under a Linux host and would be willing to provide advice/tips on doing it. A web search seems to suggest people have had success (there is even some documentation on Xilinx's own website) and my initial attempts looks promising... I think i've almost achieved my goal, however I'm increasingly getting stuck. I'm not particulary interested in the GUI related components (although having as much of them as possible would be a benifit I suppose). I'd be happly content with utilsing the command line applications directly, and that's one of my problems... I don't even know where to start using them. I've just recently started (i.e. a few months ago) using FPGAs and have mainly used the GUI tools up until now, and relied upon them calling the command line orientated ones. For example using the tools in ISE WebPack, how would I go about getting a VHDL file (say "XYZ.vhdl") synthesied and end up with an image ready for use on say an Xilinx Spartan-II XC2S50. Thanks, Christopher Fairbairn.Article: 54549
Hi (Xilinx ISE 5.2) I try to simulate one design, but I receive this message: ERROR: Hidden remap failed Reason: Reason field is empty :) When I simulate Post-Translate VHDL Model Everything is OK. What could be wrong? Jerzy Gbur
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