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Lis, With Quartus II 2.2 the basic alias command and partial assignment to aliases are fully supported. The only limitation that we are aware of is: This kind of alias declaration causes an error: signal count : unsigned(5 downto 0); alias test is count (5 downto 3); -- This is where the error happens The error message is: "non-object alias is not supported" If the alias declaration is replaced by "alias test : unsigned(5 downto 3) is count(5 downto 3)", it reads in OK. - Subroto Datta Altera Corporation lishu99@yahoo.com (Lis Hu) wrote in message news:<4faf3f56.0304090615.1f01fdea@posting.google.com>... > Subroto, > I've had trouble with the alias construct in VHDL. > > --Lis > "Subroto Datta" <sdatta@altera.com> wrote in message news:<arLka.3748$UP3.2161@newssvr19.news.prodigy.com>... > > Lis, > > > > Quartus II 2.2 has very good language coverage for both synthesizable > > VHDL and Verilog. Please feel free to email me any questions about language > > constructs, and we can verify if there will be a problem or not. > > > > - Subroto Datta > > Altera Corp.Article: 54501
Why do you think that you cannot use a clock doubler? At your low frequency, this should be no problem whatsoever, even if the clock sometimes is parked High or Low. Click on http://support.xilinx.com/support/techxclusives/6easy-techX37.htm and use at Easy Piece #4. Peter Alfke ============== CC Nguyen wrote: > > Hi all, > I know this is an old topic, but now I facing it. > I want to implement a double edge triggered flipflop in Virtex. > There's another factor : the clock signal is bursting (sometime it > totally flat, some time running), so I can't use the "clock double" > trick. > > Any suggestion is apreciated,Article: 54503
rickman <spamgoeshere4@yahoo.com> writes: > So why do you care? Because if you are bandwidth chalenged like I am, I > will make you a copy and mail it to you for $5. Xilinx will mail you a free copy of WebPACK 5.2i for $6.92 shipping and handling (in the US), and it also includes a 60-day evaluation copy of the full ISE 5.2i package. http://www.xilinx.com/xlnx/xebiz/product_detail_view3.jsp?category=-11100&prodKey=DS-ISE-WEBPACKArticle: 54504
boothmultipler@hotmail.com (booth multiplier) wrote in message news:<24160f43.0304111147.72b80b4d@posting.google.com>... > Dear All, > I have found a technique to reduce the area and the delay of Booth > Multipliers by %10. This technique can be applied on any multiplier > implementation which uses the Modified Booth Algorithm. > I wonder which companies could benefit from such an > improvement.Which companies would like to have it? > Can anybody help me to contact them? > > Thanks This is a much explored area and is thought to be completely understood. The Wallace structure is also well known and handily beats the Booth algorithm by larger & larger margins as the arrays get bigger. If anyone was really after speed, they would already be using Wallace despite its irregular structure. Wallace multiplication times can approach O(logN) times. Booth multiplication times generally follow O(N) times. Perhaps you should outline the idea and see if others will salute it, or perhaps you have reinvented one of the minor variations covered in many texts. I doubt that either Booth or Wallace recieved any fortune, but their names are immortalized here, perhaps yours will too.Article: 54505
>Why do you think that you cannot use a clock doubler? >At your low frequency, this should be no problem whatsoever, even if the >clock sometimes is parked High or Low. >Click on >http://support.xilinx.com/support/techxclusives/6easy-techX37.htm >and use at Easy Piece #4. That's a neat trick, but I'm surprised you didn't remind people that the new clock is delayed from the input clock so you have to think about clock skew issues if the input clock is used to clock any other logic, say on other chips. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 54506
> Using Parallel Cable III and Xilinx tool, it takes around 40 seconds + GUI > clikcking time to download a bit file for XC2V1000. > With Parallel Cable III and the board mentioned above, it takes less than > 4 seconds for everything. (TCKmax:1.57MHz) > > It could be faster. I have tried faster TCK clocking (> 3MHz) but the > downloading became unstable. > > I used Ethernet interface such that I can place the target far from the WS. > But you can do the same using different interface such as USB. > > It is not ready to release my design for now. But I may provide my design > including JTAG class library to the FPGA community in the future. Nice work! But do you think a roll-your-own USB cable might be even simpler? USB microcontrollers are awfully easy to come by now. One MCU + a few passives and it's done. -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54507
Eric Smith wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > So why do you care? Because if you are bandwidth chalenged like I am, I > > will make you a copy and mail it to you for $5. > > Xilinx will mail you a free copy of WebPACK 5.2i for $6.92 shipping and > handling (in the US), and it also includes a 60-day evaluation copy of the > full ISE 5.2i package. > > http://www.xilinx.com/xlnx/xebiz/product_detail_view3.jsp?category=-11100&prodKey=DS-ISE-WEBPACK Well, that is very interesting. They don't mention this at all on the Webpack product page. Seems it would be logical to tell you there that you don't have to download it, you can just buy a CD. In the past when I asked about this, I was always told that they didn't want to bother with providing CDs. Now they give them out, they just don't bother to tell you about this on the product page. Thanks for the info... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54508
"Makoto Honda" <honda@ipflex.com> wrote in message news:<b75p2v$j7j$1@nn-tk103.ocn.ad.jp>... > Please see our web at > http://www.ipflex.com/english/1_index.html . > > Makoto Honda > IP Flex Incorporated > > "Jihan Zhu" <jihan@itee.uq.edu.au> wrote in message > news:b757me$m2n$1@bunyip.cc.uq.edu.au... > > > > Hello, > > > > > > Quite an interesting website for those interested in RC, although I could not quite get past the DAP/DNA architecture.Article: 54509
rickman wrote: > > Eric Smith wrote: > > > > rickman <spamgoeshere4@yahoo.com> writes: > > > So why do you care? Because if you are bandwidth chalenged like I am, I > > > will make you a copy and mail it to you for $5. > > > > Xilinx will mail you a free copy of WebPACK 5.2i for $6.92 shipping and > > handling (in the US), and it also includes a 60-day evaluation copy of the > > full ISE 5.2i package. > > > > http://www.xilinx.com/xlnx/xebiz/product_detail_view3.jsp?category=-11100&prodKey=DS-ISE-WEBPACK > > Well, that is very interesting. They don't mention this at all on the > Webpack product page. Seems it would be logical to tell you there that > you don't have to download it, you can just buy a CD. In the past when > I asked about this, I was always told that they didn't want to bother > with providing CDs. Now they give them out, they just don't bother to > tell you about this on the product page. > > Thanks for the info... Now I *really* feel dumb. On the page where you actually select the files you want to download they have a link "Order ISE WebPACK CD" in a list to the right. Still, it would be nice if they made it a bit more obvious. Anyway, I should have my set of CDs next week. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54510
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> ha scritto nel messaggio
news:d2Ela.721$KF1.80637@amstwist00...
> Hi Andrea,
>
> > I'm new to Quartus II, and I'm tring to compile a simple test design.
> > I have 2 vhd source files: aaa_pkg.vhd and aaa.vhd.
> > The first contains a package declaration and body, the second use
function
> > defined inside aaa_pkg via the use clause :
> > library my_lib;
> > use my_lib.aaa_pkg.all;
> >
> > When I compile the design Quartus II give me error like this:
> > "VHDL Use Clause error at aaa.vhd(13): design library my_lib does
not
> > contain primary unit aaa_pkg"
> >
> > How can I create my own libraries, and how can Quartus II see them ?
>
> Assuming that you're using version 2.2 (the versions before that have a
> different menu structure) do the following:
>
> From the Project menu, select "Add/remove files in project" and add both
> files. Then make sure that aaa_pkg.vhd is the topmost one. You can do this
> by selecting aaa_pkg.vhd in the list and then hitting the 'Up' button a
few
> times.
>
> If that doesn't work, just give another shout.
>
> Best regards,
>
>
> Ben
>
>
Hi Ben,
I tried your suggestions but I cannot solve all my problems.
The situation is the following (with Quartus II v2.2):
* aaa.vhd is inside Quartus II project directory.
* aaa_pkg.vhd is inside my_lib directory under project directory.
I can do 'start analysis and synthesis' with success but I cannot create
symbol from aaa.vhd file.
The first error message I get is:
"VHDL Use Clause error at aaa.vhd(13): design library my_lib does not
contain primary unit aaa_pkg"
Also the command 'Analyze current file' on aaa.vhd gives me the same error.
I cannot solve the problem of define and use a library for packages and
components.
Thanks in advance,
Andrea
Article: 54511I need a PLD, 32 macrocells or fewer, about 20 IO pins, with very fast pin to pin delay, maximum 3 nS, 5 Vcc or less, TTL compliant. Who does this kind of devices? Thank you in advance.Article: 54512
Andrea, At present the command to generate symbols for entities in a file, expects that the VHDL file does not refer any other source files. Therefore you are not doing anything wrong, when these errors are seen. If you cut the package and paste it into the logic vhdl file, then it creates a symbol for the block without any problem. This issue will be resolved in a future version of the software. - Subroto Datta Altera Corp. "AP" <nospam@nospam.com> wrote in message news:b78j1s$5id$1@lacerta.tiscalinet.it... > "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> ha scritto nel messaggio > news:d2Ela.721$KF1.80637@amstwist00... > > Hi Andrea, > > > > > I'm new to Quartus II, and I'm tring to compile a simple test design. > > > I have 2 vhd source files: aaa_pkg.vhd and aaa.vhd. > > > The first contains a package declaration and body, the second use > function > > > defined inside aaa_pkg via the use clause : > > > library my_lib; > > > use my_lib.aaa_pkg.all; > > > > > > When I compile the design Quartus II give me error like this: > > > "VHDL Use Clause error at aaa.vhd(13): design library my_lib does > not > > > contain primary unit aaa_pkg" > > > > > > How can I create my own libraries, and how can Quartus II see them ? > > > > Assuming that you're using version 2.2 (the versions before that have a > > different menu structure) do the following: > > > > From the Project menu, select "Add/remove files in project" and add both > > files. Then make sure that aaa_pkg.vhd is the topmost one. You can do this > > by selecting aaa_pkg.vhd in the list and then hitting the 'Up' button a > few > > times. > > > > If that doesn't work, just give another shout. > > > > Best regards, > > > > > > Ben > > > > > > > > > Hi Ben, > > I tried your suggestions but I cannot solve all my problems. > The situation is the following (with Quartus II v2.2): > > * aaa.vhd is inside Quartus II project directory. > * aaa_pkg.vhd is inside my_lib directory under project directory. > > I can do 'start analysis and synthesis' with success but I cannot create > symbol from aaa.vhd file. > The first error message I get is: > "VHDL Use Clause error at aaa.vhd(13): design library my_lib does not > contain primary unit aaa_pkg" > Also the command 'Analyze current file' on aaa.vhd gives me the same error. > > I cannot solve the problem of define and use a library for packages and > components. > > Thanks in advance, > Andrea > >Article: 54513
On Fri, 11 Apr 2003 20:27:37 -0700, Garrett Mace wrote: >> Using Parallel Cable III and Xilinx tool, it takes around 40 seconds + >> GUI clikcking time to download a bit file for XC2V1000. With Parallel >> Cable III and the board mentioned above, it takes less than 4 seconds >> for everything. (TCKmax:1.57MHz) >> >> It could be faster. I have tried faster TCK clocking (> 3MHz) but the >> downloading became unstable. >> >> I used Ethernet interface such that I can place the target far from the > WS. >> But you can do the same using different interface such as USB. >> >> It is not ready to release my design for now. But I may provide my >> design including JTAG class library to the FPGA community in the >> future. > > Nice work! But do you think a roll-your-own USB cable might be even > simpler? USB microcontrollers are awfully easy to come by now. One MCU + > a few passives and it's done. > Actually I'm designing such a card now, no microcontroller just a FTDI USB245B and a 9572XL. Card is USB powered, about 1x3" and should work with 2.5 -> 5V signal levels (9572XL is 5 volt tolerant and has its VCCIO switched from 3.3 to 2.5 if Jtag VIO < 2.8v). The card will support JTAG clock rates up to 12 MHz. I am thinking about using 4bit address/4bit data characters for setup (Shift rate, bit I/O) and data transfer (send only(4), send/recieve(4), receive(4), clk(N) ) The 9572 can be programmed through the USB interface using the 245B's bit banging mode. I can make PCBs available for a nominal charge if there is any interest Still messing with ideas so any suggestions are welcome... PCW > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54514
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3E971AD0.B4B91C1A@yahoo.com... > The full installation for Webpack 5.2i is about 200 MB. I have tried to > download this in the past and it can be a real PITA over a modem link. > The phone lines here won't support over 28.8kbps which gives it a > download time of 21 hours. Try getting a download to run continuously > for that long without crapping out. > > Since I couldn't get a CD from Insight anymore, I started looking for > places to get high speed access for a couple of hours. Some of the > local for hire facilities did not do what I needed, so I went to the > library. They had the highest download rates I have seen *anywhere*! > After two hours I not only downloaded the Webpack 5.2i full install, but > every one of the other files on that page. It all just fit on a CD. Haven't been to a library in years. Do their computers actually have CD burners in them these days? By the way, I was able to download WebPack in just a few minutes. My cable modem company says to expect at best 700Kbps download, but I regularly get 2-3Mbps if the comm path and the server on the other end can handle it. I ain't complaining.Article: 54515
Leon Heller wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3E9795E9.BC50A161@yahoo.com... > > rickman wrote: > > > Thanks for the info... > > > > Now I *really* feel dumb. On the page where you actually select the > > files you want to download they have a link "Order ISE WebPACK CD" in a > > list to the right. Still, it would be nice if they made it a bit more > > obvious. Anyway, I should have my set of CDs next week. > > > > Interesting 'error'. I've just had a bit of an argument with someone about > web page design and putting stuff like that on the right. I'm quite sure > that there is a user stereotype here, with users expecting links and options > on the left. Actually, I would have expected it on an earlier page. But the time I was at this page, I had looked at a full page of info on Webpack and clicked a button that said "Download ISE Webpack" to get to this page. Buying a CD isn't really what you would expect from "Download ISE Webpack", now is it? I was also prejudiced by the fact that with previous releases I had asked about getting CDs and was told it was too much bother for Xilinx. I would have expected them to post it more noticeably than just a line in a sidebar regardless of which side. But hey, the good news is that they are now selling the CDs. So for $7 I can keep current with the latest release. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54516
Look at DSP Builder for Altera FPGA. It links the Stratix DSP Board and Nios Processor to the Simulink environment. http://www.altera.com/products/devkits/altera/kit-dsp_stratix.html http://www.altera.com/products/software/system/products/dsp/dsp-builder.html Charles Nabeel Shirazi <nabeel.shirazi@xilinx.com> wrote in message news:<3E7775E8.BD802085@xilinx.com>... > Hello, > > Xilinx has just released a new version of System Generator for DSP which can > perform HDL and Hardware Co-Simulation with Simulink. > > You can find out more about it at: > http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=system_generator > > Regards, > Nabeel ShiraziArticle: 54517
ACTEL eX ... "Valeria Dal Monte" <aaa@bbb.it> сообщил/сообщила в новостях следующее: news:hzRla.30392$iy5.868284@twister2.libero.it... > I need a PLD, 32 macrocells or fewer, about 20 IO pins, with very fast > pin to pin delay, maximum 3 nS, 5 Vcc or less, TTL compliant. > Who does this kind of devices? > Thank you in advance. > > >Article: 54518
> Hello, > > I have implemented an algorithm on a FPGA (Xilinx XC4010). Now the > problem is with the development board. Though it is convenient when it > comes to downloading the bit stream from the computer, the problem is > it is too bulky. The development board has additional LED, some more > ports etc which I dont need. The only things I need and use is the > FPGA, a parallel printer port for dumping information onto FPGA and > memory. Therefore, I want to transfer the FPGA onto a PCB alongwith > some memory (~10MB). The memory should be loadable from the computer > directly, otherwise the FPGA should be able to read the memory and > should be able to write to it. > > Since I am totally new to this area, I can only reckon a guess that I > would require a micro controller which gets programmed from flash > memory each time the device is activated, which will contain all the > handshaking protocols. But what components are there which can do this > job with least effort expended? Any ideas on this? Any pointers in > general to put me on a track would be appreciated.Article: 54519
"Valeria Dal Monte" <aaa@bbb.it> wrote in message news:<hzRla.30392$iy5.868284@twister2.libero.it>... > I need a PLD, 32 macrocells or fewer, about 20 IO pins, with very fast > pin to pin delay, maximum 3 nS, 5 Vcc or less, TTL compliant. > Who does this kind of devices? > Thank you in advance. Lattice Semiconductor: ispGAL and ispMACH 4000 (1.8V, 2.5V and 3.3V)Article: 54520
I have a laptop running Windows XP Personal. For some reason, Altera's Quartus II Free web version does not run properly. Whenever I try to compile something, I get the message: Design test_proj: Full compilation was unsuccessful. 1 error, 0 warnings. There is no more info. The error message is not clickable. Altera's online tech support has been unable to help beyond pointing me to appnotes that don't apply. I don't think the problem is me, because I was able to get the tools to install on another machine. Unfortunately, that was not my machine. My only windows machine is this laptop. Is there anyone who can help? If you're in the bay area, I'd trade you a nice lunch for getting this to work on my machine. Thanks MattArticle: 54521
Dear Matt:
Usually when something like this happens to me, its a file permission
thing. windowsXP, like NT has users/groups with file permissions. You may be
up agin either the fact that you did not install the software as
administrator (or local administrator) and windows is thwarting your efforts
to write files into certain directories. Or, you have a read-only attribute
on a file that Quartus needs to write to. I would study the settings on your
computer relating to users and groups and also ensure you have write
permission to all of the pertinent files in your Quartus installation.
Charles
"Matt Ettus" <matt@ettus.com> wrote in message
news:e8fd79ea.0304121251.2fe07403@posting.google.com...
> I have a laptop running Windows XP Personal. For some reason,
> Altera's Quartus II Free web version does not run properly. Whenever
> I try to compile something, I get the message:
>
> Design test_proj: Full compilation was unsuccessful. 1 error, 0
> warnings.
>
> There is no more info. The error message is not clickable. Altera's
> online tech support has been unable to help beyond pointing me to
> appnotes that don't apply.
>
> I don't think the problem is me, because I was able to get the tools
> to install on another machine. Unfortunately, that was not my
> machine. My only windows machine is this laptop.
>
> Is there anyone who can help? If you're in the bay area, I'd trade
> you a nice lunch for getting this to work on my machine.
>
> Thanks
> Matt
Article: 54522"Steve Casselman" <sc_nospam@vcc.com> wrote in message news:<QKCla.62$E6.7867568@newssvr13.news.prodigy.com>... > I guess no one is using the Hot2 on the SUN. The answer is yes! I have used > it on the SUN and it works! > > Steve > > "Sriram" <machosri@yahoo.com> wrote in message > news:56210527.0304071344.639ae2cf@posting.google.com... > > Hi , > > Has anybody in this group used Virtual Computing Corporation(VCC)'s > > HOT 2 board and development tools. > > Are there any issues I should look out for in interfacing their board > > to a SUN Solaris workstation through a PCI bus,or as they claim can I > > create Hardware Objects ,use them as function calls in C++ code and > > not worry about any problems with the interface part. > > > > Thanks, > > Sriram Hi Steve, thanks for replying.Can you give me a number so that I can call somebody at VCC,clarify my doubts and purchase the product too on the same day. Thanks, SriramArticle: 54523
In article <24160f43.0304111147.72b80b4d@posting.google.com>
boothmultipler@hotmail.com (booth multiplier) writes:
>Dear All,
> I have found a technique to reduce the area and the delay of Booth
>Multipliers by %10. This technique can be applied on any multiplier
>implementation which uses the Modified Booth Algorithm.
> I wonder which companies could benefit from such an
>improvement.Which companies would like to have it?
> Can anybody help me to contact them?
>
>Thanks
Are you trying to reduce your own area, booth?
Go on a weight-loss diet!
The 16th IEEE Symposium on Computer Arithmetic will be held
June 15-18, 2003 in Santiago de Compostela, Spain (north of Portugal).
There is a Monday morning session on multiplication.
You can talk with other attendees.
See conference details at http://www.dec.usc.es/arith16/index.html .
Peter Montgomery (Program Committee member)
--
What will be the 51st US state? (a) District of Columbia; (b) Guam;
(c) Canada; (d) Puerto Rico; (e) Bushlands of Iraq
Peter-Lawrence.Montgomery@cwi.nl Home: San Rafael, California
Microsoft Research and CWI
Article: 54524Thanks for the message last week, Eric - my newsreader at work isn't 100% and I had to read/respond at home. Your comment about only needing two flops is accurate as long as the designer can trust that the x1clk and x2clk domains will always work together as we'd expect where the rising edges are coincident. The reality is that those two edges may be separated by some 100s of ps since the clock net loading can be different between the two domains and input clock jitter to the DLL may translate to the two domains at different cycles. THe former problem is known, I'm only speculating on the latter. Bottom line: I can't depend on the two domains to play nice at the common rising edge, hense the nead to offset things by 1/4 the x1clk (or 1/2 th x2clk). Any further thoughts are appreciated. - John_H Eric Pearson wrote: > "John_H" <johnhandwork@mail.com> wrote in message > news:T9Hka.9$716.2363@news-west.eli.net... > >>Has anyone figured out a nice, clean method to track which phase of a > > Xilinx > >>DLL's 1x clock corresponds to a 2x clock cycle? One 2x rising edge >>corresponds to the 1x rising edge, the other 2x rising edge corresponds to >>the 1x falling edge. >> >>When I start getting up in frequencies, the ability to use the 1x clock > > and > >>inverted 1x clock to generate two signals that I can XOR for a phase is >>compromised. It's not inherently safe to use the 1x edges and 2x rising >>edges as "effectively" the same edge due to clock skews and input jitter >>issues. Using the falling edge of the 2x clock to sample the 1x generated >>signals works, but at the 1/4 period timing budget is too tight at the >>frequencies I'm working. >> >>For those who are Verilog friendly, the code here shows how I would >>"normally" extract the phase without running a clock through a LUT. The >>"negedge x2clk" is where the timing gets tough since the Tcko+Tnet+Tick is > > a > >>little over the 1/4 period of my x1clk. >> >>always @(posedge x1clk) posTog <= ~posTog; >>always @(negedge x1clk) negTog <= posTog; >>always @(negedge x2clk) rawPhase <= posTog ^ negTog; >>always @(posedge x2clk) phase <= rawPhase; >> >>Is there a cleaner way to figure out the which half of the x1clk I'm in? >> >>Thanks, >>- John_H >> >> > > > It really only takes 2 flops working on rising edge. > > always @(posedge x1clk) Toggle <= ~Toggle; > always @(posedge x2clk) Delayed <= Toggle; > assign Phase = DelTog ^ Tog; > > Eric > >
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