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In the datasheet of xapp348, "Note if CPHA=0, the slave select signal will negate and then re-assert between consecutive byte transfers as stated in the SPI specification" In my application, I've to do the reverse. That means the SS_N has to negate and then re-assert between consecutive byte transfers when CPHA=1. Does anyone know how to modify the state machine?Article: 58202
Gary,
> So... How does one create and EDIF with XST?
To produce a human readable dump of the XST .ngc output file,
you can use the (barely documented) ngc2edif utility; however,
I don't believe the resulting EDIF file is suitable for use as
an input to the P&R tools.
Brian
C:\>ngc2edif
Usage: ngc2edif [-bd <busformat>] [-log <log_file>] [-quiet] [-w] <infile>
[<outfile>]
-bd <bus_format> Specify the bus delimiter to be used in the output edif.
The argument bus_format is required and could be of type
angle (bus notation would be bus<msb:lsb>
paren (bus notation would be bus(msb:lsb)
square (bus notation would be bus[msb:lsb]
none (generate buses without delimiters, busmsb:lsb
If -bd is not used, then the bus delimiters in the input
NGC file would be preserved.
-log log_file Specify log file (Default is ngc2edif.log).
-quiet Reduce screen output.
-w Overwrite the output file
<infile> Input File: '.ngc'.
<outfile> Output file name. Default is '<ngcfile>.ndf'
ngc2edif translates an NGC file into an EDIF netlist which is intended for use
within supported synthesis tools as a means of determining resource / timing
estimates. The EDIF is defined in terms of Xilinx Library Primitives (Unisims).
email_address@message.end wrote in message news:<llq9hvs39mifu4uj2blapj4r93osk8qij1@4ax.com>...
> Hi,
>
> I'm using ISE 5.02.03
>
> It looks like they (Xilinx) removed the EDIF option from XST.
>
> I found it in a google groups search (lots of people using it in
> 4.2i), and I found it in the version 3 XST manuals: set the output
> format to EDIF with -omft EDIF
>
> When I try that with 5.2i, I get an error:1361 (invalid omft option)
>
> So... How does one create and EDIF with XST?
>
> Please Help,
> Gary
> gwhelbig -at- yahoo -dot- com
Article: 58206Hi, As you indicate, the worst you can do is no compression at all. With Cyclone, you have the option of compressing or not compressing your bitstream. In general, we see ~1.8-2.0x compression ratios for full designs, and higher for less heavily utilized designs. Given that (as you say) no more than ~50-60% of the routing muxes will be used in even the most heavily routed design (typical is much less than that) there are plenty of 0s to take advantage of. Also, even used routing muxes will only have one bit in each stage turned on (for one-hot encoded muxes, that is). Add to this <100% utilization of LEs, most RAMs are initialized to 0s, etc. and I expect the vast majority of users will experience real savings with compression. I haven't seen any design that experienced less than about 1.6x. Regards, Paul Leventis Altera Corp. "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bf1j2a$1jvp$1@agate.berkeley.edu... > In article <3F144161.242FBBAB@xilinx.com>, > Austin Lesea <Austin.Lesea@xilinx.com> wrote: > >Compression of bit streams.... > > > >Is a tricky business. Some bitstreams compress well, others do not compress > >much at all. > > Right. But compression, in the worst case, offers no savings, but in > the best case offers substantial savings. > > And I'd expect that there is generally a fair amount of savings, just > from all the switchpoints which support a fairly large amount of > fanout when most switches only have a small amount of fanout most of > the time. > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58207
Mike et al - one of the things that you are running into is caused by the router and the part - these LUT based models cannot be accurately simulated to this point because you end up hand routing and then running simulations in a circle - I end up using Actel SX parts for critical timing (they have very deterministic delays through all of the cells that allow you to do this). I like Xilinx and Altera parts very much, but they have limitations, and timing accuracy is one of them. Consider the architecture of the part when you decide on your needs. Mike Treseler wrote: > > > Denis Gleeson wrote: > >> I realise that normally to obtain a given timing relationship one would >> use synchronous logic. But in this case as I require signals with the >> same frequency as the main clock I must use combinational logic. >> >> From the output of my logic simulator I am seeing some issues which >> confuse me: >> >> (a) Different logic gates have different delays, A NOT has less delay >> than >> an OR gate. May be this should have been obvious to me. Is it >> correct? >> >> (b) If I add a gate to create a delay, it seems to be getting >> optimised out. >> Is there some way to stop a gate added for this purpose from >> being removed? > > > > Consider using an FPGA with an on-chip PLL. > With a 4x internal clock you might be able > to use the synchonous template for your > design and eliminate those issues. > > -- Mike Treseler >Article: 58208
already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0307150558.53ac3a8c@posting.google.com>... > I know that respective regulars of this newsgroup don't like to give > decisive answers to A vs. X type of questions, but... This last visit > of the Xilinx representative was a shocker ! > > A bit of the background. We are as pure Altera shop as it goes. As > such we don't follow Xilinx products very closely. When we > occasionally did the check we typically found out that for our > applications there are no big differences between offerings of Xilinx > and Altera so there was no reason to step out of the comfort zone of > established routine. We believed that this situation will last forever > - it's what the competition is invented for, isn't it ? > > I have to mention that up until recently we never faced the project > that was very multiplication-intensive on its FPGA side. The project > we are trying to achieve now is exactly like this- very multiply > (MAC) intensive almost 100% FIR filtering. As usual, initially we > figured out a possible Altera solution. It was a bit pricey and > required two (or four smaller) chips but we thought that it is the > state of the art and so be it. But here come a representatives from > Xilinx and showed as their Virtex-II Pro parts... As I mentioned above > it was a shock: about three time as many multipliers as in similar > size/similar price Stratix chip. Two and a half times more multipliers > than in significantly bigger Startix chip ! > XC2P30 - 136 18x18 Dedicated multipliers > EP1S30 - 48 18x18 Embedded multipliers (the price of the parts is > similar to XC2P30) > EP1S40 - 56 18x18 Embedded multipliers > > I suppose that Startix parts are a bit faster, but it doesn't make a > difference for our application. Doing the computational part of the > design in the distinct (faster) clock domain doesn't make much sense > when the main (data acquisition) clock already runs at 190MHz. And for > 190MHz VirtexII-Pro is o.k. For us as far as Stratix unable to run > calculation at 380MHz its speed advantage doesn't care. > > Since I have no experience with Xilinx in general and with Virtex-II > Pro in particular I am afraid I missed something. It's almost too good > to be true. IMHO if there is no catch (availability ?) here the XC2P > parts draws Stratix into irrelevance for nearly all DSP-intensive > applications. Before making a decision, you should also check out Stratix's "soft multipliers." Basically RAM blocks (which Stratix has lots of) are used to do constant-coefficient multiplies using distributed arithmetic -- exactly what FIR filters need. Since the RAM blocks are re-writable, you can also update the filter coefficients by rewriting the RAMs, in case you're doing some adapative FIR filtering. Altera's FIR compiler will automate the implementation in RAM blocks for you. See http://www.altera.com/literature/hb/stx/ch_9_vol_2.pdf for the detailed documentation. The document lists (in Table 9-3) how many 16x16 multiplies (with a net throughput of one result per cycle) you can get with this technique in various Stratix devices, even without fully optimizing the design (i.e. wasting some of the RAM inputs & bits). 1S30: 159 more 16x16 multiplies 1S40: 187 more 16x16 multiplies If you really need 18x18 multiplies (not 16x16) you'll lose about 25% of these multipliers since you will need more M512 RAMs per multiplier. On the other hand, this table (Table 9-3) assumes you've done a fairly poor job of packing your FIR taps into the RAMs, so you could come out even with a real, optimized implementation, and achieve roughly the numbers as above even for 18x18. Adding in the 18x18 multipliers in the DSP blocks takes you to a total "soft" + hard multiplier count of about 200 for the 1S30, and about 250 for the 1S40 (can't be exact without knowing your number of taps and coefficient widths precisely). Vaughn -- I am an Altera employee, in case you didn't notice the email address :).Article: 58209
Hi there! I hope this isn't too trivial: I'm having a digital system with a finite state machine and a few other modules which send a control signal to the FSM. Do you think it is possible to use only clock and only posedge Flip Flops in such a design? I can't manage it without the inverted clock so that the control signals change at half the clock signal. But is there a way to avoid this without violating setup and hold times? Cheers, HenningArticle: 58210
I have to say ECS is a powerful tool, and well designed. The new features in
6.1 are definitely worth looking forward to, but the program as it stands I
think is a sound entry into the design flow. (It would of course be great to
see Verilog 2001 support in ECS..)
Well done Xilinx, keep up the good work
PETE MASH
"Dave Blevins" <blave@xilinx.com> wrote in message
news:3F15D58E.E09D699@xilinx.com...
> carmen lee wrote:
> 4
> > ECS in ISE is terrible bad.
>
> It's always helpful if you mention what version you're talking about. Is
> this 3.1i? 4.1i? 5.1i?
>
> > 1) graphic looks ugly
>
> In what way? It's a vector-based graphic application... What would you
> like to see changed?
>
> > 2) can't push pop hiarchy macros
>
> Push *will* work, if you ensure that the underlying schematic that
> you're trying to push into has been explicitly Added to the project as a
> Source, before attempting the push (this is done via Project Navigator's
> Add Source function). Unfortunately Pop does not work - ECS needs some
> source status information that ProjNav needs to provide .
>
> The overall Push/Pop behavior will be improved in the release slated for
> next year (let's call it "7.1i"), and it should work as you expect it to
> after that. New schematics will be automatically added to the project
> when they're created, and you'll be able to Pop back up to a schematic's
> parent symbol.
>
> > 3) difficult to edit symbols
>
> In what way?
>
> > 4) it was for documentation, not for design entry
>
> No, it's for design entry. It works great for documentation too, but its
> main reason for existence is to draw logic and interconnect.
>
> > 5) bugs ( like the one you report ), everytime open a macro schematic,
> > it gives an error, ask to overwrite,...
>
> Have you contacted the Xilinx Hotline about this? I am not familiar with
> this issue.
>
> > 6) difficult to name/rename buses and signals \
>
> In 5.1i, a "context" (right mouse button) menu item was added to make
> this easier.
>
> > 7) hard copy looks ugly too
>
> I'm not sure what you mean by this either, but next year's version will
> let you control the line width of printed objects. You'll also be able
> to have a print-specific color scheme, in addition to the current
> user-customizable schemes.
>
>
> Below you'll find partial lists of the enhancements made in the current
> version (5.1i), the upcoming version (6.1i), and next year's version
> ("7.1i"). These lists do not include bug fixes....
>
> I think you'll see that we are continuing to significantly enhance the
> ECS application with every release.
>
> cheers,
>
> Dave Blevins
> Xilinx, Inc.
>
> -----------------
>
>
> ECS Enhancement Summaries
>
>
> 5.1i (i.e. current version of ISE)
>
> - Significant improvements to Attribute Handling - creation, editing,
> and control of attribute visibility on sheet
> - Easier renaming of nets/buses
> - Revised copy/paste algorithm handles net/instance names better
> - Much better copy/paste behavior when copying/moving large groups of
> objects
> - Automated naming of nets connected to a named bus
> - Zoom In/Zoom Out can be dynamically performed while in any Mode (via
> <ctrl> drag)
> - User-definable color schemes for schematics
> - Context-sensitive context (right mouse button) menus
>
> -------------------------
>
> 6.1i (to be released in the next few months)
>
> Schematic Editor -
>
> - The "Generate HDL Template from Symbol" Tool, also available in the
> Symbol Editor, allows an HDL source file with inputs and outputs
> corresponding to the currently selected symbol to be generated.
> - Bustaps are automatically created when a wire is drawn between a bus
> and a pin. This feature can be disabled if desired.
> - "Quick" I/O Marker feature - in Add I/O Marker mode, clicking or
> drawing a box around symbol pin(s) will automatically add a short wire
> and I/O Marker of the correct direction to each pin.
> - A group of selected Instances or I/O Markers can be aligned using the
> Align command.
> - The Last/Next View feature allows previously used viewpoints/zoom
> levels to be recalled.
> - New autoscrolling feature causes the viewpoint to automatically scroll
> when the user drags the mouse cursor to the page edge during certain
> operations (Zoom to Box, Add Line, Add Wire, etc.). The "hot zone" size
> and scrolling speed can be adjusted via the Preferences dialog.
> - "Snap To" feature for I/O Markers - when adding an I/O Marker, it will
> snap to the nearest wire or symbol pin. Four small squares will be
> displayed when the cursor is close enough for the snap to occur.
> - The Text Alignment command allows a group of selected text items to be
> aligned either left or right, or top or bottom as appropriate. Note: to
> align a set of net names, the user must select the "Attribute windows
> only" option in the Select Options pane before selecting the names.
> - The "Symbol Info" command will display a data sheet, if one is
> available, for the currently selected symbol in a document viewer
> window.
> - When moving a visible attribute (e.g. Instance Name), a line is drawn
> from the attribute to the corresponding instance's origin, so that it's
> always clear what the attribute is associated with.
> -Miscellaneous DRC improvements have been implemented.
> - "Rename Selected Instance" makes renaming objects easier.
> - A "Select" button has been added to the Find dialog, allowing found
> item(s) to be selected directly from the Find function, rather than
> having to close the dialog and then select the item(s).
>
> Symbol Editor -
>
> - When a pin is added, an attribute window for the corresponding pin
> name is automatically added (optional). Both the relative position and
> the distance from the pin of the attribute window are user-controllable.
>
> RTL Viewer -
>
> - The Viewer can now flatten sub-modules to show their contents, rather
> than requiring the user to push into them. The user can select the size
> of modules that should be flattened using the "Minimum Number of -
> Instances Per Page" preference.
> - The user can now cross-probe from RTL instances to the corresponding
> HDL line numbers, where possible.
> - Support for incremental synthesis has been added.
> - Instance and Symbol names can now be added to RTL Views. Note that
> these are temporary; RTL Views are stored in memory (not on disk) and
> are discarded when the RTL Viewer is closed.
> - Finite State Machine symbol support has been added.
> - Multiple-bit In/Out ports on instances are now notated with their
> width.
> - Double-clicking on an object in the Hierarchy View now causes that
> object's underlying schematic to be generated.
>
> -------------------------
>
> Some Things Planned for 7.1i
>
> - Improved macro/hierarchy push-pop operations
> - Allow RTL views to be saved as read-only schematics, along with
> instance/symbol name annotations if desired
> - Optional: ECS windows can be "docked" into Project Navigator
> - More DRC checks
> - Printing options to allow changes to line widths - e.g. nets, buses,
> etc.
> - Separate color scheme for printing
> - ...and many more...
>
>
> .end.
>
>
>
>
>
>
>
>
>
>
>
Article: 58211>Ignoring and bypassing the 8B10B encoder, each MGT output will act as a >parallel-to serial converter, converting 20 bits parallel into 1-bit >serial. All you need to supply is a reference clock that is 20 times >slower than the outgoing bitstream. >The lower limit for the reference clock frequency is 50 MHz, which >generates a 1 gigabit/sec output stream. If you want to have a lower >output rate, "stutter" the bits, i.e. duplicate adjacent bits on the >parallel side. That way, you can achieve any output bit rate you want, >from dc to 3 Gbps. I've been doing too much software recently. Whan I saw that, my head started to hurt thinking of the ugly code I was trying to write to double up on the bits. It was an embarassingly long time before I switched to hardware mode and the problem became trivial. Thanks for another neat trick. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58212
>In general, we see ~1.8-2.0x compression ratios for full designs, and higher >for less heavily utilized designs. Given that (as you say) no more than >~50-60% of the routing muxes will be used in even the most heavily routed >design (typical is much less than that) there are plenty of 0s to take >advantage of. .... I have visions of a new paramter to the place/route tools: The size of the ROM/RAM the result must fit into. :) > I haven't seen any design that experienced less than about 1.6x. One case where compression can win big is if you have several similar designs and you select one at startup time. Just store the differences. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58213
> By the way, we are live at White Mountain Rsearch Center, Barcroft Station > with another group of 100 2V6000's. Acceleration factor is ~26, so we > expeft to see upsets every 2 to 3 days at this altitude. So far, we > are seeing exactly what the "theory" predicts for altitude. Neat. Thanks. Can you package up a box of chips and run a test via air freight? I'm guessing that they are powered up but don't need to be clocked so heat won't be a problem. I know about cooling problems at higher elevations due to the reduced density of the air. How many other second-order type problems from elevation are there that we need to keep in mind? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58214
I don't think so.
Why Xilinx didn't adopt Viewdraw as the sch design entry tool .
"Peter Mash" <pwtm2@cam.ac.uk> wrote in message
news:bf5f3p$9rs$1@pegasus.csx.cam.ac.uk...
> I have to say ECS is a powerful tool, and well designed. The new features
in
> 6.1 are definitely worth looking forward to, but the program as it stands
I
> think is a sound entry into the design flow. (It would of course be great
to
> see Verilog 2001 support in ECS..)
>
> Well done Xilinx, keep up the good work
>
> PETE MASH
>
>
>
> "Dave Blevins" <blave@xilinx.com> wrote in message
> news:3F15D58E.E09D699@xilinx.com...
> > carmen lee wrote:
> > 4
> > > ECS in ISE is terrible bad.
> >
> > It's always helpful if you mention what version you're talking about. Is
> > this 3.1i? 4.1i? 5.1i?
> >
> > > 1) graphic looks ugly
> >
> > In what way? It's a vector-based graphic application... What would you
> > like to see changed?
> >
> > > 2) can't push pop hiarchy macros
> >
> > Push *will* work, if you ensure that the underlying schematic that
> > you're trying to push into has been explicitly Added to the project as a
> > Source, before attempting the push (this is done via Project Navigator's
> > Add Source function). Unfortunately Pop does not work - ECS needs some
> > source status information that ProjNav needs to provide .
> >
> > The overall Push/Pop behavior will be improved in the release slated for
> > next year (let's call it "7.1i"), and it should work as you expect it to
> > after that. New schematics will be automatically added to the project
> > when they're created, and you'll be able to Pop back up to a schematic's
> > parent symbol.
> >
> > > 3) difficult to edit symbols
> >
> > In what way?
> >
> > > 4) it was for documentation, not for design entry
> >
> > No, it's for design entry. It works great for documentation too, but its
> > main reason for existence is to draw logic and interconnect.
> >
> > > 5) bugs ( like the one you report ), everytime open a macro schematic,
> > > it gives an error, ask to overwrite,...
> >
> > Have you contacted the Xilinx Hotline about this? I am not familiar with
> > this issue.
> >
> > > 6) difficult to name/rename buses and signals \
> >
> > In 5.1i, a "context" (right mouse button) menu item was added to make
> > this easier.
> >
> > > 7) hard copy looks ugly too
> >
> > I'm not sure what you mean by this either, but next year's version will
> > let you control the line width of printed objects. You'll also be able
> > to have a print-specific color scheme, in addition to the current
> > user-customizable schemes.
> >
> >
> > Below you'll find partial lists of the enhancements made in the current
> > version (5.1i), the upcoming version (6.1i), and next year's version
> > ("7.1i"). These lists do not include bug fixes....
> >
> > I think you'll see that we are continuing to significantly enhance the
> > ECS application with every release.
> >
> > cheers,
> >
> > Dave Blevins
> > Xilinx, Inc.
> >
> > -----------------
> >
> >
> > ECS Enhancement Summaries
> >
> >
> > 5.1i (i.e. current version of ISE)
> >
> > - Significant improvements to Attribute Handling - creation, editing,
> > and control of attribute visibility on sheet
> > - Easier renaming of nets/buses
> > - Revised copy/paste algorithm handles net/instance names better
> > - Much better copy/paste behavior when copying/moving large groups of
> > objects
> > - Automated naming of nets connected to a named bus
> > - Zoom In/Zoom Out can be dynamically performed while in any Mode (via
> > <ctrl> drag)
> > - User-definable color schemes for schematics
> > - Context-sensitive context (right mouse button) menus
> >
> > -------------------------
> >
> > 6.1i (to be released in the next few months)
> >
> > Schematic Editor -
> >
> > - The "Generate HDL Template from Symbol" Tool, also available in the
> > Symbol Editor, allows an HDL source file with inputs and outputs
> > corresponding to the currently selected symbol to be generated.
> > - Bustaps are automatically created when a wire is drawn between a bus
> > and a pin. This feature can be disabled if desired.
> > - "Quick" I/O Marker feature - in Add I/O Marker mode, clicking or
> > drawing a box around symbol pin(s) will automatically add a short wire
> > and I/O Marker of the correct direction to each pin.
> > - A group of selected Instances or I/O Markers can be aligned using the
> > Align command.
> > - The Last/Next View feature allows previously used viewpoints/zoom
> > levels to be recalled.
> > - New autoscrolling feature causes the viewpoint to automatically scroll
> > when the user drags the mouse cursor to the page edge during certain
> > operations (Zoom to Box, Add Line, Add Wire, etc.). The "hot zone" size
> > and scrolling speed can be adjusted via the Preferences dialog.
> > - "Snap To" feature for I/O Markers - when adding an I/O Marker, it will
> > snap to the nearest wire or symbol pin. Four small squares will be
> > displayed when the cursor is close enough for the snap to occur.
> > - The Text Alignment command allows a group of selected text items to be
> > aligned either left or right, or top or bottom as appropriate. Note: to
> > align a set of net names, the user must select the "Attribute windows
> > only" option in the Select Options pane before selecting the names.
> > - The "Symbol Info" command will display a data sheet, if one is
> > available, for the currently selected symbol in a document viewer
> > window.
> > - When moving a visible attribute (e.g. Instance Name), a line is drawn
> > from the attribute to the corresponding instance's origin, so that it's
> > always clear what the attribute is associated with.
> > -Miscellaneous DRC improvements have been implemented.
> > - "Rename Selected Instance" makes renaming objects easier.
> > - A "Select" button has been added to the Find dialog, allowing found
> > item(s) to be selected directly from the Find function, rather than
> > having to close the dialog and then select the item(s).
> >
> > Symbol Editor -
> >
> > - When a pin is added, an attribute window for the corresponding pin
> > name is automatically added (optional). Both the relative position and
> > the distance from the pin of the attribute window are user-controllable.
> >
> > RTL Viewer -
> >
> > - The Viewer can now flatten sub-modules to show their contents, rather
> > than requiring the user to push into them. The user can select the size
> > of modules that should be flattened using the "Minimum Number of -
> > Instances Per Page" preference.
> > - The user can now cross-probe from RTL instances to the corresponding
> > HDL line numbers, where possible.
> > - Support for incremental synthesis has been added.
> > - Instance and Symbol names can now be added to RTL Views. Note that
> > these are temporary; RTL Views are stored in memory (not on disk) and
> > are discarded when the RTL Viewer is closed.
> > - Finite State Machine symbol support has been added.
> > - Multiple-bit In/Out ports on instances are now notated with their
> > width.
> > - Double-clicking on an object in the Hierarchy View now causes that
> > object's underlying schematic to be generated.
> >
> > -------------------------
> >
> > Some Things Planned for 7.1i
> >
> > - Improved macro/hierarchy push-pop operations
> > - Allow RTL views to be saved as read-only schematics, along with
> > instance/symbol name annotations if desired
> > - Optional: ECS windows can be "docked" into Project Navigator
> > - More DRC checks
> > - Printing options to allow changes to line widths - e.g. nets, buses,
> > etc.
> > - Separate color scheme for printing
> > - ...and many more...
> >
> >
> > .end.
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
>
>
---
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Article: 58215Ray Andraka <ray@andraka.com> writes: > > David Tucker wrote: > > > I'm working on implementing a custom game boy advance cartrige with > > the following features: > > > > - 4-16MByte flash rom (bank switched to a 24 pin buss) > > - 32kbyte save ram (game state save, can be stored in flash rom if > > needed) > > - usb-to-pc link > > - in system reprogramability via usb > > - hardware assist for MP3/OGG decoding or similar lossy compression > > (target compression is 8bit, 2-8Kbit/sec, for 30min of audio in > > 2mbyte of rom) > > > I recall seeing recently someone with an FPGA (I think it is Xilinx > Spartan2) board for a gameboy advance. I'll have to look around to see > where it was, but I did get the distinct impression it is commercially > available. > Would that be this one? http://www.charmedlabs.com/xportmain.htm According to the FAQ at http://www.charmedlabs.com/xportfaqmain.htm the FPGA is an XC2S50. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 58216
leon qin <leon.qin@2911.net> wrote: : I don't think so. : Why Xilinx didn't adopt Viewdraw as the sch design entry tool . Then they have to pay fees to the producer for every copy. Not good for the free Webpack... Bye : "Peter Mash" <pwtm2@cam.ac.uk> wrote in message : news:bf5f3p$9rs$1@pegasus.csx.cam.ac.uk... :> I have to say ECS is a powerful tool, and well designed. The new features <about 200 lines deleted> Please don't fullquote. This clutters up the archives. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 58217
Henning Bahr wrote: > Hi there! > I hope this isn't too trivial: > I'm having a digital system with a finite state machine and a few > other modules which send a control signal to the FSM. Do you think it > is possible to use only clock and only posedge Flip Flops in such a > design? I can't manage it without the inverted clock so that the > control signals change at half the clock signal. But is there a way to > avoid this without violating setup and hold times? I'm not completely sure, but I would say that today 90% of all clocked designs are working with only one clock using only one edge. What might scare you is your belief that the new state arrives at the input of FlipFlops before the clock edge has "gone through", right? Indeed, that's a problem. But first it is to say that it takes some time until the new state arrives. Secondly, clocked FlipFlops are built so that they have a very narrow time margin for "opening". This also requires more or less fast clock edges. Thirdly, chip designers try to keep the clock skew at a minimum. That is, all FlipFlops on the chip shall receive their clock more or less at the same time. FPGAs (and ordinary chips as well) have special clock distribution networks for this purpose. To conclude: If you are working on an FPGA/CPLD design, you don't need to worry about this issue and you can safely go with one clock and one edge. The only thing you have to ensure is that you force the clock signal to be routed via a clock distribution network. Regards, MarioArticle: 58218
"Ray Andraka" <ray@andraka.com> wrote in message news:3F134720.D19A8BCA@andraka.com... > Mine used a barrel shift in the feedback to get a gain that increased with the > size of the error. Had to do that to get a quick lock and still be able to > chase the reference. The reference was derived from a quad encoder on the > mechanical media path. The PLL had to adjust a process to keep a certain number > of events between encoder pulses. All in all, it was a pretty nasty problem > because of the dynamics and limited resolution of the encoder. > > Kevin Neilson wrote: > I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it. -KevinArticle: 58219
In article se10110@yahoo.com says... > Hi all. > > I was actually thinking about digital PLLs recently when I was doing > investigation on analog PLLs. > > Can someone describe the basic parts and operation of a DPLL? > Essentially these are the components I figured would be needed and this > is how the operation might work, I'd appreciate comments.... Just wondering, I never got any responses to my original (and slightly off-topic) post. Was I off in my design insights? I'm actually thinking about using my aforementioned design in a project, I would like to know if it's a good starting point or not... One thing I was particularly curious about, when thinking about my own design, do I have to worry about synchronizing / clock domain problems between the two reference inputs to the loop or does the standard two- DFF design actually take care of that? I'm guessing that the *outputs* (Up/Down) from the DFF loop should be put through a de-metastablizer (two DFF in series or something) since those outputs could change irrespective of my system clock. Comments? Oh, finally, is there a better frequency/phase detector than the standard two-DFF one? I know that the two-DFF one hunts when the phase/frequency are close to being locked. Thanks! -- Jay.Article: 58220
Hi, I'm having some trouble with Quartus II 3.0 on win2k and a selfmade byteblaster cable. I'm getting a 'Attempted to acccess JTAG server - internal error code 82 occured' when clicking on the 'Add Hardware' button in the Hardware setup window. Since the hardware is rather simple I guess it's a driver problem :-/ Has anyone similar problems with Quartus II? PeterArticle: 58221
Hi Fellows, I am having this error, I changed my edf file but it didn't work. still getting this error.. ERROR:NgdBuild:180 - On or above line 1413 in file "VIR3_top.edf": Bad instanceRef "SR_DATA_IO_int_reg_7" in net "N_SR_DATA_IO_7". This likely means that the EDIF netlist was improperly written. Please contact the vendor of the program that produced this EDIF file. I check the file but I didn't find any thing unusal infact everything for SR_DATA_IO_7 is same for the one's which are not mentioned in the error. Like SR_DATA_IO_6 or lower. Waiting for your view on this Cheers ISAACArticle: 58222
david.tucker@goliathindustries.com (David Tucker) wrote in message news:<e67c452f.0307010747.390938fc@posting.google.com>... > I'm working on implementing a custom game boy advance cartrige with > the following features: > > - 4-16MByte flash rom (bank switched to a 24 pin buss) > - 32kbyte save ram (game state save, can be stored in flash rom if needed) > - usb-to-pc link > - in system reprogramability via usb > - hardware assist for MP3/OGG decoding or similar lossy compression >(target compression is 8bit, 2-8Kbit/sec, for 30min of audio in 2mbyte of rom) > > Space is a huge concern, my target board size is 1x2 inches. Plus my > target cost in quantitys of 1,000 or more is $10-$15 total for the space is not your concern directly, 1x2 inches (if fully avaiable for components and both sides allowed) is today pretty much enough real-estate. price is your concerne, and real one. flash+ram+logic for bank switching == fits the target price if you need USB then it comes real problem (at your target price) options - ftdi245 5usd needs support logic for flash reprog - usb tranceiver (low cost) needs to large PLD/FPGA too expensive - c801f320 7$ (works without crystal!!!) - AT90S2313 with soft-usb 2$ needs 12MHz and some glue logic for flash access - microuPD?? from www.st.com has 8051 micro, usb+flash+ram and small PLD price? - 89SND1 8051+MP3+usb breaks the budget - some ARM device that does the MP3 in software - again breaks budet PLD at your budget you can only use some small (smallest) PLD some small coolrunner (www.xilinx.com) the device will be only enough for bank switch and some gluing ok, the flash reporgramming must be done with some program that is executed by the GBA (the pld is too small to isolote the flash and connect it to usb_micro) MP3 decoder - trying it PLD/FPGA is out of the question (to costy) so you need some special MP3 circuit for that job, and that will break your budget. sorry - at 1K volumes the 15$ target price cant be achieved. I assume your allowances for NRE costs are 0.0$ ? you need to cut-off something or extendt the price or make 2 options a) no MP3 accelerator b) with MP3 accelerator antti PS the GBA device Ray referred has a XC2S100 and some memory if I recall correctly and costs 150$Article: 58223
Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3F15ECE4.50D5B45E@xilinx.com>... > Hello Rob, > > I am fairly certain you won't find the pinout in the > IP data sheet. There are a lot of pinouts and we have > They should be able to get it to you. There's nothing > super secret about it... > > Thanks, > Eric Crabill if you have access to either avnet or memec RDC lounges there are ref designs with schematics and PCI UCF files (for xilinx pci core) also if you goooooooooogle real deep - some strange edu project has published some partial xilinx pci designs there are also info as needed - sorry dont recall where it was or how to find it. anttiArticle: 58224
Hi,
I am using DDC from Xilinx CoreGen. What is the data format of the
input (DIN)? Is it two's complement or biased or something else?
Regards,
Nagaraj CS
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