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Hal, Simple. Every memory cell is a drain (pun intended) as the devices are getting leakier and leakier. No memoery cells: less leakge. Austin Hal Murray wrote: > From the article: > Antifuse also has some power consumption advantages over SRAM. > > Can anybody explain that to me? Perhaps that refers to static current? > > [The SRAM part of an SRAM FPGA doesn't change during normal operation > so the F part of C*V^2*F is 0.] > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 61526
Don't remember "Shannon's expansion theorem". Can simplify using boolean algebra postulates. C' + A'C + AB'C = (C' + A')(C' + C) + AB'C = (C' + A') + AB'C =(C' + A') + CAB' =( (C' + A') + C)((C' + A') + AB') =(C' + C) + A')((C' + A') + AB') = (1 + A')((C' + A') + AB') = 1((C' + A') +AB') = ((C' + A') + A)((C' + A') + B') = ((C' + 1))((C' + A') + B') = (C' + A' + B') or, using De'Morgan's theorem (A.B.C)' = A'+B'+C', you could've reached the above result instantly! -- sincerely, Russell Powell Artisan Components SR. FAE - U.S. Central rpowell@artisan.com 469-438-6589 "zaf" <hsultan@utnet.utoledo.edu> wrote in message news:3aaabe6b.0310051158.5dd1f1b@posting.google.com... > Hello members...i need urgent help with a digital design problem > > can some please help me expand the following function using shannon's > expansion theorem > > F = (A.B.C)' > = C' + A'C + AB'C > > I need to map this function to an Altera ACT 1 FPGA logic module with > three 2:1 MUX's and one OR Gate. > > any help would be greatly appreciated > > thanks > zafArticle: 61527
Vinh Pham wrote: > > > (I remember a Xilinx article stating that metastability can be ignored > > for clock rates < 200MHz). > > It might be a good idea to see what situation that < 200 MHz thing applies > to. > > Metastability can happen at any frequency. Say you have just a 1 Hz signal > that you're resynching to just a 2 Hz clock. If the phase relationship is > just right, your FFs can go metastable all the time. > > Besides, bugs caused by metastability are a pain to track down. If you're > unlucky, they'll occur with the customer's equipment, but not with the one > in your lab. Worse yet, when you pay to ship the customer's equipment back > to your lab, the bug mysteriously disappears. Prevention is far more > valuable than a cure, in this case. :_) I think the frequency reference is talking about ignoring metastability once you have used the 2 FF sync trick. The sync circuit depends on the timing slack between the two FFs to allow the output of the first FF to settle. Above 200 MHz the slack time gets pretty short even if your routing is pretty good. The other effect of frequency is on MTBF. This is a linear effect related to the product of the two frequencies. So when reading a pushbutton at 32 kHz, I would not worry too much about metastability. But at much higher clock rates without a sync circuit, it can be a problem as you say. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61528
Brian, Wow. I agreed to move this up the list, and thanked you. Various CR (change requests) are now in progress. I am so dissapointed. I agreed with you. I thanked you for putting all of the items in a nice concise list. No denial here. I explained why the capacitance is high. In fact, why in must be high, and why we (and others) have no choice unless the LVDS inputs are dedicated in their own bank, with no other standards attached (which no one wants in the FPGA world). Our parts meet the LVDS standard, they work. If you use them wrongly, they don't work. If you want 2pF inputs, go make your ASIC. That is how the ASIC/ASSP folks try to lock us out of their markets. Unfortunately for them, there are plenty of folks who can not afford their devices, and know how to properly simulate, and terminate and use capacitive inputs. As for wanting to "observe" the signal, that is about the best way to mess it up (which you aptly point out). Rather than do that, how about using the existing variable phase shift feature to measure the actual eye opening at the place where it counts: in the FPGA? Our customers that do that are delighted that they no longer have to lose sleep over how much margin they have: they measure it directly in the device itself. You asked about the IBIS model, so I checked that. If the coupled/uncoupled t-line are an issue, that is Mentor's responsibility. I hope you file bug reports with them if that is the case. Sorry you are not satisfied with the agreement, and the positive response, and the acknowledgement and appreciation. AustinArticle: 61529
Guy Eschemann wrote:
>
> My 27 MHz signal is a single bit line, not a bus.
> Actually it is the clock line for an 8-bit video data stream. My
> problem is to synchronize this incoming data stream with the 108MHz
> system clock.
>
> I know I could be using an asynchronous FIFO for this, but this might
> be overkill. In order to save resources, wouldn't it be better to
> synchronize the 27 MHz clock with my system clock (2-stage pipeline
> should do the job), then use some logic to detect the appropriate edge
> and use the output of the edge detector as a clock enable signal for
> the input data FFs, which are clocked by the system clock ?
Since your internal clock is 4 times the external clock, you should have
no problem. Use the 27 MHz clock to register the data and sync the 27
MHz clock to the 108 using two FFs. The resulting synchronized clock
will give a rising edge between a quarter and a half period of the 27
MHz clock and can be safely used to enable reclocking of the data. You
should use an edge detector which will delay the clock one more quarter
of a 27 MHz period and will still be safe.
--- --- Sync'd
Data ---------|D Q|------------------------------------|D Q|------
27 MHz --+----|> | --- | | Data
| --- +------------| | | |
| --- --- | --- | & |------|CE |
+----|D Q|-----|D Q|--+--|D Q|----O| | | |
108 MHz ------|> | |> | |> | --- |> |
--- --- --- ---
View this in a monospaced font.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 61530I have developed the PCI-device for which it is necessary 128 bytes of ports of input-output, 512 Kb of memory and one interrupt. When I install 4 devices simultaneously, BIOS allocates for them necessary resources, windows 98 allocates resources only for 3 devices. And Windows XP at all it does not want to be loaded. Why?Article: 61531
> The problem with >using 2 stage FFs with a bus is that some bits might go metastable, and get >delayed one cycle, while others don't, so the bits on your bus get >misaligned. For example, if you have a 4-bit bus that transitions from a >0x0 to an 0xF, on the 108 MHz side you might see it go from 0x0 to 0xE then >finally to 0xF. That's not a metastabiliy issue. It's a simple setup/hold time. Some of the bits get there before the clock and some get there after. Even if the all get there at the same time, the setup times will differ (slightly) from FF to FF or the routing will be different or ... -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 61532
I have a question about how I best should implement my I/O in an FPGA (Altera EPXA1F484C1) . Being a student, and not having a whole lot of people to ask for advice, I have no idea how I best should solve my problem. I initially wanted to have 128 + a few inputs and 128 + a few output pins, so that I could work in parallell on 128 bit blocks. This didn't work, apparently because I had used to many pins. Quartus (II 3.0) gave said in it's report that I had only used 258 of in all 292 available pins, but I suppose I had used all available general purpos I/O-pins or whatever. I scaled down my design, until I got to compile it. At that time I was using 186 pins. And I when looked at the floorplan, every row and column I/O-pin was in use. So I guess 186 pins is the maximum limit. So my first question is: Why can I only use 186 pins, when Quartus tells me that there are 292 pins available? So I had to decise how I would send and recieve my data. And this is my main question, my design question: Would I be best off using say 64 pins for input and 64 pins for output, and solve my problem that way, or could I use a bidirectional solution, where I alternate on recieving and sending data over a 128 bits bus? I put together a test-design wich utilizes this solution, and it compiled fine. I put an image of the schematics on a website, so you can take a look: http://www.battlefield.no/bilder/EPXA1_PinTest3.gif But is this an sound solution?! Or should I rather go for separat in- and out-pins? Since I have no clue, I have to ask someone. And you guys drew the shortest straw ;-) -"Panic"Article: 61533
"worry" is an interesting word. What are the costs of getting it wrong? You should worry a lot more if your design will go on an expensive satellite or will be controling a nuclear reactor. If you want your circuit to work correctly, you always have to pay attention when crossing clock domains. In many cases, it is easy to get it good-enough. You can never eliminate metastability problems, just reduce the probability/MTBF. By "good-enough" I mean that the chances of metastability causing troubles are so low that you should spend your time looking for problems in other areas. For example the MTBF might be the age of the universe. >Is a simple 2-stage DFF synchronizer a safe way to handle this ? (I >remember a Xilinx article stating that metastability can be ignored >for clock rates < 200MHz). I'd suggest finding that Xilinx article and understanding it. As others have said, the key is slack time. If you give the tools a chance, they can do stupid things. You need to supply the right constraints to make sure they don't. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 61534
> > Thanks. One other question, is it a pure RTL design or does it > instantiate Xilinx specific primitives? Ditto for NIOS? > > Cheers, > Jon Jon, The Nios RTL does instantiate Altera-specific primitives for things such as multiplication and on-chip memory (for register files, FIFOs, etc.)... with Nios you get the RTL source code for free, but the licensing agreement specifically states that the RTL is for use in Altera devices only (although ASIC licensing is an option). Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 61535
I was discussing SDRAM a few weeks ago and I can't seem to find it in this newsgroup. I guess it had gone to email. I have finally had a chance to go on the web and take a look at some of the sources and I am finding information hard to come by. I only find four main companies making parts in either x32 arrangements or in small packages. They are Micron, Samsung, Elpida and Hynix. I know there are a few "also ran" companies making parts, but they don't seem to have the small packages or the wide bus. Does anyone know if these parts in the small FBGA or TSSOPs packages are shipping and if the availability is good? Any other makers than the ones I listed above? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61536
maxlim79@hotmail.com (Maxlim) wrote in message news:<a6140565.0310031910.90bc774@posting.google.com>... > Thanks a lot, Ken. I tried to copy all header files needed by the > library into nios-gnupro/nios-elf/include folder when the compiler > asking for those files. After I'd done that, a lot of errors appeared. > It seem like the library files for multi-precision arithmetic is not > supported by GNUPro compiler. Is there any other multi-precision > arithmetic library files available for GNUPro compiler? Hi Maxlim, I am still not sure what you mean by "multi-precision" - you you mean "floating point"?? The GNU toolset/GCC compiler/associated libraries do support floating point math. Declaring a variable as "float", "double", or "long long" (fixed point) should work. There is also a library include, 'math.h' which provides more advanced math beyond the basic arithmetic and logical operands (this is getting into the area where the rednat/gnupro documentation should cover things). One piece of advice I can give you is that all the paths required for default libraries should be setup when you installed Nios -- so copying library files around might cause more harm than good. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 61537
Theron Hicks (Terry) wrote: <snip> > The area of improvement is > in simple, useable documentation. If I need to check three or for different > areas for a full picture of what it taakes to get a job done, can you at least > create a link between the areas. Check out publications by part: http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Publications This was recently added this area to the web site to do just that. If you see anything missing, or have suggestions on how to improve it you can contact me directly since I do not check this newsgroup too often. Xilinx could save a bundle in tech support, if > they would just improve the documentation. We have also put the ability to provide direct feedback on specific documents in our documentation collection. If you ever look at a doc and do not feel it has met your needs, you can tell us by clicking on "Helpful? Yes|No". Be as specific as possible. Let me know if there is anything else we can do. Thanks, RobertArticle: 61538
You should always be concerned about metastability, whenever asynchronous signals are being synchronized. Let me add some numbers to Phil Freidin's excellent comments: Metastability creates unpredictable additional settling delays (even oscillations can be considered delays to valid out). The probability of a specific max delay depends on the clock rate, the data rate, and the IC technology. For Virtex-IIPro, we measured and extrapolated the following data for your case: If your data and clock were truly asynchronous (!), and you could guarantee 3 ns of slack between the two stages of yor double-synchronizer, then you would get, statistically, one failure in a billion years. For every extra ns of slack, the MTBF would be a million times longer. ( Since these numbers are for Virtex-IIPro, add an extra nanosecond for the slightly slower Spartan-II.) As you can see, with a little care in short routing between the two flip-flops, you need not loose any sleep. But you said that the clock was not truly asynchronous, but was 4 times the data rate, with an unknown ( but stable?) phase relationship. I would solve that with an adaptive circuit, driving data into a 4-bit shift register and detecting the best phasing with a majority-voting circuit.(Just one LUT). Effectively you try out, which of the four clock pulses per data bit gives you the best result. This assumes a reasonably stable (unknown) phase relationship, and would avoid all fear of metastability. Peter Alfke =================================== Hal Murray wrote: > > "worry" is an interesting word. > > What are the costs of getting it wrong? You should worry a lot > more if your design will go on an expensive satellite or will be > controling a nuclear reactor. > > If you want your circuit to work correctly, you always have to > pay attention when crossing clock domains. In many cases, it > is easy to get it good-enough. > > You can never eliminate metastability problems, just reduce the > probability/MTBF. > > By "good-enough" I mean that the chances of metastability causing > troubles are so low that you should spend your time looking for > problems in other areas. For example the MTBF might be the age > of the universe. > > >Is a simple 2-stage DFF synchronizer a safe way to handle this ? (I > >remember a Xilinx article stating that metastability can be ignored > >for clock rates < 200MHz). > > I'd suggest finding that Xilinx article and understanding it. As > others have said, the key is slack time. If you give the tools > a chance, they can do stupid things. You need to supply the right > constraints to make sure they don't. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 61539
"Morten Leikvoll" <m-leik@online.nospam> wrote in message news:<IP8gb.28381$os2.396615@news2.e.nsc.no>... > My collegue and I discussed how our placer (xilinx's) handled going from 1x > clocks to 2x clocks and back. (These have of course common rising edge) > > For this example I use a 100Mhz clock and a 200Mhz clock: > > There are 3 ways of doing this: > > 1 (based on the timing of the previous ff's output ) Signals coming from 1x > to 2x will be routed with max 10ns delay. This means that you can not tell > wether the signal will appear at the 2x at the 5ns or 10ns rising 2x clock. > > 2 (based on the input timing) Signals coming from 2x to 1x will be routed > with max 10ns delay. This means that the output can sometimes skip the first > 1x edge. > > 3 (based on the lowest delay of input and previous output) This works, but > my collegue claims this tool doesn't do it this way. Can anyone confirm this > is the case? > > How DOES the placer tool handle this? If you check your source and destination clocks for the timing in your timing analyzer, you'll see that the timing is based on 5 ns, not 10 ns. Unless you tell it otherwise with your timing constraints, the tools assume that something generated in one domain will be used in the other domain on the earliest rising edge. The logic will require the 5 ns times unless you have explicit enables in the 200MHz domain and specific logic to keep the 200 MHz outputs steady for 2 clocks going back to the 100 MHz domain. Everything ends up being timed to the faster clock. Can you explain how a 10 ns delay either direction would work properly given the data changes 5 ns before the clock edge (at least for *a* rising edge for the 100 MHz to 200 MHz transition).Article: 61540
"zaf" <hsultan@utnet.utoledo.edu> wrote in message
news:3aaabe6b.0310051158.5dd1f1b@posting.google.com...
> Hello members...i need urgent help with a digital design problem
It amuses me that student problems are invariably "urgent". By
contrast, we who work in the commercial world of course have
infinitely long timescales for our projects :-)
> can some please help me expand the following function using shannon's
> expansion theorem
Not being an academic I have never heard of Shannon's expansion
theorem, but Shannon was a pretty bright guy and I have no reason
to doubt that he invented such a thing.
> F = (A.B.C)'
> = C' + A'C + AB'C
It's useful to remember that you can write a multiplexer as
a Boolean expression:
Mux = in0.Sel' + in1.Sel
represents a 2:1 mux selected by Sel, with inputs in0 and in1.
To help with this Mux description, let's define that as a
function M(in0,in1,Sel).
So we can re-think your expression as multiplexers...
F = C' + (A' + A.B').C
= C' + C.M(1, B', A)
= M(1, M(1, B', A), C)
One more little observation:
B' = 1.B' + 0.B
= M(1, 0, B)
Hey, I got one over on your prof! I don't need that OR gate at all!
F = M(1, M(1, B', A), C)
= M(1, M(1, M(1, 0, B), A), C)
|\
|\ 1-| |
|\ 1-| | | |----F
1-| | | |------| |
| |------| | |/
0-| | |/ |
|/ | C
| A
B
ASCII-schematic with thanks, as usual, to Andy Weber's wonderful
AACircuit program (www.tech-chat.de).
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 61541Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote in message news:<lthe2m7f3m.fsf@mis.dtek.chalmers.se>... > hmurray@suespammers.org (Hal Murray) writes: > > > >I overuse the syn_keep attribute and I hate the idea of instantiating > > >LUTs. My Carnot skills aren't exactly used regularly. > > > > Are Carnot skills needed? > > Not unless you're building a heat engine out of your FPGA... > > Homann Just goes to show how little my Karnaugh skills are used. Thanks for the laugh. :-)Article: 61542
Martin Euredjian wrote: > I'll have to respectfully disagree with some of what you said. That's what the newsgroup is all about. . . . > Then there's the issue of efficiency. I've taken a few very well taught > courses over the years where, within a few days, you go from a rudimentary > understanding of the subject to having a very clear and organized insight > from which to build. This isn't so much due to the verbal tradition I was > speaking of, but rather because someone who truly understands the subject > AND is a good teacher lays out the subject right there, in front of you, to > assimilate and build from. Good teachers are worth 1000 books. No doubt > about it. -- I agree that instruction from a qualified and interested expert with recent industrial experience is ideal. The practical problem is finding such an expert who is also in the business of teaching. > So, if you attend a good course, you can be on your way very quickly. It's > a matter of efficiency. And, while it might be true that all in the > universe could be learned from books and, these days, the Internet, there's > a real imporant factor we must not forget: the business equation. If what > you do is a hobby then, by all means, burn time experimenting and reading > through hundreds of documents, surfing the Web or playing with dev boards. > However, in the context of a business that needs to get product out the > door, it is much more efficient to pay someone to show you the ropes quickly > and then get on with your work. -- I agree that it makes good business sense to pay a consultant or take a course that teaches you something faster than you could learn in yourself. However, my experience with such seminars is that this just doesn't happen beyond the introductory tutorials. I set aside an hour or two a day for focused self-study, and I don't believe this has adversely affected the time it takes me to get working designs out the door. In fact I think it helps. > Let me ask you this. Do you think that spending 45 minutes listing all of > the I/O out of a DCM block has a place in an advanced class? Or how many > clocks can be distributed in a Virtex II? I agree with you. This is exactly what happens. This is where I walk out and why I no longer attend. > How about getting into how to > properly start-up a DCM with real-world issues and code? Yes. A little more *code* please. Design entry, inference, and simulation are routinely neglected. > $1,000 is a lot of money for a printed version of PowerPoint slides. I > would gladly pay $5,000 for a class that had the right content. Money is > not the issue here. If you tell me you'll teach an advanced class for $1K, > then do it. If that class requires $10K, then tell me so. Maybe other designers will post some good experiences with seminars or classes. I wish I had some to report. -- Mike TreselerArticle: 61543
news@sulimma.de (Kolja Sulimma) wrote in message news:<b890a7a.0310060516.2056fc82@posting.google.com>... <snip> > > > Two LUT's to look at two consecutive nibbles. > > > One LUT to AND the output of the above with the next most significant bit > > > (the ninth bit). <snip> > > Almost. The LUTs can't look at full nibbles. Since I need to make > > sure all bits are equal to each other, there's a "smear." I was trying to underscore that nibble checks with the 9th bit as the qualifier were not sufficient. You expand upon this below by qualifying with the [0] and [4] bits from the nibbles you looked at. > You can look at nibbles without the smear. > If you know that all bits in each of the nibbles are equal you can > select one bit for each nibble as a representant and check whether the > nibbles are equal. > > for each byte: > eq3210 <= '1' when data(3 downto 0) = "0000" or data(3 downto 0) = > "1111" else '0'; > eq7654 <= '1' when data(7 downto 4) = "0000" or data(7 downto 4) = > "1111" else '0'; > eq840 <= '1' when data(8)&data(4)&data(0) = "000" or > data(8)&data(4)&data(0) = "111" else '0'; > run_found <= eq3210 and eq7654 and eq840; > > That's three lut's and a carry chain or four luts in two levels of > logic. > > > Kolja Sulimma I appreciate the fresh perspective - I tried coding some things inline similar to what you suggested, all with sub-optimal results. Using syn_keeps on the three different variables and ANDing them together would produce a valid result much like what has been achieved already. It's too bad the nibble approach didn't convince the synthesizer to do things any different than before.Article: 61544
Lest there be any confusion, I was not commenting on the classes. I was talking about documentation being unnecessarily difficult to sort through. I am sorry if I gave the indication that I was refencing the classes. I have not taken any of the classes. Documentation is my main frustration area. Even then, _if_ I make contact with someone at Xilinx, I alomost always get a solution eventually. But wouldn'y it be cheaper if I could get the answer without that human intervention at Xilinx. Theron >>>>>>>>>>>> un-needed quote removed by archive managerArticle: 61545
> I think the frequency reference is talking about ignoring metastability > once you have used the 2 FF sync trick. The sync circuit depends on the Ah, that makes sense. Thanks rick.Article: 61546
> That's not a metastabiliy issue. It's a simple setup/hold time. Some True, thanks for catching that. Yeah, violating setup/hold doesn't automatically = metastability. I was using the word a little too liberally. "Oh your 401K doing poorly this year? Yeah that's metastability in action there."Article: 61547
Guy, this is the cheapest way to sync your incoming video (good job Rick)
and its work (I use this trick many time in the past).
But this is correct only for duty cycle of >25% (high time).
If you can't garanteed a high time of your 27MHz clock of min. 1/4 cycle,
you must create a 13.5Mhz derived from 27MHz and detect both edges of
13.5Mhz with 108MHz clk (because if your high time is to small, you have
some chance to never see it with the 108 MHz clk).
(Please view in fixed-width font, e.g. Courier)
--- --- Sync'd
Data ---------|D Q|------------------------------------|D Q|------
27 MHz --+----|> | | | Data
| --- | |
| | |
| +---------+ | |
| | --- | | |
| +--|D Q|O-+---+ | |
+----|> | | | |
--- | | |
+---------------+ --- | |
| +------------| | | |
| --- --- | --- |XOR|------|CE |
+----|D Q|-----|D Q|--+--|D Q|-----| | | |
108 MHz ------|> | |> | |> | --- |> |
--- --- --- ---
regards
fe
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F8188BD.8B5D3F31@yahoo.com...
> Guy Eschemann wrote:
> >
> > My 27 MHz signal is a single bit line, not a bus.
> > Actually it is the clock line for an 8-bit video data stream. My
> > problem is to synchronize this incoming data stream with the 108MHz
> > system clock.
> >
> > I know I could be using an asynchronous FIFO for this, but this might
> > be overkill. In order to save resources, wouldn't it be better to
> > synchronize the 27 MHz clock with my system clock (2-stage pipeline
> > should do the job), then use some logic to detect the appropriate edge
> > and use the output of the edge detector as a clock enable signal for
> > the input data FFs, which are clocked by the system clock ?
>
> Since your internal clock is 4 times the external clock, you should have
> no problem. Use the 27 MHz clock to register the data and sync the 27
> MHz clock to the 108 using two FFs. The resulting synchronized clock
> will give a rising edge between a quarter and a half period of the 27
> MHz clock and can be safely used to enable reclocking of the data. You
> should use an edge detector which will delay the clock one more quarter
> of a 27 MHz period and will still be safe.
>
> --- --- Sync'd
> Data ---------|D Q|------------------------------------|D Q|------
> 27 MHz --+----|> | --- | | Data
> | --- +------------| | | |
> | --- --- | --- | & |------|CE |
> +----|D Q|-----|D Q|--+--|D Q|----O| | | |
> 108 MHz ------|> | |> | |> | --- |> |
> --- --- --- ---
>
> View this in a monospaced font.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
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Article: 61548"Austin Lesea" wrote: > One bad review posted here does a lot of damage: and we are concerned especially > when we have hundreds of glowing reviews for the same class/instructor! Please understand that I meant this to be constructive criticism, meant to help improve things, not cause damage. Let me give you my opinion as to why you have so many glowing reviews, at least from the group I was with. In short: Corporate students. Pretty much everyone else at the class was from the same company. They had been sent out on what I like to call a "corporate training tour". It's a fun break away from the office and you get to learn something to boot. These guys took a number of courses during the same trip. At least one (and probably more) of them was fresh out of school. I had a couple of good conversations with him during breaks and realized that he did not belong in that class at all. When I asked how much FPGA experience he had, he replied that he'd just done the usual labs at school, not much more. I can't comment on every single person at the class, but you can learn a lot about them based on the questions they ask. Again, it didn't seem that they had enough time at the wheel. When the team leader is asking questions about the I/O of a DCM block in an advanced class I pretty much know that they didn't have a decent look through the VirtexII data sheet. Another couple of guys were asking about how to configure Select I/O in order to have series termination. They were also asking about good development boards, etc. In general terms, to the uninitiated, the class was wonderful. If you are too lazy to learn the basics (ok, to be fair, maybe didn't have the time?) then the class exposed you to a lot of interesting information that, if researched further, would result in valuable learning (wheen you are coming from that context). For someone without the experience this class was rocket science and you probably left in awe of all that's possible. Then there's the "I'm happy to be out of the office" effect. Everyone is happy to do that. At least when you are part of a large corporate entity and you are very detached from the financials. You'll probably get raving reviews out of this group as well. Lastly, it takes caring and ... well ... balls to say what I'm saying. What does a rank-and-file guy gain by saying that the class wasn't adequate? Zilch. As a small business owner who actually pays the bills, designs hardware, writes code, etc., etc., I'm intimately aware of the value of time and money. I came to the class with a completely different frame of reference. That's why you are not getting my stamp of approval by default, which is what I think most attendees tend to do. Thanks for looking into it, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61549
Just out of curiosity, has anyone ever used the phase-shifting capabilities of the Xilinx DCMs to implement an adaptive clocking circuit to avoid metastability? Once the clocks are in phase, what's the standard drift, i.e. how often would it be necessary to verify if the phase relationship is still right? Are there any reasons not to do this? Pierre-Olivier -- to email me, remove the obvious from my address --
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