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H. Peter Anvin <hpa@zytor.com> wrote in message news:<bo7s6b$ddg$1@cesium.transmeta.com>... > Hello, > > Does anyone happen to know of a stock FPGA prototyping board with (a) > onboard oscillator, (b) Ethernet and (c) at least 4 MB of SRAM? > > I have a need for such a board in a configuration which needs to > support a very large range of input frequencies, hence I would prefer > using SRAM; however, most boards seem to have no more than 1 MB SRAM > and the rest SDRAM... which would have to be supported as an > asychronous clock domain in order to work correctly at the low end of > the frequency range. > > -hpa http://www.xess.comArticle: 62676
Thomas Womack <twomack@chiark.greenend.org.uk> wrote: : Two common peripheral interfaces are Firewire (400Mbps or 800Mbps) and : USB2 (480Mbps). These are serial, so you've got incredibly high bit : rates on the incoming pins; significantly higher than the clock rates : of reasonable FPGAs. : Do there exist chips to convert an 800Mbps serial stream to a 50MHz : stream of 16-bit words, and what are they called? I imagine it's not : impractical to hook a couple of those and a couple of SRAMs to a : single FPGA, stream in the signal and then read out little bits of : it if you need to look in the stream for control signals. There are the UTMI Phys chips for USB, e,g. Lucent USS2X1, NEC uPD720120, Philips ISP1501 or as a system approach Cypres CY7C680XX :... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 62677
I am a user of Nedit (nedit.org) and I do a lot of Verilog coding.
When coding verilog modules, you have a module definition which takes
one form, and you have a module instantiation which takes another
form. Even with columnar copy/paste/search/replace, it can be a
tedious process to convert one to the other. Thus, I humbly offer a
Nedit macro I wrote that converts a module definition (header) to an
instantiation. Make a copy of the module definition header, paste it
where you want it, put the cursor anywhere within the copy, and then
run the macro.
Thus, if you have this:
module lut(
clock,
pixel_in,
pixel_out
);
Running the macro will produce this:
module lut(
.clock (clock),
.pixel_in (pixel_in),
.pixel_out (pixel_out)
);
You have to remove 'module' and add an instance name manually.
Please excuse if the characters don't line up in the email, but in the
editor, the port wires all line up. The macro will attempt to leave
comments alone (commas in the comments cause a bug right now), and if
more than one port name is on the same line, then it will separate
them automatically into separate lines.
Thus, this:
module lut(
clock, pixel_in, pixel_out
);
Will also be converted automatically into this:
module lut(
.clock (clock),
.pixel_in (pixel_in),
.pixel_out (pixel_out)
);
The only restriction I want to put on the macro is that I am not
legally liable for any damage caused by it. I only hope others will
find it useful. Please use it. If there are problems, I will help
people with it who want to use it. This macro has saved me incredible
amounts of time, and I know others will be pleased to have it.
Another thing I should note is that this assumes emulated tabs and
relies on $em_tab_dist.
I'm not sure what is the best form for providing the macro. Below is
a copy out of my .nedit file, but if you would like me to provide it
in a different form, please ask!
Verilog Module Instance@Verilog:Alt+1::: {\n\
# Rewind to (\n\
\n\
start = search("(", $cursor, "backward")\n\
if (get_character(start) != "(") {\n\
beep()\n\
return 0\n\
}\n\
\n\
start++\n\
\n\
# Scan for max comma column so that port variables are aligned
in a pretty column.\n\
# This detects when multiple port names are on the same line
and estimates the width\n\
# column alignment of port subsequent to the first on a
line.\n\
# NOTE: Will screw up if there are commas in comments. Will
fix later.\n\
max_col = 0\n\
last_comma = start\n\
same_line = 1\n\
pos = start\n\
set_cursor_pos(start)\n\
while (pos < $text_length) {\n\
c = get_character(pos)\n\
if (c == ")") {\n\
# quit at end of instance\n\
break\n\
} else if (c == "\\n") {\n\
# end of line means accurate column number\n\
last_comma = pos\n\
same_line = 0\n\
} else if (c == ",") {\n\
dist = pos - last_comma\n\
if (same_line) {\n\
# if this is on the same line as the last port, add
tab spacing into distance\n\
dist += $em_tab_dist\n\
}\n\
if (dist > max_col) {\n\
max_col = dist\n\
}\n\
\n\
last_comma = pos\n\
same_line = 1\n\
}\n\
\n\
pos++\n\
}\n\
\n\
\n\
# Insert a tab's worth of spacing between port name and
variable.\n\
# Then pad out to an integral tab stop.\n\
max_col += $em_tab_dist\n\
i = max_col % $em_tab_dist\n\
if (i) max_col += $em_tab_dist-i\n\
\n\
# How to break between multiple ports on same line\n\
indent = "\\n"\n\
for (i=0; i<$em_tab_dist; i++) indent = indent " "\n\
\n\
pos = start\n\
set_cursor_pos(pos)\n\
start = -1\n\
end = -1\n\
last_line = $line\n\
\n\
comment = 0\n\
star = 0\n\
\n\
while (pos < $text_length) {\n\
c = get_character(pos)\n\
\n\
if (comment == 1) {\n\
star = 0\n\
if (c == "/") {\n\
comment = 3\n\
} else if (c == "*") {\n\
comment = 2\n\
} else {\n\
comment = 0\n\
}\n\
} else if (comment == 2) {\n\
if (star && c == "/") comment = 0\n\
star = (c == "*")\n\
} else if (comment == 3) {\n\
if (c == "\\n" || c == "\\r") {\n\
comment = 0\n\
}\n\
} else if (c == "/") {\n\
comment = 1\n\
} else if (c == " " || c == "\\n" || c == "\\t" || c ==
"\\r") {\n\
end = pos\n\
} else if (c == "," || c == ")") {\n\
if (start >= 0) {\n\
# When port name is found, insert dot and
(portname).\n\
# also, insert line break when applicable\n\
\n\
if (end <= start) end = pos\n\
string = "(" get_range(start, end) ")"\n\
set_cursor_pos(start)\n\
if ($line == last_line) insert_string(indent)\n\
insert_string(".")\n\
set_cursor_pos($cursor + end - start)\n\
i = $column\n\
while (i < max_col) {\n\
string = " " string\n\
i++\n\
}\n\
insert_string(string)\n\
pos = $cursor\n\
start = -1\n\
end = -1\n\
\n\
last_line = $line\n\
}\n\
\n\
if (c == ")") break\n\
} else {\n\
if (start < 0) start = pos\n\
}\n\
\n\
pos++\n\
}\n\
}\n
Article: 62678I would recommend a LVDS receiver to convert your sinewave to a LVTTL signal. Use 2 resistors and a capacitor to bias one input at 1.2 volts and run a terminating resistor to the other input. You could also feed the signal directly to the FPGA if it has a LVDS clock input although this will give more jitter. Daniel Lang "Ted Lechman" <eastwood132@yahoo.com> wrote in message news:b89924f9.0311041104.69d352b5@posting.google.com... > I'm trying to convert a 120MHZ 1V p-p ac coupled sinewave to a LVTTL > (3.3V) format for use as a 120MHz clock signal to an FPGA. > 1. PECL Comparator - I'm trying to avoid using PECL Comparators, > because I would have to convert the PECL output to a LVTTL swing, > which just brings me back around to the original problem. > 2. "normal" comparators - I've looked through Linear Tech and other > places, and the max spec is 100MHz. Do you know of any LVTTL > comparators with specs closer to 120MHZ?????????? > 3. Transistor. There are many high frequency RF transistor with > excellent small signal gains around their bias points but lousy large > signal - DO you know of any discrete transistors that will switch > fully at 120MHz rates?? > ThanksArticle: 62679
>I'm trying to convert a 120MHZ 1V p-p ac coupled sinewave to a LVTTL >(3.3V) format for use as a 120MHz clock signal to an FPGA. >1. PECL Comparator - I'm trying to avoid using PECL Comparators, >because I would have to convert the PECL output to a LVTTL swing, >which just brings me back around to the original problem. I got burned (years ago) using a PECL-TTL level shifter. It had a normal TTL output when I wanted a CMOS signal. Worked much better when we added a CMOS gate/buffer to clean it up. I'd probably try a fast CMOS inverter. AC couple your signal in and feed a 1 megohm resistor from the output back to bias the input. Got a couple spare pins on your FPGA? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62680
Timothy Miller wrote:
> I'm not sure what is the best form for providing the macro.
Rather not the way you do. Please write a subroutine (ie
define function_name {
}
)
and just call it in the menu entry (function_name()).
BTW, I only looked quickly on the macro and it looks rather
complicated. Notice that you probably would better use arrays in
combination with the split() function. (What NEdit version do you
have? - latest would be 5.4)
Moreover, for sharing macro functions, coming to nedit.org or Niki
would be nice, too :-)
Cheers,
Jörg
--
Niki -- The NEdit WiKi:
http://www.nr.no/~joachim/Niki/
Article: 62681Daniel, Of, if it is has an SSTL or HSTL or GTL input (which has a reference voltage) you have the high speed comparator already built in to your FPGA. Austin Daniel Lang wrote: > I would recommend a LVDS receiver to convert your sinewave to > a LVTTL signal. Use 2 resistors and a capacitor to bias one > input at 1.2 volts and run a terminating resistor to the other > input. > > You could also feed the signal directly to the FPGA if it has > a LVDS clock input although this will give more jitter. > > Daniel Lang > > "Ted Lechman" <eastwood132@yahoo.com> wrote in message > news:b89924f9.0311041104.69d352b5@posting.google.com... > > I'm trying to convert a 120MHZ 1V p-p ac coupled sinewave to a LVTTL > > (3.3V) format for use as a 120MHz clock signal to an FPGA. > > 1. PECL Comparator - I'm trying to avoid using PECL Comparators, > > because I would have to convert the PECL output to a LVTTL swing, > > which just brings me back around to the original problem. > > 2. "normal" comparators - I've looked through Linear Tech and other > > places, and the max spec is 100MHz. Do you know of any LVTTL > > comparators with specs closer to 120MHZ?????????? > > 3. Transistor. There are many high frequency RF transistor with > > excellent small signal gains around their bias points but lousy large > > signal - DO you know of any discrete transistors that will switch > > fully at 120MHz rates?? > > ThanksArticle: 62682
Hello all. I am involved in a project where I need to provide a DVI display of a camera input. Here are the technical specs of the matter: I have a 125 Hz frame rate camera coming in to my FPGA. The camera resolution is 640x480. It has the usual vsync and hsync signals, with dead time in some spots. A typical camera. On the other end, I have to feed a DVI display with a native resolution of 1280x1024 and an optimal refresh rate of 60 Hz. A typical DVI display. At the moment I simply want to display the camera data in the upper left corner (640x480) and just write black pixels for the rest of the screen. So I am not worried about image resizing functions. The main problem lies in crossing the clock domain for the system. For use as video buffers I have 2-2MB SRAM's external to the FPGA. I currently have an implementation where I read from one memory while writing to the other memory. When I have read an entire frame of data, I switch the memory operations. I begin reading at the beginning of the new read memory and write to the what would be the next memory location in the new write memory. Therefore, part of the memory is one frame behind the current frame. This does not cause a problem with the display until I move the camera. At this point the image tears (a bad white line) throughout the image until the motion stops. This can be very annoying and I need to prevent this from happening. I am wondering if anyone has completed a camera to display conversion successfully using simple frame buffers or if anyone has any suggestions on techniques to try. Logic use is not a problem, as I am currently only using 5% of the V-II Pro. Thank you for your assistance. ~ScottArticle: 62683
Is the line in your 640x480 source signal when the camera moves? Are you moving the camera with a motor? Does the line come from cross talk from the motor? Are your cables shielded? Try moving the camera manually (you may need to disconnect the motor), is the line still there? If no, you better find a person who is good at EMI/Cross talk issues Are you moving the camera manually? Do the vents get blocked and the camera control unit heat ups (happened to me once - someone set paper on top of the camera control unit)? Are you synchronizing the signals that handshake the buffer trade-off since the cross clock domains? Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Scott Connors wrote: > Hello all. > > I am involved in a project where I need to provide a DVI display of a > camera input. Here are the technical specs of the matter: > > I have a 125 Hz frame rate camera coming in to my FPGA. The camera > resolution is 640x480. It has the usual vsync and hsync signals, with > dead time in some spots. A typical camera. > > > On the other end, I have to feed a DVI display with a native > resolution of 1280x1024 and an optimal refresh rate of 60 Hz. A > typical DVI display. > > At the moment I simply want to display the camera data in the upper > left corner (640x480) and just write black pixels for the rest of the > screen. So I am not worried about image resizing functions. > > The main problem lies in crossing the clock domain for the system. > For use as video buffers I have 2-2MB SRAM's external to the FPGA. I > currently have an implementation where I read from one memory while > writing to the other memory. When I have read an entire frame of > data, I switch the memory operations. I begin reading at the > beginning of the new read memory and write to the what would be the > next memory location in the new write memory. Therefore, part of the > memory is one frame behind the current frame. > > This does not cause a problem with the display until I move the > camera. At this point the image tears (a bad white line) throughout > the image until the motion stops. This can be very annoying and I > need to prevent this from happening. > > I am wondering if anyone has completed a camera to display conversion > successfully using simple frame buffers or if anyone has any > suggestions on techniques to try. > > Logic use is not a problem, as I am currently only using 5% of the > V-II Pro. > > Thank you for your assistance. > > > ~ScottArticle: 62684
Wolfgang, Reset alone does not do it. You have to monitor LOCKED. If you don't achieve lock within a certain period of time (see data sheets for worst case) you hit the DCM with a RESET again and go wait for lock one more time. Repeat as needed. There are other status bits that will give you more information as to what is happening with the DCM or its input. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "wolfgang" <wolfgang.hofmann@arcs.ac.at> wrote in message news:bo879p$dip$1@newsreader1.netway.at... > hey! > > i'm using a virtex2 device for implementing a lvds channel link receiver. To > recover the bitclock from the incoming clock- line, i use a dcm with > feedback on clk0. > > constant lvds_clk_m : integer := 7 ; > constant lvds_clk_d : integer := 2 ; > constant lvds_phase_mode : string := "FIXED" ; > constant lvds_phase_value : integer := 45 ; -- phase shift value for > place and route > constant lvds_phase_value_udsim : integer := 45 ; -- phase shift value for > unit delay simulation > > attribute CLKIN_PERIOD of dcm_3_5_lvds_clk: label is "30" ; > attribute CLKOUT_PHASE_SHIFT of dcm_3_5_lvds_clk: label is > lvds_phase_mode ; > attribute PHASE_SHIFT of dcm_3_5_lvds_clk: label is > lvds_phase_value ; > attribute CLKFX_DIVIDE of dcm_3_5_lvds_clk: label is lvds_clk_d ; > attribute CLKFX_MULTIPLY of dcm_3_5_lvds_clk: label is lvds_clk_m ; > attribute DUTY_CYCLE_CORRECTION of dcm_3_5_lvds_clk: label is "TRUE" ; > attribute DFS_FREQUENCY_MODE of dcm_3_5_lvds_clk: label is "LOW"; > > > the incoming clock is a 33 MHz clk with 57% to 43% dutycycle. > > when i disconnect the clock line and plug it in again, the dcm doesn't lock > again. i tried to reset the dcm at the falling edge of the locked pin to > ensure a defined startup, but this seems to have no effect. > > now my question: what can i do, to reset the dcm after an interruption of > input clock clkin? is there a specific sequence of actions if have to > execute? > > regards > > wolfgang > > > >Article: 62685
1. Design entry
Tool1: emacs vhdl-mode, verilog mode
Tool2: Quartus block diagram
2. Simulation
Tool1: Modelsim
Tool2: Aldec
3. Synthesis
Tool1: Leo Spec
Tool2: Synplify Pro
Tool3: Quartus
Tool4: XST
4. Place and Route
Tool1: Xilinx Place & Route + static timing
Tool2: Quartus Place & Route + static timing
-- Mike Treseler
Article: 62686Another area to research could be electric circuit simulation (ie Spice). There are similarities: each circuit node can influence every other (at least potentially). Spice basically revolves around inverting a mega-matrix. There's been quite a lot of work put into building hardware accelerators for Spice. You may be able to leverage off that. antti@case2000.com (Antti Lukats) wrote: :"mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote in message news:<bo4na0$5qk$1@tomahawk.unsw.edu.au>... :> Hello all, :> :> Firstly I would like to say that other than knowing what a FPGA is on a most :> basic level my knowledge about the subject is nil. I am looking at this :> from an application that needs a solution. I have seen about the place add :> on boards for PC's that act as co-processors. This is the interesting bit :> to me. Our research group is looking into building a computer (cluster :> perhaps) for calculation of particle dynamics, similar to CFD in :> application. Our programs are in C/C++ running on Linux ( any flavour will :> do). : :in München, Germany there is a research group that uses Xilinx a lot :they do some 'particle' search I think FPGAs are mostly used to filter :out the data coming from then experiment. as you are also in heavy :research area maybe good idea to contact them - I have no addresses :but there are not so many nuclear labs so the one I mentioned should :be easy to find for you : :anttiArticle: 62687
Hi Scott,
I think the problem is that when you swap RAM banks, your camera can
have written a partial frame to the write memory. This is fine when the
camera's still, because the data are identical to the last frame, but when
the camera's moving it's gonna go wrong and leave artifacts. You'll have
half of an old frame with half of a new frame in the buffer.
Try this. As the write frame rate is > 2x the read frame rate, when
you swap read banks, wait for the start of the next write frame then write
that into the write buffer. Then stop writing until the frame read cycle is
complete. Then swap banks and start all over again.
HTH, Syms.
"Scott Connors" <scott.a.connors@boeing.com> wrote in message
news:5f825c95.0311041425.58c6ac6e@posting.google.com...
> Hello all.
>
> I am involved in a project where I need to provide a DVI display of a
> camera input. Here are the technical specs of the matter:
>
> I have a 125 Hz frame rate camera coming in to my FPGA. The camera
> resolution is 640x480. It has the usual vsync and hsync signals, with
> dead time in some spots. A typical camera.
>
>
> On the other end, I have to feed a DVI display with a native
> resolution of 1280x1024 and an optimal refresh rate of 60 Hz. A
> typical DVI display.
>
> At the moment I simply want to display the camera data in the upper
> left corner (640x480) and just write black pixels for the rest of the
> screen. So I am not worried about image resizing functions.
>
> The main problem lies in crossing the clock domain for the system.
> For use as video buffers I have 2-2MB SRAM's external to the FPGA. I
> currently have an implementation where I read from one memory while
> writing to the other memory. When I have read an entire frame of
> data, I switch the memory operations. I begin reading at the
> beginning of the new read memory and write to the what would be the
> next memory location in the new write memory. Therefore, part of the
> memory is one frame behind the current frame.
>
> This does not cause a problem with the display until I move the
> camera. At this point the image tears (a bad white line) throughout
> the image until the motion stops. This can be very annoying and I
> need to prevent this from happening.
>
> I am wondering if anyone has completed a camera to display conversion
> successfully using simple frame buffers or if anyone has any
> suggestions on techniques to try.
>
> Logic use is not a problem, as I am currently only using 5% of the
> V-II Pro.
>
> Thank you for your assistance.
>
>
> ~Scott
Article: 62688Thanks for all the support guys, Ive carefully studied the threshold voltages of my various 5V devices and found the margins too small for driving with 3.3V. I am forced to use 74LVX4245 / 74LVX3245 devices for interfacing. Although its extra components on the board, i'd feel safer using the translators, especially when the design matures and we can move towards greater speed increases using clock multiplication, etc. Thanks for all the suggestions. Lockie. "Peter Alfke" <peter@xilinx.com> wrote in message news:3FA7E9E3.F9DD1AF0@xilinx.com... > Regarding 95288XL: > > Input: > The pins are 5-V tolerant, so you can drive a full-swing 5 V signal into > the input. > > Output: > When used as an output, it obviously only drives up to the 3.3 V rail. > If your 5-V device uses "TTL" thresholds, it only requires a Vih of 2.4 > V, so there is no problem. If your 5-V device has "CMOS" thresholds, you > need a pull-up resistor, and you also need to 3-state the CPLD outputs > (otherwise the pull-up transistor will conduct current backwards and > clamp the pin to Vcc anyhow.) > > You may want to read about a circuit trick that speeds up the pull-up, > and has been very successful in FPGAs. This is from TechXclusives "Six > Easy Pieces" on the Xilinx website, where you also find the simple > schematic : > > " 5. Driving a 5V Signal from a 3.3V Output > > When a CMOS-level 5V input is driven, the output High voltage from a > 3.3V device is marginal. If the 3.3V output is 5V tolerant, a pull-up > resistor to 5V can pull the output that is in a 3-state condition all > the way to 5V. The problem is the slow rise time of tens or hundreds of > nanoseconds, which is caused by the capacitive load. This circuit > greatly reduces the rise time by keeping the active pull-up engaged > until the output voltage has passed the threshold voltage of ~1.6V. > Slowing down the internal input signal and 2-input AND gate will speed > up the rise time even more. " > > I have never implemented this in a CPLD, but it might work there also. > > Peter Alfke > > > > >Article: 62689
Hi folks, Just want to make sure of something - the VCCO and VCCJ supply voltages for PlatformFlash - I expect these must match the VCCO of the FPGA IO bank to which they are connected? The xc2v1000-fg456 has the D0 pin on bank 4, which I'm running with VCCO_4 at 2.5V. So, I connect the PlatFlash VCCO and VCCJ to 2.5V right? Any errors there? Is there a full datasheet for these parts? So far I've only found something labelled "Preliminary Product Specification"... Thanks, JohnArticle: 62690
Gentlemen:
My employers would like to upgrade from an ABEL compiler and some rather
rudimentary hardware programming capabilities to a more advanced
compiler programming a varied field of programmable devices including
EEPROMs, PLDs, CPLDs and FPGAs from various manufacturers. They
would like to program in ABEL, Verilog & VHDL (or any compatible
language set).
I'm not sure where to go to make inquiries about this
kind of compiler. I know where to go to get a free compiler
of this sort, if I were willing to live with Xilinx only
products, but when I floated this past my employers they
got grumpy about the shortage of generality.
Any pointers describing where to get this software
& its price (though price is not much of a roadblock)
would be deeply appreciated.
Thanx in advance,
2Penny
--
2Penny putting in his 2 cents worth
"Giving money and power to government is like
giving liquor and car keys to teenage boys." - P J O'Rourke
Article: 62691Another way could be to construct a big frame fifo using the 2x2M srams you have. Since you cross clock boundaries, you need to construct an async. fifo. Hint to fifo construction: 1. ping-pong between two srams 2. an ififo(xilinx internal) for camera input 3. an ofifo(xilinx internal) for dvi output 4. counters on each end to keep tracking pixel flows ---Bob "Scott Connors" <scott.a.connors@boeing.com> wrote in message news:5f825c95.0311041425.58c6ac6e@posting.google.com... > Hello all. > > I am involved in a project where I need to provide a DVI display of a > camera input. Here are the technical specs of the matter: > > I have a 125 Hz frame rate camera coming in to my FPGA. The camera > resolution is 640x480. It has the usual vsync and hsync signals, with > dead time in some spots. A typical camera. > > > On the other end, I have to feed a DVI display with a native > resolution of 1280x1024 and an optimal refresh rate of 60 Hz. A > typical DVI display. > > At the moment I simply want to display the camera data in the upper > left corner (640x480) and just write black pixels for the rest of the > screen. So I am not worried about image resizing functions. > > The main problem lies in crossing the clock domain for the system. > For use as video buffers I have 2-2MB SRAM's external to the FPGA. I > currently have an implementation where I read from one memory while > writing to the other memory. When I have read an entire frame of > data, I switch the memory operations. I begin reading at the > beginning of the new read memory and write to the what would be the > next memory location in the new write memory. Therefore, part of the > memory is one frame behind the current frame. > > This does not cause a problem with the display until I move the > camera. At this point the image tears (a bad white line) throughout > the image until the motion stops. This can be very annoying and I > need to prevent this from happening. > > I am wondering if anyone has completed a camera to display conversion > successfully using simple frame buffers or if anyone has any > suggestions on techniques to try. > > Logic use is not a problem, as I am currently only using 5% of the > V-II Pro. > > Thank you for your assistance. > > > ~ScottArticle: 62692
I've got a design for a $40 assembled and tested fpga dev board that is on a pci card for use in a standard PC (probably running linux). It would have ethernet and some other ports for experimentation, but basically the fpga would become a configurable pci device. Possible applications could be mpeg encoding/decoding, encryption/decryption, or just plain experimentation with fpga technology. I'm debating whether to do a production run of these things, but if they won't sell I don't want to bother. Would anyone consider buying such a thing?Article: 62693
Philip Freidin <philip@fliptronics.com> wrote in message news:<2hseqvsmbtbs1o23kedfpbjsucv884m80f@4ax.com>... > On Mon, 3 Nov 2003 16:05:52 +1100, "mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote: > >Hello all, > > Hi Mike, > > >Firstly I would like to say that other than knowing what a FPGA is on a most > >basic level my knowledge about the subject is nil. I am looking at this > >from an application that needs a solution. I have seen about the place add > >on boards for PC's that act as co-processors. This is the interesting bit > >to me. Our research group is looking into building a computer (cluster > >perhaps) for calculation of particle dynamics, similar to CFD in > >application. Our programs are in C/C++ running on Linux ( any flavour will > >do). > > So that we may better help you, please answer the following questions: > > Is the arithmetic Floating Point (FP) or Integer? > > If mixed, what is the ratio of the two? > (i.e. 10000 integer ops to every floating point op) > (If the ratio is greater than 100000:1, could you do the integer > stuff in the FPGAs, and the FP in a host X86 processor?) > rest snipped Alot of really good points covered by Philip and also above posts. Its clear that many FPGA pros would like to get their grubby hands on such a project as long as it pays ofcourse. I can only wish there were more of these projects but its a bit off the normal path. I am going to suggest instrumenting the code to find out the answers unless its obvious by inspecting the code. The FP question is paramount though. Alot of DSP written in C often uses lazy math because the FP is basically free. If you were to largely eliminate FP the way we used to > 20yrs ago, you can often get just as good a result and get a much better understanding of whats really important and where precision & dynamic range are really needed and where its wasted. In the DSP world, 16-18bits has proven to be adequate for most tasks as long as special care is taken to keep signals in range. Many algorithms can block up the range so only one exponent is needed for a whole group of points, and this exponent can be as little as a common divide by 1,2,4 etc in the FFT case. I suspect it won't be as easy for your problem. As an aside, most cpus don't even perform integer math very well for DSP tasks, for instance when rounding, many uninformed programmers will use >> to do division by 2^N not realizing this introduces roundoff errors biasing the signed signal to negative. To do it correctly requires more integer ops to check for msbs & lsbs etc but it reduces the need for extra width and can bring the results much closer to an all FP result converted back to same size int. One approach I used to turn a Wavelet algorithm into RTL HW was to rewrite the original C code along with the Matlab guy so that the main engine module called small C functions to eval each and every operator, *s +s, /s, and even movs etc. These could also tally the use counts and do more precise math on words that might be odd bit widths. My busses were 17,18 & 37bits wide. By tweaking the widths of various operators we could reduce the cost of HW func blocks to an acceptable value in an ASIC. When Dr Matlab was happy with the C code, all the funcs were easily turned into equiv Verilog (or VHDL) modules, params became ports. The operator counts are needed to design suitable datapaths with fixed/variable arithmetic units. The C program that had been calling these funcs in a C dataflow was then used to construct a FSM to arrange for data to keep moving between the various arithmetic modules/funcs and multiple memories. It gets harder because the HW is 10 stages of overlapping pipelines, very difficult to express in C HDL. Even still it took 6months just to get from Fortran-C to RTL Verilog. Ofcourse the C & Verilog results were identical and very close to FP Matlab model. Since Sharcs, Transputers & Occam were mentioned, I would mention that the ADI links on the Sharcs (& TI chips IIRC) are a variation of the Transputer links that supported Occam channels across multiple cpus. If only a modern Transputer existed that was comparable to todays embedded cpus/DSPs. KROC anyone? Then it would be perfectly reasonable to build the project in Occam or C-CSP and spread it accross as many tightly coupled cpus as needed. The resulting code will be HW like but with alot less pain and could also lead to HW synthesis (HandelC). I happen to be working on such a Uber Transputer plus compiler but its still some ways off. The native programming language for this is V++ or Verilog + C + Occam + asm all rolled into one (horrid) language. A mini version of SystemVerilog but tuned to run natively on the event/process scheduler already in the cpu. The Verilog part allows HW to be described directly either behavioural, dataflow, RTL and most of that remains synthesizeable if written so. Processes can be engineered back & forth between synthed HW (coprocessors) & SW if cpu is in FPGA. Some might call this a HW accelerator on the cheap or a simulation engine, but thats like calling conventional cpus Turing accelerators. The Occam part is just the !? alt,par,seq,chan model in C syntax. The underlying scheduler is not so different from the HW event timing wheel. The C part adds data types and allows conventional seq programming and importing of code. Asm touches the HW directly. The compiler is based on the lcc design. I am curious to know what folks think of combining HDL,CSP,C rather than keeping HW & SW miles apart as in conventional engineering. regards John johnjaksonATusaDOTcom (ignore yahoo)Article: 62694
"The Big Bear" <thebigbear@myrealbox.com> wrote in message news:boa1ua$1cison$1@ID-6883.news.uni-berlin.de... > I've got a design for a $40 assembled and tested fpga dev board that is > on a pci card for use in a standard PC (probably running linux). It would > have ethernet and some other ports for experimentation, but basically the > fpga would become a configurable pci device. Possible applications could be > mpeg encoding/decoding, encryption/decryption, or just plain experimentation > with fpga technology. I'm debating whether to do a production run of these > things, but if they won't sell I don't want to bother. Would anyone > consider buying such a thing? I would happily buy one. RalphArticle: 62695
Hi, to install your own exception handler routines for the microblaze, you have to use some library functions. The prototypes are located in the file "xexception_l.h", but just including this file doesn't work. How can I get this headerfile into the include directory of the microblaze directory automatically (when generating the libraries? TIA, FrankArticle: 62696
> I would happily buy one. > > Ralph > I would too. But as long as it is not shipped by UPS. I would cost more than that to ship to Australia. Documentation would be important as in this case I am a bit thick. MikeArticle: 62697
The Big Bear wrote: > I've got a design for a $40 assembled and tested fpga dev board that is > on a pci card for use in a standard PC (probably running linux). It would > have ethernet and some other ports for experimentation, but basically the > fpga would become a configurable pci device. Possible applications could be > mpeg encoding/decoding, encryption/decryption, or just plain experimentation > with fpga technology. I'm debating whether to do a production run of these > things, but if they won't sell I don't want to bother. Would anyone > consider buying such a thing? What FPGA? LeonArticle: 62698
XILINX - ISE 6.1.02 - Modelsim 5.7 SE In verilog I described my top module as follows: module BoothMult (ck, load, ...) parameter N=4; I used testbench waveform to generate the testbench and I obtained: module tbbooth; ... defparam UUT.N = 4; BoothMult UUT ( .ck(ck), ... obviously it is ok pre-synthesis but not post (N parameter doesn't exist anymore). It seems to me this is a software bug, please let me know if I'm wrong. luigiArticle: 62699
Hello all,
While synthesysing the verilog module to generate clock of 12.5MHz
from the default clock of XSA100 i.e 50MHz in ISE WebPack for
XC2S100-TQ144 Spartan-II FPGA, I am getting an error. I have two
inputs clock and reset and one output out.
Here I go step by step:
i) Synthesis verilog code
No error but the following warnings:
=========================================================================
* HDL Synthesis
*
=========================================================================
Synthesizing Unit <fulladd28>.
Related source file is ddfs.v.
WARNING:Xst:646 - Signal <sum<26>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<25>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<24>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<23>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<22>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<21>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<20>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<19>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<18>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<17>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<16>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<15>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<14>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<13>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<12>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<11>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<10>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<9>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<8>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<7>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<6>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<5>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<4>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<3>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<2>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<1>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<0>> is assigned but never used.
INFO:Xst:1304 - Contents of register <sum<27>> in unit <fulladd28>
never changes during circuit operation. The register is replaced by
logic.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <clock> is never used.
Unit <fulladd28> synthesized.
=========================================================================
ii) Implement design
works fine. But I am only seeing the signal out and not the clock and
reset in the Pad Reports.
iii) Constraining the Fit:
Create new Source (by right clicking on the verilog code
file)Implementation constraints file..
iv) Open Xilinx Pace by clicking "Assign package pin". It gives a
message
"Top Level Block has pins that are not connected to any signals. Do
you want them to treat them as user I/O?"
I click "Yes"
v) Then I assign the pins P93 to reset, P88 to clock, P67 to out. And
save it.
vi) Now when I click "Pad Report" to view the pin Assignment it gives
me the following error;
****************************************************************************
Annotating constraints to design from file "ddfs.ucf" ...
ERROR:NgdBuild:755 - Line 2 in 'ddfs.ucf': Could not find net(s)
'reset' in the
design. To suppress this error use the -aul switch, specify the
correct net
name or remove the constraint.
ERROR:NgdBuild:756 - Line 3 in 'ddfs.ucf': Could not find net(s)
'reset' in the
design. To suppress this error specify the correct net name or
remove the
constraint.
ERROR:NgdBuild:755 - Line 6 in 'ddfs.ucf': Could not find net(s)
'clock' in the
design. To suppress this error use the -aul switch, specify the
correct net
name or remove the constraint.
ERROR:NgdBuild:756 - Line 7 in 'ddfs.ucf': Could not find net(s)
'clock' in the
design. To suppress this error specify the correct net name or
remove the
constraint.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"ddfs.ucf".
Writing NGDBUILD log file "fulladd28.bld"...
ERROR: NGDBUILD failed
Reason:
Completed process "Translate".
*******************************************************************************
here is the verilog code:
*******************************************************************************
`timescale 1ns/1ps
module fulladd28(out,clock,reset);
parameter a=28'd67108864;
parameter w = 28; // bit width of phase accumulator
output out;
input clock, reset;
reg [w-1:0] sum;
always @(posedge clock or posedge reset)
if(reset)
sum <= 0;
else
sum <= +a;
assign out = sum[w-1];
endmodule //end of module fulladd28
*******************************************************************************
Can anyone please guide me why is the error and how to remove it?
Sorry for bothering such a massy e-mail.
Thanks and Regards
Atif
Research Associate
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