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I suggest you use ACTEL's pro-asic plus devices. It protects your IP and does not need a battery. It is FLASH based technology. "JP Nicholls" <jpnicholls@pwav.com> wrote in message news:d61fddc5.0305090056.5f335fc2@posting.google.com... > We want to use the encrypted bitstream option of a Xilinx FPGA in order > to protect IP. However we are having trouble sourcing a suitable battery. > > Our product needs to have a shelf life of 10 years plus. The customer might > stick the unit on a shelf in a cold dark warehouse and not use the product for > several years, but it must still work. If it fails on operation that has very > expensive consequences for our customers - and us. > > Has anybody found a suitable battery for this? > > Are there any alternative way to encrypt the FPGA bitstream? The bitstream and > any keys must not be accessible to any probes. > > Many thanks, > > -- > JP Nicholls / jpnicholls@pwav.com > > Digital design engineer > > Powerwave UK Ltd > Embassy House > Queen's Avenue > Bristol, BS8 1SB > United Kingdom > > Tel: +44 (0)117 910 5600 > Fax: +44 (0)117 910 5601 > Web: http://www.powerwave.com > ___________________________________Article: 55476
I am planning to write a tutorial on FPGA-programming for students. As an excercise I would like the students to "program" a very simple logic function using an interactive representation of an FPGA. Due to limitited display size the graphical representation of the FPGA has to be very simple. Now I'm searching for detailed information about the interconnect structure of FPGAs using antifuses. How are the in-/output pins connected to the relating CLBs? I haven't found anything yet. Can anyone help me?Article: 55477
of course I have my own suggestion: http://www.jopdesign.com/cyclone/ but take a look at: http://www.fpga-faq.com/FPGA_Boards.htm a long list of different boards, Martin "Giando" <GOTEB@katamail.com> schrieb im Newsbeitrag news:1402ce4.0305090536.2dd72fa@posting.google.com... > Hi I'm a PhD student and have to buy a fpga development kit(board, > chip, and software) that will be used by students of Electonic > Engineer. I need a little suggest about it. The development kit must > be simple to use for programming and debug and not very expensive. I'd > like that the software included was able to simplify the configuration > of the connections of the board and that the debug of the chip could > be done by the software. > An Altera reseller proposed me the Nios development kit, but I think > it is difficult to use for the students. What do u think about it? > There is a good product by Xilinx? > Thanks for the answer.Article: 55478
JP Nicholls <jpnicholls@pwav.com> wrote: > We want to use the encrypted bitstream option of a Xilinx FPGA in order > to protect IP. However we are having trouble sourcing a suitable battery. Just about any lithium battery has a life of 10 years. You just need to pick the size you need. How much current do you need -- http://inquisitor.i.am/ | mailto:inquisitor@i.am | Ian Stirling. ---------------------------+-------------------------+-------------------------- 'Where subtlety fails, we must simply make do with cream pies' -- David BrinArticle: 55479
FPGA user wrote: > Thanks, both of you, for responding. > > I can't use a constant vector because I just don't have the room. You can infer a rom into blockram using leo, synplicity or quartus synthesis. > I called Altera last night, and after being on hold for a half hour, gave up > and went on the web site to file a report. There, the system had forgotten > me and I had to reregister to use it. This is one reason I prefer synthesis to device specific cores. -- Mike TreselerArticle: 55480
"Wolfgang Schmiesing" <wolfgang@byke.com> schrieb im Newsbeitrag news:eb5a527f.0305090707.520af32@posting.google.com... > I am planning to write a tutorial on FPGA-programming for students. > As an excercise I would like the students to "program" a very simple > logic function using an interactive representation of an FPGA. Due to > limitited display size the graphical representation of the FPGA has to > be very simple. > > Now I'm searching for detailed information about the interconnect > structure of > FPGAs using antifuses. How are the in-/output pins connected to the I would concentrate too much on this technology specific stuff. For the designer its in most cases not important to know about this details. Especially for the students, IMHO its more important to get a basic feeling what FPGA means. And, as other already noted, to see that VHDL/Verilog/whatever ISNT just another programming language like C/Pascal/Whatever. Its a Hardware description language, and desiging logic is different from designing (classic) software. > relating CLBs? I haven't found anything yet. Can anyone help me? Have a look into the datasheets of Spartan-II/Virtex-II. The offer plenty of information, almost too detailed for beginner students cource. I would concentrate too much on thisArticle: 55481
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3EBB2623.DD99ACBD@yahoo.com... > Anyone getting the 384 parts at a price that is more in line with the > size and IO count, like under $30? I can use the 256 parts if I don't > mind cutting the IO and cell count down to the exact number I estimate. > I just don't like the idea of not leaving room for errors or future > design changes. But there is no way I can justify a 4X price > differential on a part that is 50% larger and 20% more IO. Rickman, have a look in the archive. This topic has been discussed detailed a while ago. -- MfG FalkArticle: 55482
On 9 May 2003 08:07:54 -0700, wolfgang@byke.com (Wolfgang Schmiesing) wrote: >I am planning to write a tutorial on FPGA-programming for students. >As an excercise I would like the students to "program" a very simple >logic function using an interactive representation of an FPGA. Due to >limitited display size the graphical representation of the FPGA has to >be very simple. > >Now I'm searching for detailed information about the interconnect >structure of >FPGAs using antifuses. How are the in-/output pins connected to the >relating CLBs? I haven't found anything yet. Can anyone help me? Have you considered a SRAM based FPGA? I think these would be more appropriate for an educational setting, as the students can actually program/reprogram them over and over. Altera and Xilinx both have University support programs that will help you. Philip Freidin Philip Freidin FliptronicsArticle: 55483
On 9 May 2003 06:36:47 -0700, GOTEB@katamail.com (Giando) wrote:
>Hi I'm a PhD student and have to buy a fpga development kit(board,
>chip, and software) that will be used by students of Electonic
>Engineer. I need a little suggest about it. The development kit must
>be simple to use for programming and debug and not very expensive. I'd
>like that the software included was able to simplify the configuration
>of the connections of the board and that the debug of the chip could
>be done by the software.
Both Altera and Xilinx have University support programs that can
supply you software, trainng material, and probably boards.
Check out their web sites:
http://www.xilinx.com/univ/index.htm
http://www.altera.com/education/univ/unv-index.html
>An Altera reseller proposed me the Nios development kit, but I think
>it is difficult to use for the students. What do u think about it?
>There is a good product by Xilinx?
>Thanks for the answer.
I agree that starting out with Nios is probably not the way to go.
I would suggest simple gates and flip flops with schematics first,
then migrate into VHDL/Verilog.
Philip
Philip Freidin
Fliptronics
Article: 55484Wolfgang Schmiesing wrote: > I am planning to write a tutorial on FPGA-programming for students. > As an excercise I would like the students to "program" a very simple > logic function using an interactive representation of an FPGA. Due to > limitited display size the graphical representation of the FPGA has to > be very simple. Back in the 80's DataIO published fuse map grids where you could see what all the fuses did on small devices like the 22V10. But even this was was too complicated for a tutorial. It might be more useful to students to demonstrate a simple hdl synthesis and show the resulting schematic views. Very few designers look directly at the "fuse" level anymore. > Now I'm searching for detailed information about the interconnect > structure of > FPGAs using antifuses. How are the in-/output pins connected to the > relating CLBs? I would be surprised if the Actel web site didn't have this. -- Mike TreselerArticle: 55485
JP Nicholls wrote: > We want to use the encrypted bitstream option of a Xilinx FPGA in order > to protect IP. However we are having trouble sourcing a suitable battery. > Our product needs to have a shelf life of 10 years plus. I don't think there is such a battery. You need to at least provide some way for the customer to reload the keys after replacing the battery. Maybe stash the keys in flash and have the uP reload stealthily on some date related command. You also have to consider whether this level of security is worth the bother to your customers. Remember that bitstream encryption has zero value for them. -- Mike TreselerArticle: 55486
Jim Granville wrote: > > rickman wrote: > > > > I am looking at the larger CPLDs and there seems to be a price wall > > between the 256 and 384 macrocell parts. Both the Xilinx and Lattice > > parts have about the same features and functionality and the same > > significant price jump. The XCR3256XL in the 256 BGA package is about > > $15 in moderate quantity. But the XCR3384XL in the same package is over > > $60!!! The same disparity (although not quite as large) exists in the > > Lattice LC4 line. > > > > Anyone getting the 384 parts at a price that is more in line with the > > size and IO count, like under $30? I can use the 256 parts if I don't > > mind cutting the IO and cell count down to the exact number I estimate. > > I just don't like the idea of not leaving room for errors or future > > design changes. But there is no way I can justify a 4X price > > differential on a part that is 50% larger and 20% more IO. > > > > If I get really tight, I might just consider the Lattice 384 cell part > > since it is much cheaper than the Xilinx part. But it will bug the heck > > out of me to pay the price. > > You could use two smaller parts ? - We've done that in the past. No, I would certainly have done that if it was practical. I have considered using the 256 part along with a 32 or 64 part, both of which are very cheap. But board space is a problem. There are a bunch of unused pins on the LC4256 in a 256 pin BGA. Adding another package to give me more pins that don't connect internally to the others has limited advantage and uses valuable board space. > Or, maybe move away from the bleeding-edge of a family. I'm not sure what this means. What family and what edge are you referring to? > Lattice made this claim in July 2002, you could check into : > ( this family goes 256/512/768/1024, so 256/512 is at the small end of > the ruler :) > > > Price and Availability > > The ispXPLD 5512MX in the 1.0mm ball pitch, 484 fpBGA package will sample later this quarter > >with initial production scheduled for Q4. Pricing for the ispXPLD 5512MC in volumes of >1000 > >pieces starts at $17.75. Additional members of the ispXPLD 5000MX family are expected to be > >released over the coming year. > > -jg I remember looking at the XPLD parts and there is something about them that does not fit the socket. I remember now. It was the price... Avnet Lattice Semiconductor LC5512MV-75F256C Description: 512MC, 196 I/O, ispJTAG, 3.3V, min 90 - mult 90 25 - 99 @ $103.4000 100 - 999 @ $82.7750 As to being at the "small" end of the family, so far the 512 is the *only* part they even list ordering info for in the data sheet! It may be awhile before this is an economy part. I would *love* to use this part. Perhaps this is *prototype* pricing only. I could use the 256 part except it does not have enough IOs. I wonder how nicely I would have to ask to get the price down from $83 to $20??? :) Right now I am trying to get their LC4384B for $20 and I don't expect to get it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55487
Ziad, Very helpful post. Thanks for the information. Regards, Mike zabulebdeh@yahoo.com (Ziad Abu-Lebdeh) wrote in message news:<f784b02b.0305030620.46ce53e3@posting.google.com>... > Mike, > > The Stratix board I was talking about will work as an add-on card in > that backplane if the backplane meets the PCI standard. If you want > to make it a Host card, then you will have to do some soldering. You > can use the 64-bit signals on the Stratix card to just solder jumpers > to any pin on the 32-bit side of the connector. This should be enough > for you to get REQ, GNT and the interrupt pins to work. You will have > to make sure you do very clean soldering and keep the wires as short > as you can. > > For the clock, get a shielded wire that you can solder a ground with > it on both ends. You can just put a wire between one of the clock > crystals on the board to the clock pin on the PCI connector and that > will give you a PCI clock. > > The one thing that I do not know is how they get the clocks to the > other slots. I thought I saw some clock traces on the backplane board > so I do not think you will have any issues in meeting the clock skew. > > Good luck, > > ZiadArticle: 55488
rickman wrote: > <snip> > > > Price and Availability > > > The ispXPLD 5512MX in the 1.0mm ball pitch, 484 fpBGA package will sample later this quarter > > >with initial production scheduled for Q4. Pricing for the ispXPLD 5512MC in volumes of >1000 > > >pieces starts at $17.75. Additional members of the ispXPLD 5000MX family are expected to be > > >released over the coming year. > > > > -jg > > I remember looking at the XPLD parts and there is something about them > that does not fit the socket. I remember now. It was the price... <snip> > I wonder how nicely I would have to ask to get the price down from $83 to > $20??? :) I'd start by quoting their press release back to them, that states $17.75/1000 :) This was not a 'Price 2 years out in million pcs' as I have seen other do, but claims to be a 2002 price, 1000 pcs column. -jgArticle: 55489
Mike, Most lithium cells are rated at 15 years, abs min, with a suitable small load. Since the memory is < 100 nA, that is (probably) less than the leakage from the battery holder. http://www.sanyo.com/batteries/lithium_ind.cfm At .5% per year self-discharge rate, and 15 years, that is still way up there in capacity. At 850 mAHr capacity, 15 years at 100 nA is .013 aH, or 13 mAHr, so it looks a small coin cell works.... Austin Mike Treseler wrote: > > JP Nicholls wrote: > > We want to use the encrypted bitstream option of a Xilinx FPGA in order > > to protect IP. However we are having trouble sourcing a suitable battery. > > Our product needs to have a shelf life of 10 years plus. > > I don't think there is such a battery. > > You need to at least provide some way for the customer to > reload the keys after replacing the battery. > > Maybe stash the keys in flash and have the uP reload > stealthily on some date related command. > > You also have to consider whether this level of security > is worth the bother to your customers. > > Remember that bitstream encryption has zero value for them. > > -- Mike TreselerArticle: 55490
Wolfgang, are you aware of the fact that antifuse FPGAs inherently can only be programmed once. "OTP" means one-time-programmable. In my experience, this is not meaningful in a school environment where students want to learn by doing. I do not want to badmouth antifuse FPGAs, they have some merits. But they do not belong in a student/teaching environment. This is friendly advice, not anti-antifuse propaganda. :-) Peter Alfke, Xilinx Applications ============================ Wolfgang Schmiesing wrote: > > I am planning to write a tutorial on FPGA-programming for students. > As an excercise I would like the students to "program" a very simple > logic function using an interactive representation of an FPGA. Due to > limitited display size the graphical representation of the FPGA has to > be very simple. > > Now I'm searching for detailed information about the interconnect > structure of > FPGAs using antifuses. How are the in-/output pins connected to the > relating CLBs? I haven't found anything yet. Can anyone help me?Article: 55491
I am more positive. Since the current drawn from the battery is essentially zero, you are only limited by its shelf life, and Lithium batteries are very good in that regard. Just make sure that your pc-board is clean and has no acidity left on the surface, causing leakage current. Also remember that you can exchange the battery ( but only while the device is powered up ) as often as you want. While Vcc is active, Vcc supports the key information, the battery does nothing. Peter Alfke, Xilinx Applications ================= Mike Treseler wrote: > > JP Nicholls wrote: > > We want to use the encrypted bitstream option of a Xilinx FPGA in order > > to protect IP. However we are having trouble sourcing a suitable battery. > > Our product needs to have a shelf life of 10 years plus. > > I don't think there is such a battery. > > You need to at least provide some way for the customer to > reload the keys after replacing the battery. > > Maybe stash the keys in flash and have the uP reload > stealthily on some date related command. > > You also have to consider whether this level of security > is worth the bother to your customers. > > Remember that bitstream encryption has zero value for them. > > -- Mike TreselerArticle: 55492
Why not put two batteries on it. Then you can swap one out while the other is still working. Steve "Peter Alfke" <peter@xilinx.com> wrote in message news:3EBC2559.6BED3FBE@xilinx.com... > I am more positive. > Since the current drawn from the battery is essentially zero, you are > only limited by its shelf life, and Lithium batteries are very good in > that regard. Just make sure that your pc-board is clean and has no > acidity left on the surface, causing leakage current. > > Also remember that you can exchange the battery ( but only while the > device is powered up ) as often as you want. > While Vcc is active, Vcc supports the key information, the battery does nothing. > > Peter Alfke, Xilinx Applications > ================= > Mike Treseler wrote: > > > > JP Nicholls wrote: > > > We want to use the encrypted bitstream option of a Xilinx FPGA in order > > > to protect IP. However we are having trouble sourcing a suitable battery. > > > Our product needs to have a shelf life of 10 years plus. > > > > I don't think there is such a battery. > > > > You need to at least provide some way for the customer to > > reload the keys after replacing the battery. > > > > Maybe stash the keys in flash and have the uP reload > > stealthily on some date related command. > > > > You also have to consider whether this level of security > > is worth the bother to your customers. > > > > Remember that bitstream encryption has zero value for them. > > > > -- Mike TreselerArticle: 55493
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=2528452066&category=466 3&rd=1Article: 55494
Does anyone know prices for a "loaded" MJL Stratix board (32 MB SDRAM+16 MB FLASH) and is it shipping now? I have emailed the MJL sales guys but no one responded. Thanks. Atif Zafar. Indiana University jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0305060839.35dcccad@posting.google.com>... > Unfortunately it only has a 10 Mbps Ethernet connection instead of a > 10/100. Bummer if you need to transfer a lot of data. > > If it had a 10/100 connection, I would have purchased it over the > Altera NIOS Stratix 1S10 Development Board. > > Jim > > > azafar@iupui.edu (Atif Zafar) wrote in message news:<6ed146ef.0305051755.50e81dec@posting.google.com>... > > Ziad: > > > > Check out http://www.mjl.com/product/mjlstratix.asp > > I like this board because it is inexpensive ($795) and has an EP1s25 > > device. It also has integrated VGA output. I anticipate a graphics > > project using FPGA's. > > > > Atif. > > > > zabulebdeh@yahoo.com (Ziad Abu-Lebdeh) wrote in message news:<f784b02b.0305030542.5976b082@posting.google.com>... > > > Hi Atif, > > > > > > I am not familiar with the MJL kit you are talking about, but Altera > > > does have a 1S80 Kit for DSP. Check it out here: > > > http://www.altera.com/products/devkits/altera/kit-dsp_stratix_pro.html > > > > > > Ziad Abu-Lebdeh > > > > > > azafar@iupui.edu (Atif Zafar) wrote in message news:<6ed146ef.0305010820.682b01be@posting.google.com>... > > > > Does anyone have experience with the MJL Stratix dev kit. It is the > > > > lowest cost Stratix EP1s25 kit I could find. Anyone know whether it > > > > can handle devices denser than the 1s25 (i.e. 1s40 or 1s80?). I have > > > > an imaging and 3d graphics pipeline project. Does anyone know whether > > > > the Virtex II are a better choice or the Stratix? Thanks. > > > > > > > > Atif Zafar > > > > Indiana UniversityArticle: 55495
Hello eveyone,
I would like to know is it possible to drive the input of DLL from the internal
logic for Vertex-E or spartan II E device by any means (i.e through global buffer, etc..) ?
Article: 55496"Wolfgang Schmiesing" <wolfgang@byke.com> wrote in message news:eb5a527f.0305090707.520af32@posting.google.com... > I am planning to write a tutorial on FPGA-programming for students. > As an excercise I would like the students to "program" a very simple > logic function using an interactive representation of an FPGA. Due to > limitited display size the graphical representation of the FPGA has to > be very simple. > > Now I'm searching for detailed information about the interconnect > structure of > FPGAs using antifuses. How are the in-/output pins connected to the > relating CLBs? I haven't found anything yet. Can anyone help me? have you looked at the info and links on the xilinx xup(xilinx university program) site ? http://xup.msu.edu/ http://xup.msu.edu/students/tutorials.htm http://xup.msu.edu/students/examples.htm http://www.xilinx.com/univ/index.htmArticle: 55497
There are of course secure micros, Dallas/Maxium make them, battery backed and the entire code is stored in ram, and encrypted differently each time you program it. The also do the one touch thing, with encrypted memory to boot Simon "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:b9ip81$jof1e$1@ID-84877.news.dfncis.de... > "Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag > news:3EBC16D2.953822CF@xilinx.com... > > > Most lithium cells are rated at 15 years, abs min, with a suitable small > > load. Since the memory is < 100 nA, that is (probably) less than the > > leakage from the battery holder. > > How about a big (gold)cap + a recharge diode + photo cell (if there is any > chanche that light fall onto the PCB) ?? > I guess a thermonuklear battery for satallite apps is just a little overkill > ;-)) > > > > Maybe stash the keys in flash and have the uP reload > > > stealthily on some date related command. > > This sounds NOT like a good idea. AFAIK the trick is to hold the keys inside > the FPGA in SRAM cells, so a hacking attack is EXTREMLY difficult to > impossible. An external uC can easyly be cracked. > > -- > MfG > Falk > > > >Article: 55498
Jim Granville wrote: > > rickman wrote: > > > <snip> > > > > Price and Availability > > > > The ispXPLD 5512MX in the 1.0mm ball pitch, 484 fpBGA package will sample later this quarter > > > >with initial production scheduled for Q4. Pricing for the ispXPLD 5512MC in volumes of >1000 > > > >pieces starts at $17.75. Additional members of the ispXPLD 5000MX family are expected to be > > > >released over the coming year. > > > > > > -jg > > > > I remember looking at the XPLD parts and there is something about them > > that does not fit the socket. I remember now. It was the price... > > <snip> > > I wonder how nicely I would have to ask to get the price down from $83 to > > $20??? :) > > I'd start by quoting their press release back to them, that states > $17.75/1000 :) > > This was not a 'Price 2 years out in million pcs' as I have seen other > do, > but claims to be a 2002 price, 1000 pcs column. Thanks, that's a good idea. Not only did I find the press release you describe, but there is also one on the 4000V family which has a $15 price on the 512 part. I am only asking them to meet a $20 price point. I have printed both pages to PDF and will forward them on to the sales rep. He had already sent me an email indicating an interest in discussing the price disparity after I told him what I had posted here. This will give me a bit more ammunition for him to work with. Of course I am asking for pricing on qty 100 rather than 1000, but I would hope there would not be a 2x difference in price. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55499
Hello Karthik, The DLL input can be one of the following three: 1. BUFG - Internal global clock buffer 2. IBUFG - Global clock input buffer on the same edge of the device (top or bottom) 3 - IO_LVDS_DLL - the pin adjacent to a global clock pin. What you need to do is insert you signal from the internal logic to a global clock buffer, and from there to the DLL CLKIN input. Gilad.
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