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Hello! I'm working on a project right now that's centered around
Spartan-IIEs, but the capabilities of the new IIIs seem really
exciting, especially since some of our applications focus on DSP. Does
anyone know what availability is like on these? Anyone actually talked
to xilinx? Costs? Our app needs BRAMs, so we'd have to switch from a
XC2S50E to a XC3S200, which might be cost-ineffective...
...Eric
Article: 54826Hi, Has anyone had any success with Webpack 5.2 installation on Windows 98? I get to the point where it asks me to check off on approval of their (we own yours ass!) license, but the check box is greyed out. So I can't proceed any further. Help? Anyone? Thanks LTArticle: 54827
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > Christopher Fairbairn <ckf13@student.canterbury.ac.nz> wrote: > : Hi, > > : Uwe Bonnes wrote: > :> A recent well configured wine with the prerequisited for Installshield 6 > :> installers ( native stdole*.tbl) in the <wine>/windows directory should > :> do the job. Installation will take some time ( wine directory handling in <snip> > Now cd to the webpack base directory and run "wine bin/nt/ise.exe". It > should work. Set the wine version to a windows version required by > webpack. Running with native msvcrt is needed at least for the CPLD verilog > flow. I'm in the process of attempting an install, and have it at least installed. I'm now trying to find out which DLLs it needs, and what versions. (I do not have an install of windows on any of my machines). Can you program CPLDs under wine? -- http://inquisitor.i.am/ | mailto:inquisitor@i.am | Ian Stirling. ---------------------------+-------------------------+-------------------------- "Looks like his brainwaves crash a little short of the beach..." - Duckman.Article: 54828
"Loi Tran" <leotran@att.net> wrote in message news:Rehoa.35691$cO3.2680296@bgtnsc04-news.ops.worldnet.att.net... > Hi, > > Has anyone had any success with Webpack 5.2 installation on Windows 98? I > get to the point where it asks me to check off on approval of their (we own > yours ass!) license, but the check box is greyed out. So I can't proceed any > further. > > Help? Anyone? > As far as I can see on the Xilinx site, the 5.2 version only supports Win2k and WinXP :-( Cheers KlausArticle: 54829
> for exhaustive testing of FPGA'S v make use of LFSR's. and to >generate the maximun number of output states v have to feedback the >xnor output of the cetain flipflop outputs to the input of the first >flipflop. and it is associated with the maximum polynomial. Could you say more about how you are going to test things? How big a polynomial do you need and/or how long is it going to take to run? > i would like to know how to find out the maximum polynomial. Ask mathematicians. They have big lists of them. Computer or communications people often use them for error detecting codes. The Xilinx app note lists lots of useful ones. Why do you need any more? >i have gone through the xilinx date sheets and they gave just the >number of the flip flops whose ouput should b given to the xnor gate >input. The inputs to the XOR correspond to 1s in the polynomial. I think you have to add a high-order 1. Thus if you use taps 3 and 4 on a 4 bit LFSR, the polynomial is 10011. (I could easily have right/left reversed here. I think the bit reversed version of a maximal polynomial is also maximal.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 54830
"Hal Murray" <hmurray@suespammers.org> wrote in message news:va3au11vjqej25@corp.supernews.com... > > for exhaustive testing of FPGA'S v make use of LFSR's. and to > >generate the maximun number of output states v have to feedback the > >xnor output of the cetain flipflop outputs to the input of the first > >flipflop. and it is associated with the maximum polynomial. > > Could you say more about how you are going to test things? > How big a polynomial do you need and/or how long is it going > to take to run? > > > > i would like to know how to find out the maximum polynomial. > > Ask mathematicians. They have big lists of them. Computer > or communications people often use them for error detecting > codes. I don't know the theory so well, but I believe it is significantly harder to find good ones as the get larger. Still, people have found some big ones. > The Xilinx app note lists lots of useful ones. Why do you need > any more? Numerical Recipes has a table, and some description of the theory. > >i have gone through the xilinx date sheets and they gave just the > >number of the flip flops whose ouput should b given to the xnor gate > >input. > > The inputs to the XOR correspond to 1s in the polynomial. I think > you have to add a high-order 1. Thus if you use taps 3 and 4 on > a 4 bit LFSR, the polynomial is 10011. (I could easily have > right/left reversed here. I think the bit reversed version of > a maximal polynomial is also maximal.) Most likely that is true. If not, you can reverse both the polynomial and the data, and get a similar result. There is an ambiguity which comes from converting a byte string to a bit string, which works out to asking which bit is sent first. Ethernet sends LSB first, so this is the most common form for the CRC32 polynomial. Ethernet initializes to all '1' bits, and complements at the end. -- glenArticle: 54831
eric - Mtl wrote: > > Bill Hanna wrote: > > I have been designing a Digital Signal Processor using the XC2V4000 > > chip. > > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in > > developing the design: > > > > Software bugs in SystemAce causes erase problems in the MPM. > > Deleting signal wires in ECS causes Fatal errors that crash the > > system. > > A large design exceeds the 2GB memory limit and generates a fatal > > memory error. > > > > I have designed Altera chips for over 6 years and never had a > > problem. > > > > All digital designers should stop designing new projects with > > Xilinx ICs until Xilinx corrects all software problems with ISE. > > > > Bill Hanna > > Hi, > > I'm not going to boycott Xilinx, since the good with them > really outweighs the bad, but as an ECS (Schematic capture) > user, I must admit that this tool often drives me crazy ... > > Xilinx's great silicon chips really deserve better tools ! > > I know the usual debate about schematic vs HDL, but if I'm to > ever switch to HDL I'd like it to be for what they have to > offer, not because the Schematic capture software is so badly > designed and buggy that I can't take it anymore. > > Even when using HDL for blocks, I really think that schematic > diagram is great for the top level of a design, because of it's > inherently parallel representation, opposed to the visually > sequential nature of text based HDL representations, but that's > not the point here ... I was a die hard schematic user too. I felt that I had better control over my design with schematic. But then I worked with VHDL for awhile and I realized the power. It can be a bit of a PITA to really optimize the hardware, but using schematic does not really assure you of getting what you put on the page. The tools optimize things sometimes since they know more than you do :) But the transition was really confirmed for me when I started writing test benches to verify my design. I can generate a model of a bus or an ADC or any other logic external to my design that I need to test it. With the waveform editor I had to *plan* my simulation very laboriously. If anything changed, I would often have to redo large parts. With an HDL test bench the test bench interacts with your design the same way the real board does. > If I had to rank quality and code stability for ECS, it would > be very close to the bottom. ...snip... > I don't know how many Xilinx users actually use ECS and if peoples from > the ECS development team ever read those NG posts, but I'm pretty sure > other users too experience these inconveniences on a daily basis and would > appreciate to see them addressed as much as I do. I am sure your many bug reports are valid and hopefully someone will address them. I did not read the details. Did you report many of these? If they are not reported, they can't be fixed. I know this takes time, but at this point if you are vested in the tool, it will be up to you to report the bugs. I don't know how many ECS users there still are, but I can tell they must be real die hards. I realized that HDL was the way to go when Ray Andraka switched. He designs hierarchical, blocked out, highly floorplanned designs. In the past he had built up a large library of schematic elements that allowed him to build large DSP designs very quickly complete with schematic specified floorplanning. I know from experience that this took a lot of effort to implement. But once he was forced by a contract to work with an HDL, he realized the labor savings from working with code and once he started converting his symbol library to a code library, I don't think he ever looked back. Perhaps I should not put words in his mouth, but this is what I have gotten from reading his posts. > Also, since most new users start with schematics, pissing them off from > day one with such a buggy software is probably not a wise thing to do. That may have been true in times past, but I think newbies now start with an HDL. When I went to school, Fortran was still the only required language in EE. Now I don't think you can earn a BSEE without knowing some HDL. I have met HDL designers who work in HDL without even drawing a block diagram of what they want. This is very alien to me but it seems to be the norm now. I think the time of schematic has passed. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54832
I'm having a problem trying to get a file to synthesized when calling a library. library hdlc; use hdlc.hdlc_components_pkg.all; this is the error I get ERROR:HDLParsers:3317 - C:/webpack/bin/hdlc/./RX/CORE/RxChannel.vhd Line 54. Library hdlc cannot be found. ERROR:HDLParsers:3013 - C:/webpack/bin/hdlc/./RX/CORE/RxChannel.vhd Line 55. Library hdlc is not declared. I did add the library to the project. So what am I doing incorrectly. Thanks, LTArticle: 54833
Eric wrote: > > Hello! I'm working on a project right now that's centered around > Spartan-IIEs, but the capabilities of the new IIIs seem really > exciting, especially since some of our applications focus on DSP. Does > anyone know what availability is like on these? Anyone actually talked > to xilinx? Costs? Our app needs BRAMs, so we'd have to switch from a > XC2S50E to a XC3S200, which might be cost-ineffective... I have been told 1Q04 for production. No one is talking about samples except to the *big* customers. But I have been told that the 3S50 and 3S1000 are sampling engineering samples now. I am not trying to rag on Xilinx about any past releases, since everyone can have a few delays from time to time. But I would not count on the XC3S parts yet, even if you don't need production until next year. There's many a slip twixt the cup and the lip! Again, I don't want to knock Xilinx (I like 'em... I like 'em a lot!), but the Altera Cyclone is looking pretty good and priced right. The Cyclone parts have as much or more RAM bits than the XC2S parts. Compared to the XC3S they are in smaller blocks. If you don't need a full 18kbits in each block, the Cyclone may be just what you need with 4kbit blocks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54834
Loi Tran wrote: > > Hi, > > Has anyone had any success with Webpack 5.2 installation on Windows 98? I > get to the point where it asks me to check off on approval of their (we own > yours ass!) license, but the check box is greyed out. So I can't proceed any > further. > > Help? Anyone? I have not installed this version yet, but normally when you see this it means that they want you to actually *read* the license. Just click in the scroll window or you may even have to scroll to the bottom. Then the check box should be clickable. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54835
In article <b7ssbr$5jk$2@hercules.btinternet.com>, "Leon Heller" <leon_heller@hotmail.com> wrote: > >"Loi Tran" <leotran@att.net> wrote in message >news:Rehoa.35691$cO3.2680296@bgtnsc04-news.ops.worldnet.att.net... >> Hi, >> >> Has anyone had any success with Webpack 5.2 installation on Windows 98? I >> get to the point where it asks me to check off on approval of their (we >own >> yours ass!) license, but the check box is greyed out. So I can't proceed >any >> further. >> > >5.2 only works with Win2000 or XP. > >Leon Thanks to everyone who replied. Crap! If I'd known this I wouldn't have paid for the CD to be shipped to me from Xilinx in the first place. LTArticle: 54836
hi murray,
actually i started thesis work on diagnosia and fault tolerence
on FPGA'S. i was wondering if i know to generate my set of output
states of LFSR'S i can reduce the number of testing inputs set
depending upon the application.
naveen
"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:<UCjoa.530602$3D1.293299@sccrnsc01>...
> "Hal Murray" <hmurray@suespammers.org> wrote in message
> news:va3au11vjqej25@corp.supernews.com...
> > > for exhaustive testing of FPGA'S v make use of LFSR's. and to
> > >generate the maximun number of output states v have to feedback the
> > >xnor output of the cetain flipflop outputs to the input of the first
> > >flipflop. and it is associated with the maximum polynomial.
> >
> > Could you say more about how you are going to test things?
> > How big a polynomial do you need and/or how long is it going
> > to take to run?
> >
> >
> > > i would like to know how to find out the maximum polynomial.
> >
> > Ask mathematicians. They have big lists of them. Computer
> > or communications people often use them for error detecting
> > codes.
>
> I don't know the theory so well, but I believe it is significantly harder to
> find good ones as the get larger. Still, people have found some big ones.
>
> > The Xilinx app note lists lots of useful ones. Why do you need
> > any more?
>
> Numerical Recipes has a table, and some description of the theory.
>
> > >i have gone through the xilinx date sheets and they gave just the
> > >number of the flip flops whose ouput should b given to the xnor gate
> > >input.
> >
> > The inputs to the XOR correspond to 1s in the polynomial. I think
> > you have to add a high-order 1. Thus if you use taps 3 and 4 on
> > a 4 bit LFSR, the polynomial is 10011. (I could easily have
> > right/left reversed here. I think the bit reversed version of
> > a maximal polynomial is also maximal.)
>
> Most likely that is true. If not, you can reverse both the polynomial and
> the data, and get a similar result. There is an ambiguity which comes from
> converting a byte string to a bit string, which works out to asking which
> bit is sent first. Ethernet sends LSB first, so this is the most common
> form for the CRC32 polynomial. Ethernet initializes to all '1' bits, and
> complements at the end.
>
> -- glen
Article: 54837Using the FPGA to generate multiple clocks is almost certainly the way to go. However, since you are using Virtex-II devices, you don't need to generate a 2x clock under normal circumstances; you can use the VII DDR IOB flops to generate external copies of the clock for you. If you have your 120MHz clock on a global clock buffer (call this clk120ext), then instantiate two FDDRRSE elements FDDRRSE flop0 ( .C0(clk120ext), .C1(!clk120ext), // the FDDEESE has the ability to use the inverted clock .CE(1'b1), .D0(1'b1), .D1(1'b0) // Connect R and S as you see fit ); Do the same for flop1 (you may need to fight with your synthesis tool to prevent optimization from merging the two flops into one - set_dont_touch in synopsys or syn_preserve in synplicity). Tie the Q outputs to the I of OBUFs of the appropriate type, and lock them to two nearby IOBs, and you have created two very low skew clock outputs. Furthermore, you can use the same clock to generate the control signals going to the RAMs - if the load on the clock and the control lines is identical, the arrival time of the control signals at the RAMs will be nearly identical to the arrival of the clock (you can invert the clock in the FDDRSE by flipping the values of D0 and D1 in the instantiations if you want the control changes to take place around the falling edge of the clock). The duty cycle of the outgoing clock will be similar to clk120ext - if clk120ext is generated by a DCM, then the duty cycle will be pretty close to 50/50. If you want the external clock to be the same as the internal clock, then you may need to do some additional things. Starting with the board clock (clk120), connect that through an IBUFG (call this CLK120in) and connect it to the CLKIN of a DCM. Then connect CLK0 of the DCM to a BUFG. The output of this BUFG is clk120ext, which is used to drive the DDR flops described above. Instead of just instantiating two FDDRRSE and OBUFs, instantiate three. Connect the output of the third OBUF to another IBUFG pin (on the board), and from there to the CLKFB of the DCM. Match the three PCB trace lengths. This ensures that the clocks at the SRAMs are in phase with clk120 (the clock coming into the FPGA). You can then use a second DCM to generate another clock domain - connect clk120in to the CLKIN of the DCM, connect CLK0 to a second BUFG, and connect the output of the BUFG (called clk120int) to the CLKFB of the DCM. This will generate an internal clock (clk120int) which is ALSO in phase with CLK120, which can be used to clock flip-flops inside the device. The design of high speed RAM interfaces can be tricky, but the Virtex-II architecture provides you with a lot of tools to design them well - particularly the DDR flops, and the DCMs (including the fine phase shift of the DCM). You don't mention what kind of RAM you are using; Xilinx has several appnotes about using Virtex-II devices with different types of synchronous memories. Avrum "Hal Murray" <hmurray@suespammers.org> wrote in message news:v9uikqh1ec8f6@corp.supernews.com... > One approach to consider. The idea is to avoid the external > clock buffer by generating several copies of the clock in > the Xilinx. > > Make a 240 MHz clock. Use that to make a 120 MHz sq wave, and > feed that to several nearby IOBs. Nearby is to reduce skew, > so you want them all on the same clock line. I think that > constrains you to left or right side rather than top or bottom. > You would need to check the final routing carefully. > > You might be able to do something similar by connecting several > OBUFs (rather than one) to the output of the DCM. You just need > a way to make sure the skew between them is low. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 54838
Does any manufacturer make a very small programmable logic device (with FLASH storage) is say a SOIC-8 or similar. It's for a small home project that only has one output and only one input (plus CLK) Thanks in advance. IanArticle: 54839
"Ian Hickey" <ihickey@ieee.org> schrieb im Newsbeitrag news:3ea276da$1@clear.net.nz... > Does any manufacturer make a very small programmable logic device (with > FLASH storage) is say a SOIC-8 or similar. > > It's for a small home project that only has one output and only one input > (plus CLK) AFAIK no. The smallest pincount for CPLDs/FPGAs is somewhere at 44 pins. If you need such a small logic device, and the speed requirements are not too high, you may use a microcontroller. They are available in such small packages, e.g. ATMEL offers them (AVR devices) -- MfG FalkArticle: 54840
Hi, Uwe Bonnes wrote: > :> A recent well configured wine with the prerequisited for Installshield > :> 6 > :> installers ( native stdole*.tbl) in the <wine>/windows directory > :> should do the job. Installation will take some time ( wine directory > :> handling in help/usenglish/newroot with it's 5499 files is not optimal) > :> , show some errors and message box stacking may be wrong so that na > :> "OK" buttom is hidden, but the installation should be useable. Finally got some time to look at this again and it's working like a charm! Thank for all the great advice. For others (a couple have emailed me) here's what I finally did and what I found out along the way... 1) I had no luck with the version of wine that I was using (sorry can't remember what it was now) so I upgraded to Wine 20030408 and things immediatly started to look better. I've configured WINE as a "fake windows" rather than telling it where my real windows installation is. 2) I changed my copy of ~/.wine/config to set the windows version to nt40. 2) You should be able to start the installation of webpack via a command such as "wine WebPACK_52_fcfull_i.exe". On my setup at least (I'm not sure if by design, as I've only run the installer under WINE) the wizard skipped right past the page which allowed you to select which modules you wanted to install. It is important to go to this page and explictly deselect the programming device driver options as attempting to install these will fail. You can explictly select which page of the wizard you want by clicking on it's title on the left hand side of the screen. The installation should then go smoothly up the stage where it attempts to run the SUN Java Runtime Envirionment installation. At this stage it will quickly dump into winedbg. Exiting winedbg (type quit) will cause the installation to continue (it might appear to not be doing anything at all for a little while). 4) set the XILINX environment variable to the installation directory for Webpack (in my case C:\xilinx). This should allow you to execute most of the executables, all located in $XILINX\bin\nt\. For example "wine C:\xilinx\bin\nt\par.exe", or ise.exe. However you will most likly get errors with respect to msvcirt.dll. 5) I copied msvcirt.dll over from my Win2k machine and placed it in ~/c/windows/system32 Following these steps allows me to use the command line utilties and the ISE GUI (ise.exe) and with my limited testing so far I haven't seen any major problems. As for board programming support I don't know what the options are there, as I have a board specific application to do this in my case. Hope it helps, Christopher FairbairnArticle: 54841
Greger G. wrote:
>
> Ello,
> I have this 8-bit paralell binary signal I need to read with a LED display,
> speed is not essential as the ouput is on for as long as I give it the strobe signal.
> One idea would be to use a Xilinx 9536/9572 (the only two I'm capable of programming)
> and feeding it to an ICM7212 LED driver. However this is beyond my current skills and I'm
> wondering if someone has perhaps already done something like this or has a few pointers.
> The signal in contains the values 256bits and today I use led's for 1-2-4-8-16 etc, so a
> 3 segment led display would be a great improvement :)
> I'm only familiar with the schematics design of the xilinx software and know nothing
> of vhdl programming itself
> Thanks,
>
> //Greg
Can you explain why 256bits and are you using leds arranged in 1 , 2
,4,8 ,16 digit pattern?
eg.
*
* *
* *
*********
*
*
*
* represent LED
Thanks
Article: 54842Hello! Can I use bidirectional mode with differential LVDS? Target device will be Altera Cyclone. I know there are two kinds of resistor connection for transmiter and receiver (Altera application note 254, figure 3 on page 5 http://www.altera.com/literature/an/an254.pdf ). But I need a transreceiver. Should I use same connection as with transmitter or something else? Or is only way to have transmitter and receiver pins & resistors and then connect them to together? Thank you for your help! - JRArticle: 54843
Hello EveryOne, In our shop we have very limited experience with the older MMI/AMD series of PALs mostly in maintaining legacy products. Recently, we have an application or two that could benefit from the use of programmable logic and would like to take advantage of some of the newer products availible. One product under consideration is Altera's ATF750 series. Can anyone point towards resources that would let someone with limited experience with Programmable logic get up to speed quickly with this product ? Specificly, we are after tutorials simulation software, or development boards that would let us determine if this is a viable way to go. We did download WinCUpl from the Altera site, but at first glance the documentation seems sparse or the learning curve is steep. Any thoughts or contributions are welcome. Thanks, WallyArticle: 54844
On Sun, 20 Apr 2003 22:30:57 +1200, "Ian Hickey" <ihickey@ieee.org> wrote: >Does any manufacturer make a very small programmable logic device (with >FLASH storage) is say a SOIC-8 or similar. > >It's for a small home project that only has one output and only one input >(plus CLK) A PIC microprocessor may do what you want (small package and reprogrammable) assuming you don't need to do things extremely quickly. Try news:sci.electronics.design or perhaps news:comp.arch.embedded for more details Regards, Allan.Article: 54845
paraag wrote: > Hi > Im tring to layout a mac fir filter in ISE 5.1 generated from core > generator. Im having problems in synthezing the Xilincorelib library > as it has textio and records in the vhdl files--- itried in Leonardo > and also ISE 5.1. Any source file using textio is intended for simulation, not synthesis. Vendors provide no synthesizable HDL source for cores, because then you could target other devices. The choice is synthesis *or* vendor core generation. > anyone tell me exactly how to go about the process of core generation > and laying it out. To use the vendor cores, you have to follow the vendors script and work partly in the dark. To get into a standard design flow, consider writing your own code. -- Mike TreselerArticle: 54846
Hello,
Is there any information about Xilinx bitstream file format?
I would like to download bitstream using my own program, but I have no
idea how the bitstream download to Xilinx chip.
Is it read 8-bit per clock to the download cable or ..?
thanks.
Fan.
Article: 54847"Yang-Tzu" <d8728141@knight.fcu.edu.tw> wrote in message news:85c3c777.0304201025.73ad6bf9@posting.google.com... > Hello, > Is there any information about Xilinx bitstream file format? > I would like to download bitstream using my own program, but I have no > idea how the bitstream download to Xilinx chip. > Is it read 8-bit per clock to the download cable or ..? > thanks. > > Fan. See Xilinx application notes on their website, e.g. XAPP138 : Virtex Configuration and Readback, and also the data sheet of your device. Download can be serial or parallel. MarcArticle: 54848
Hi Joona, > Can I use bidirectional mode with differential LVDS? Target device > will be Altera Cyclone. > I know there are two kinds of resistor connection for transmiter and > receiver (Altera application note 254, figure 3 on page 5 > http://www.altera.com/literature/an/an254.pdf ). > But I need a transreceiver. Should I use same connection as with > transmitter or something else? Or is only way to have transmitter and > receiver pins & resistors and then connect them to together? I ran into this a few weeks back. Quartus will refuse a bidir with LVDS as its I/O standard, so it'll be either LVDS out or LVDS in. However, SSTL-2 standard uses the same signalling levels as LVDS, although it has less drive current. So, if you only have a point-to-point bidirectional channel over a fairly short distance this should do the trick. If the Cyclone has to drive a lot of inputs you might run out of steam because SSTL-2 might not have enough drive to attain the proper slew rate. Hope this helps, BenArticle: 54849
Hi Wally, The ATF750 is made by Atmel, not Altera. Kind of important. It's an interesting part (The AFT750), but sole-sourced, and has poor software support. Last time I checked, it was expensive too. Get yourself a copy of Warp. A decent introduction to HDL design, and it has the synthesizer and simulator for standard PAL parts. Start with the 16V8 / 22V10 and work your way up. Altera's part is the MAX7000. Xilinx make the 95xx and Cool-Runner. Software from both is free from their web sites. $.02, SH On Sun, 20 Apr 2003 15:05:05 GMT, Wally Daniels <wdaniels@glinx.com> wrote: > >Hello EveryOne, > > In our shop we have very limited experience with the older >MMI/AMD series of PALs mostly in maintaining legacy products. > > Recently, we have an application or two that could benefit >from the use of programmable logic and would like to take advantage >of some of the newer products availible. > > One product under consideration is Altera's ATF750 series. > > Can anyone point towards resources that would let someone with >limited experience with Programmable logic get up to speed quickly >with this product ? > > Specificly, we are after tutorials simulation software, or >development boards that would let us determine if this is a viable >way to go. We did download WinCUpl from the Altera site, but >at first glance the documentation seems sparse or the learning >curve is steep. > > Any thoughts or contributions are welcome. > >Thanks, Wally
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