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Tja! While working on our masters thesis project, we just realised that we need a techdef file for the Xilinx 4013 chip in order to generate RTL-VHDL for Synopsys FPGA Compiler with Alta Group's Visual Architect tool. If anybody has hacked or know about where we could get hold of such a file, we would greatly appreciate it. Very Truely Yours Joachim Strömbergson Peter WikmanArticle: 7151
A William Sloman <sloman@sci.kun.nl> wrote:
>Richard B. Katz wrote:
>>
>> hi,
>>
>> as part of a space flight instrument, a high speed digitizer is required.
>> here's a brief specification.
>>
>> 1. sample rate >= 1 gigasample/second, 8-bit resolution; > 1.6
>> Gigasample/second desired.
>> 2. input bandwith >= 250 MHz
>> 3. memory depth >= 32,000 samples; > 64,000 samples desired.
>> 4. 100 MHz clock input, PLL to increase speed as needed
>> 5. 80 Hz rate.
>> 6. power <= 25 watts.
>> 7. prefer mcm packaging
>> 8. design life >= 8 years, 5 years on-orbit.
>>
<snip>
>
>Actel's ACT3220DX-1 offers 5nsec SRAM in a fast, one-time programmable
>FPGA, which is probably the way to go if you can afford the price - $250
>per FPGA, and $2,500 for the programming software. The prices were
>quoted by the Dutch agents, so you might well get the stuff cheaper.
>
I guess Bill means the A32200DX-1, there is no 3220.
Depending on your design lead time you could consider the A32100. It
has half the logic capacity of the 32200 (10000 vs 20000 gates) but
has almost as much RAM (2048 vs 2560 bits). This should make it quite
a bit cheaper but almost as good for your SRAM application. Trouble
is, it's not yet available. :-(
If your design were high volume you could probably get the pursuade
your local Actel distributor to give you the design tools but as a
space flight application I doubt that's gonna apply.
<snip>
Good Luck
Julian
--
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk error: smartass.sig not found
Hardware development eng. August Systems Ltd
---------------------------------------------------------------------
Article: 7152Examples? >I'm totally blown away by the price of serial eeproms. >It seems I can buy a micro, parallel eprom, and a pal >cheaper than a serial part. Am I missing something? >(I hope). > >Bruce Nepple >remove .nospam to email Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 7153
Dave, Whether it is on the same machine (tightly coupled multiprocessing) or over multiple machines (loosely coupled multiprocessing) shouldn't matter....at least with a good OS... I personally use a dual PPro machine with NT 4.0 WS. I find that I can do my simulations, routing, schematics, e-mail, news, etc. simultaneously with little or no degradation! It works excellently. Note, the current tools are not made to support multiprocessing intentionally, but what happens is the route seems to go to one CPU, and the simulation goes to the other... and the other stuff fits around it...(schematics are not very CPU intensive...). I thing going to NT by it self will help most of your current problems. AustinArticle: 7154
David Decker <mushh@jps.net> wrote in article <33e9575f.787240@news.jps.net>... > > Thanks for your comments, Austin, but I'm not asking about > multiprocessors, I'm asking about multiple PCs where I could do > simulation on one machine, Place and rout on another and schematic > capture on another. > > I know you can do all this on one machine, but Win95 has a way of > killing the job one way or another. Sometimes I do get away with > doing more than one thing at a time, but it's dangerous. I think your problem is that Win95 is kind of a toy OS compared to some of the others. I use both Unix and Windows NT. If your software is more Windows based, then I think NT would be a better choice than Win95. I can run synthesis, place and route, and many other stuff simultaniously. NT has a great feature to be able to assign priorities to tasks so when I'm running place and route for example, I set it at low priority -- once you do this, you can't even tell its running because the machine is so responsive for everything else you do, yet it really doesn't slow the job down noticeably because every spare CPU cycle still goes to it so the CPU meter is always pegged. Very slick. -- Rich Iachetta IBM Corporation iachetta@us.ibm.comArticle: 7155
I haven't used any other ISP CPLD devices than the Xilinx XC9500. However, there are a number of application notes on using the JTAG port on the Xilinx web site including the following Adobe Acrobat files. See 'http://www.xilinx.com/apps/epld.htm' for more information. Using the XC9500 JTAG Boundary-Scan Interface: http://www.xilinx.com/xapp/xapp069.pdf Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools: http://www.xilinx.com/xapp/xapp067.pdf XC9500 In-System Programming Using an Embedded Microcontroller: http://www.xilinx.com/xapp/xapp058.pdf This one also includes link to associated files. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.comArticle: 7156
The online-help of XACTStep6000 (SunOS-Version) contains the following
information:
Notes on SDF Files
XACTstep 6000 allows the generation of Standard Delay Format, or SDF
files.
This annotates the known timing characteristics of a circuit with the
delays
incurred by routing.
Simulation tools such as Synopsys VSS can both read and write this SDF
data.
Simulation before placement and routing may test the static
functionality of a
circuit, but cannot test all the dynamic effects which may depend on
delays on
the nets between gates.
When I try to read the SDF-File generated by XACT6000 into VSS, I get
lots of errors like:
**Error: vhdlsim,260:
(SDF File: mini.sdf Line: 54) generic
/MINI/REG/THOLD_CLR_C_noedge_posedge
is not declared.
All the generics listed are not declared in the xc6000_VITAL.vhd file.
I set up my synopsys-environment according to the manuals in the
synopsys-directory (Synopsys_flow.pdf, synopsys_lib_doc.pdf, ...). We
use Synopsys DC 3.5a here at the moment.
Best regards
F. Gilbert
____________________________________________________________________
LOOK AT OUR WEB SERVER: http://xputers.informatik.uni-kl.de
Frank Gilbert | University of Kaiserslautern
mailto:gilbert@informatik.uni-kl.de | Dept. of Computer Science
fax: ++49/0 631 205 2640 | Germany
..._/ _/ _/_/_/ _/ _/ _/_/_/ _/_/_/ _/_/_/ _/_/ ....._/
..._/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ ......._/_/
..._/ _/_/_/ _/ _/ _/ _/_/_/ _/_/_/ _/_/ ._/_/_/_/_/
._/_/ _/ _/ _/ _/ _/ _/ _/ _/ ...._/_/
_/ _/ _/ _/_/ _/ _/_/_/ _/ _/ _/_/ ....._/
Article: 7157Julian Cox <CoxJA@augustsl.demon.co.uk> wrote in article <877cd$c1119.2bd@news.august-systems.co.uk>... > A William Sloman <sloman@sci.kun.nl> wrote: > > >> > <snip> > > > >Actel's ACT3220DX-1 offers 5nsec SRAM in a fast, one-time programmable > >FPGA, which is probably the way to go if you can afford the price - $250 > >per FPGA, and $2,500 for the programming software. The prices were > >quoted by the Dutch agents, so you might well get the stuff cheaper. > > > I guess Bill means the A32200DX-1, there is no 3220. > Depending on your design lead time you could consider the A32100. It > has half the logic capacity of the 32200 (10000 vs 20000 gates) but > has almost as much RAM (2048 vs 2560 bits). This should make it quite > a bit cheaper but almost as good for your SRAM application. Trouble > is, it's not yet available. :-( > > If your design were high volume you could probably get the pursuade > your local Actel distributor to give you the design tools but as a > space flight application I doubt that's gonna apply. > > <snip> > > Good Luck > > Julian hi, that's an interesting solution and one that was considered. however, 1. i'm not sure that the sram will work that fast via the external pins vs. internal timing and make guaranteed setup and hold times. 200 MHz is FAST. 2. for space flight use, the A32200DX devices latch up fairly easily with very large currents and would require that latchup detection circuits be present and interrupt the power. then one prays that the part did not get damaged and lose long term reliability. to date, immediate functional failure after latchup has not been observed. ironically, the a32200dx is designed w/ an epi layer similar to other actel commercial/military devices and i measure 8.5 and 9.0 um on two lots. ironically, it is the sram area itself that causes the latchup, as the sister part without sram, a32140dx, does not latch. 3. another possibility i've considered is the chip express cx2001 with its embedded sram modules. testing of that chip is planned to be performed shortly. rkArticle: 7158
Due to explosive growth in our FPGA product line, this Microelectronics group of a $23billion Communications company is seeking a very talented engineer for a MTS FPGA Field Applications Engineering position. Locations-San Diego,Ca. Santa Clara, Ca. and Boston, Ma. Applicants should have at least 3 years exp in the design and development of integrated circuits, either FPGA or ASIC. Expertise in VHDL or Verilog HDL is required. BSEE or MSEE required. We are looking for a seasoned digital circuit designer with the interpersonal skills to perform the presentation and customer relationship roles. Duties include: Working with engineers to implement/optimize designs Presentations to engineers and managers Working with engineers to teach them tool flows Educating customers on methods and techniques Converting existing designs from competitors products to there FPGAs Providing feedback for future products, features, and tools Evaluting and prioritizing opportunities Providing detailed technical info/assistance FAE will be set up in a virtual office or will be located in leased executive/shared office facilities. Salary--$60-$90K base + 12 to 15% annual bonus and Field Sales Incentive Plan(Normally a bonus of approximately 15 to 25/30% for design wins and car allowance and who knows what else. THIS IS A VERY LUCRATIVE COMPENSATION PACKAGE FOR A TALENTED DESIGNER WHO IS READY TO "COME OUT FROM BEHIND THE DESK". THESE POSITIONS WON'T LAST LONG!!! -- Eddie Amara- Executive Recruiter SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" Home Page-http://www.spencersearch.com Voice 972-378-0280 Fax 972-378-0279 Email amaraju@onramp.net =====================================================================Article: 7159
In older Xilinx designs ( XC3000 families ) the serial datastream rate is limited to 1 MHz, in the newer designs ( XC4000 and XC5200 families) it is selectable between 1 MHz and 8 MHz, and can be driven at up to 10 MHz. ( There are ways to go faster, but they are a bit complicated )The number of bits varies with device size: ~15,000 bits for the smallest XC3000 device ( XC3020) to 1,925,000 bits for the presently largest XC4000 device ( XC4085XL). ( That comes to 10 to 20 bits per gate. ) Configuration times are thus between 10 ms and 250 ms, if you use the faster clock rate for the bigger devices. Byte-parallel configuration modes are not any faster, since they operate bit-serial inside the chip. The exception is the XC5200 Express mode that accepts byte-wide date at 10 MHz, thus configuring the 15,000-gate XC5215 with ~238,000 bits in about 4 ms. Peter Alfke, Xilinx ApplicationsArticle: 7160
We require FPGA work done on our custom VME signal processing card immediately (Xilinx based). Work involves modifying the VME address decoding to work with new Motorola MVME2604 CPU. Work has been estimated at 2-3 days and additional 2-3 weeks testing. You can work onsite at our location and use our lab facilities! - ViewLogic and Xact toolset. Please contact: Mike Mansell DataVation Inc. North York, Ontario. 416-665-0767 x228Article: 7161
Thomas Berndt (berndt@eas.iis.fhg.de) wrote: : : Hi, : : does anybody knows how I can download designs which are compiled with MAXPLUS2 : over the LPT port? : : Thanks in forward. : : Thomas : ______________________________________________________________________________ : | | : | Dipl.-Ing. Thomas Berndt Tel: 0351 / 4640-731 | : | email: berndt@eas.iis.fhg.de | : | URL: http://www.eas.iis.fhg.de/sim/staff/berndt| : | FAX: 0351 / 4640-703 | : | | : | Fraunhofer-Institut fuer Integrierte Schaltungen (IIS) | : | EAS Dresden | : | Zeunerstr. 38 | : | 01069 Dresden | : |______________________________________________________________________________| : : I used to use the LPT1 to download the binary bit file into the FLEX10K device. First an ".rbf" file has to be generated from the MAXPLUS2 using the "Combine Programming" files. There is an application note at http://www.altera.com describing the format of the file. Note specially the bit order. In the hardware setting, the data0 of tbe printer port is connected to the DIN, and DATA1 is connected to CLK. SOftware will generate all the clocks necessary to latch the programming data, which is in data0, into the FPGA. Note FPGA should be in PS mode. Hope this helps. --FengArticle: 7162
An example Altera'a new EPF6016 is $22, decreasing to $12 (budgetary) in 1998 It takes a serial 260KBit EEPROM, priced at $18 (Yes, from Atmel). I can buy a parallel EPROM for $3. What gives? Bruce Nepple Remove .nospam to e-mailArticle: 7163
What should I pay attention to, if I need to design a PLL or a logic which multiplies system clock, while using Synergy Synthesizer and Optimizer? Both Verilog and VHDL know-how's will be very useful. Thanks in advance. -- Utku Ozcan, http://www.ehb.itu.edu.tr/~utku/Article: 7164
Frank Gilbert <gilbert@informatik.uni-kl.de> wrote: >The online-help of XACTStep6000 (SunOS-Version) contains the following snip > > Simulation tools such as Synopsys VSS can both read and write this SDF >data. snip > >When I try to read the SDF-File generated by XACT6000 into VSS, I get >lots of errors like: > >**Error: vhdlsim,260: > (SDF File: mini.sdf Line: 54) generic >/MINI/REG/THOLD_CLR_C_noedge_posedge > is not declared. > >All the generics listed are not declared in the xc6000_VITAL.vhd file. > >I set up my synopsys-environment according to the manuals in the >synopsys-directory (Synopsys_flow.pdf, synopsys_lib_doc.pdf, ...). We >use Synopsys DC 3.5a here at the moment. > > >Best regards > >F. Gilbert >_____________________________________________________________ There are two incompatible versions of the VITAL standard out there, i.e. v2.2b and v3.0. Most of the recent tools use v3.0 (otherwise known as VITAL '95) and some allow you to switch between versions. Could it be that the version of VITAL written out by XACT is not the same as the version expected by the Synopsys tools ? -- Alasdair Maclean, Development Engineer GEC Marconi Electro-Optics Ltd., GNET: 709-5711; Tel: +44 (0)131-343-5711 Fax: +44 (0)131-343-5050 Email: <mailto:alasdair.maclean@gecm.com>Article: 7165
"Bruce Nepple" <brucen@imagenation.nospam.com> writes:
> An example
> Altera'a new EPF6016 is $22, decreasing to $12 (budgetary) in 1998
> It takes a serial 260KBit EEPROM, priced at $18 (Yes, from Atmel).
> I can buy a parallel EPROM for $3. What gives?
EPROM != EEPROM (parallel or not)
I doubt you get a parallel 256kBit EEPROM for that price.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 7166Bruce Nepple wrote: > > An example > Altera'a new EPF6016 is $22, decreasing to $12 (budgetary) in 1998 > It takes a serial 260KBit EEPROM, priced at $18 (Yes, from Atmel). > I can buy a parallel EPROM for $3. What gives? > Last time I checked, (over a year ago) the Atmel parts were at rough price parity with the non-reprogrammable Xilinx 17xxx parts and therefore were not a bad deal, but both are still outrageous compared to jellybean 27Cxxx EPROMs. The reason? Limited sales volume (microscopic compared to EPROMs), captive markets, and not much competition. I believe that the vendors would say they are providing the serial PROMS as a service and are basically just recovering costs. Since there is usually a microprocessor in a system that uses FPGAs, most cost-conscious designers go for serial or parallel download, in effect using cheap EPROM (or disk) instead of expensive serial PROMs. regards, tom (tburgess@drao.nrc.ca)Article: 7167
There is a comprehensive list of FPGA and CPLD consulting engineers available on the Programmable Logic Jump Station. See 'http://www.optimagic.com/consultants.html' for more information. We've indicated the companies that we've either worked with directly or are familiar enough with their work that we feel comfortable recommending them . . not that the others aren't good. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Michael G. Mansell <mansell@datavtion.com> wrote in article <33EA37AB.787E@datavtion.com>... | We require FPGA work done on our custom VME signal processing card | immediately (Xilinx based). Work involves modifying the VME address | decoding to work with new Motorola MVME2604 CPU. | Work has been estimated at 2-3 days and additional 2-3 weeks testing. | You can work onsite at our location and use our lab facilities! - | ViewLogic and Xact toolset. | | Please contact: | Mike Mansell | DataVation Inc. | North York, Ontario. | 416-665-0767 x228 |Article: 7168
Sam Falaki <Falaki@uqtr.uquebec.ca> wrote:
:> >> Has somebody tested the free actel software? Is it worth to download?
:> >> Is programmer support included? Is the ACTIVATOR needed or is there
:> >> a free design for a simple programming hardware.
:
:I managed to compile VHDL and target a very wide range of devices
:without even going through any tutorial or reading any "help"
:whatsoever. It's really easy to use. You can kind of guess your
:way along and next thing you know you're done. I liked it.
The software may be free (and good), but what else do you need to get
working silicon? A big-bucks programmer, maybe? The bottom line is the
cost of _all_ tools necessary.
Please, will one of the SRAM-based FPGA vendors put out something
similar? So we (the great impoverished <g>) can actually put their
chips to work in real systems.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7169>I'm totally blown away by the price of serial eeproms. >It seems I can buy a micro, parallel eprom, and a pal >cheaper than a serial part. Am I missing something? >(I hope). If you are using XILINX serial proms I agree. XILINX is very preditory on their pricing. So much so that it's probably illegal, although I don't know anybody who has sued them yet. They play some very nasty sales tactics.Article: 7170
In alt.comp.hardware.homebuilt David R Brooks <daveb@iinet.net.au> wrote: : Sam Falaki <Falaki@uqtr.uquebec.ca> wrote: : :I managed to compile VHDL and target a very wide range of devices : :without even going through any tutorial or reading any "help" : :whatsoever. It's really easy to use. You can kind of guess your : :way along and next thing you know you're done. I liked it. <snip> : Please, will one of the SRAM-based FPGA vendors put out something : similar? So we (the great impoverished <g>) can actually put their : chips to work in real systems. Please everyone using this, write actel, congratulating them on this move, emphasising that although you may be playing with it in your spare time, if a project you are working on goes to volume, then it makes you more likely to buy actel. They deserve some good feedback. Now, what I'd really like is a linux version :) Writing other FPGA vendors may be a thought too. Programmers can be hired from some places. About to look up the programming specs, to see how hard they would be to build. -- Ian Stirling. Designing a linux PDA, see http://www.mauve.demon.co.uk/ -----******* If replying by email, check notices in header *******------- What a wonderfull world it is that has girls in it! Robert A Heinlein. Shhh I'm huntin Windows. --PRRArticle: 7171
A new website has been established that contains summaries of recent issues of the Programmable Logic News & Views newsletter. This newsletter has been published for over five years and covers the programmable logic and associated design tools industry. You can order a complimentary copy of the newsletter from the website – http://www.plnv.com. Regards Murray DismanArticle: 7172
"Bruce Nepple" <brucen@imagenation.nospam.com> wrote:
:I'm totally blown away by the price of serial eeproms.
:It seems I can buy a micro, parallel eprom, and a pal
:cheaper than a serial part. Am I missing something?
:(I hope).
Have you looked at the Atmel AT17Cxxx parts? They replace the Xilinx
serials, and Atmel are usually pretty keen on pricing. You get
in-circuit programmablility as an extra. The ISP algorithm? Its just
I2C.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7173In article <33ebabe0.228220832@news.m.iinet.net.au>, David R Brooks <daveb@iinet.net.au> wrote: >Sam Falaki <Falaki@uqtr.uquebec.ca> wrote: > >:> >> Has somebody tested the free actel software? Is it worth to download? >:> >> Is programmer support included? Is the ACTIVATOR needed or is there >:> >> a free design for a simple programming hardware. >: >:I managed to compile VHDL and target a very wide range of devices >:without even going through any tutorial or reading any "help" >:whatsoever. It's really easy to use. You can kind of guess your >:way along and next thing you know you're done. I liked it. > > The software may be free (and good), but what else do you need to get >working silicon? A big-bucks programmer, maybe? The bottom line is the >cost of _all_ tools necessary. > > Please, will one of the SRAM-based FPGA vendors put out something >similar? So we (the great impoverished <g>) can actually put their >chips to work in real systems. > >-- Dave Brooks <http://www.iinet.net.au/~daveb> >PGP public key: finger daveb@opera.iinet.net.au > servers daveb@iinet.net.au > fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34 > What's all this? see http://www.iinet.net.au/~daveb/crypto.html --------------------------------------------- Last I looked, Altera had bought Intel's FlexPLD's and called them FlashLOGIC or such and they are FPGA's that are SRAM and EEFLash programmable with a LPT-JTAG cable I have the plans for that uses just one '244. I don't do PLD that big, so I haven't bothered, but that sounds like what you just asked for. Yes? No? All you need to do is hunt down the command to dump the SRAM to EEFlash, (they want to sell you software to do that one tiny bit, but it is a well known code), and you got it!! I THINK I still have that info! Write or call them! www.altera.com . -Steve -- -Steve Walz rstevew@armory.com ftp://ftp.armory.com:/pub/user/rstevew -Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew Europe:(Italy) ftp://ftp.cised.unina.it:/pub/electronics/ftp.armory.com Oz:.AU ftp://ftp.peninsula.apana.org.au:/pub/electronics/ftp.armory.comArticle: 7174
> > I want to design a card with a PCI interface.
> > 1. Can I make use of the DMAC of any 486/Pentium machines for data
> > transfers ? Or do I have to use a DMAC on my card and develop
> > an arbiter as well ?
>
This code will generate a burst write from the
cpu to a pci board if the board can handle
bursts.
/*
** This function talks to the on board RAM
** On the HOT Works board.
*/
void
Pci6200::writeRAM(unsigned long addr, unsigned long * data, unsigned
long count){
unsigned long addrRAM = addr + membase;
/* addr and membase come from the
driver and repersent the memory
mapped location of the board
*/
__asm
{
push edi
push ecx
push esi
mov esi, data
mov edi, addrRAM
mov ecx, count
cld
rep movsd
pop esi
pop ecx
pop edi
}
} /* end Pci6200::writeRAM() */
--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com
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