Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
does anyone here know where I can get a cache simulator which works for direct-mapped cache's written in x86 ? I need to see how it works right away. Please e-mail any info you have. Thanks in advanceArticle: 7126
On Sat, 2 Aug 1997 23:46:44 GMT, fliptron@netcom.com (Philip Freidin) wrote: >To a lesser extent, all of the Xilinx 4000 series (and derivatives, >including the Lucent devices that have RAM capability in the function >generators), have some reconfigurability possible by writing to the >function generators as ram, then using them as logic. But the first >mentioned devices are designed for partial config while running, whearas >the use of the function generator RAM is a bit of a stretch. ORCA is partially reconfigurable and was designed so to be. It has been that way, practically since day one. It's just that the idea of pertial reconfiguration sounds great, until you start doing it for real. Then you come up against all kinds of "issues" that need careful design optimisation to acheive a working solution. Most reconfigurable systems still seem to use one-shot total reprogramming. StuartArticle: 7127
In a previous article mush@jps.net (David Decker) writes: ;2. I've seen a switch that can switch a monitor, keyboard, :and mouse. among up to 4 live PC boxes. ;(OmniView Belkin F1D066 for ~$300.00.) :Is it any good? ; :2a. There is also the possibility of controlling multiple PCs on a ;network, remotely, from one PC. Carbon Copy, I think. Is this a better :way? Oh the shackles that microsoft made us wear. It is sad to see a whole lot of us getting driven to these contraptions in order to stay productive. The most attractive solution is to get UNIX boxes. With a site-wide licence, and a shell interface, you can start any number of runs on any number of machines from your machine at the office, at home, or anywhere. We do that routinely with ORCA FPGA software, which is a close kin to Xilinx M1. I can start them, put them in the back ground, go away and log in some some where else to check on them and continue to work on them. I do not currently have that luxury with the tool for another FPGA, and I am now sitting in my office waiting for it to finish so I can proceed with the next step, when I can be instead be waiting remotely at home, perhaps next to my pool.Article: 7128
Christine Price wrote: > > I too, would like to know how to do this using Altera EPLDs (7000S > parts). I did obtain from Altera the authorization to generate the > appropriate .SVF files from their .POF files. Altera doesn't seem to > have any app notes on how this information is to be used to actually > send this file over the JTAG port from a micro. I must not be looking > in the right place for the information. Contact your Altera FAE. They supposedly provided us with some sample code to do this - I haven't looked at it yet. We are doing ISP with XILINX 95000 parts, which may have given Altera more incentive to get us an alternative. XILINX has several app notes and sample C code (for 8051) on their web site. Steve Darby Huntsville Microsystems, Inc. http://www.hmi.comArticle: 7129
In article <33e4ec28.21766358@news.netcomuk.co.uk>,
Peter <z80@dserve.com> wrote:
>For example, when I did my last FPGA -> ASIC job, I found that the
>ASIC firm could not accept the Xilinx netlist format (XNF). It is hard
>to imagine someone advertising "Xilinx FPGA netlist conversion" and
>not being able to accept XNF. They could only accept a netlist from
>Cadence or Verilog or whatever (I am not familiar with these $50k+
>tools :))
>In the end, they wrote a converter for XNF to their in-house netlist
>format. A day's work.
>Next, they could not accept the Viewsim text vectors. NOW WHAT IS THE
>POINT in doing a FPGA -> ASIC conversion if the ASIC vendor cannot
>make use of (at least some) FPGA test vectors. Generating test vectors
>has always been a highly time consuming part of doing an ASIC, and
>being able to test the ASIC (certainly the ASIC vendor's simulation
>database, and ideally also the actual silicon) with those same vectors
>greatly reduces the risk. In the end, they wrote a test vector
>converter.
>Next, their library did not have a D-type with a clock enable. They
>thought that is the same as a D-type with an AND gate in the clock.
>This had to be sorted out.
He he... well it sounds like they're Xilinx capable now... :-)
(at your expense)
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7130Wen-King Su wen-king@myri.com wrote: >Oh the shackles that microsoft made us wear. It is sad to see a whole >lot of us getting driven to these contraptions in order to stay productive. >The most attractive solution is to get UNIX boxes. With a site-wide... This doesn't seem to be a Microsoft "shackle" since there are many ways to spawn a remote process under NT (and possibly even Win 95). This is more limited by the ORCA software which requires a hardware key to run on a PC. I can't think of a reason why ORCA wouldn't work with a dual-pentium PC. I have (accidentally) started two Place-n-Route processes on the same uniprocessor PC and had them both complete successfully.Article: 7131
>He he... well it sounds like they're Xilinx capable now... :-) >(at your expense) At my customer's expense :) Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 7132
Richard B. Katz wrote:
>
> hi,
>
> as part of a space flight instrument, a high speed digitizer is required.
> here's a brief specification.
>
> 1. sample rate >= 1 gigasample/second, 8-bit resolution; > 1.6
> Gigasample/second desired.
> 2. input bandwith >= 250 MHz
> 3. memory depth >= 32,000 samples; > 64,000 samples desired.
> 4. 100 MHz clock input, PLL to increase speed as needed
> 5. 80 Hz rate.
> 6. power <= 25 watts.
> 7. prefer mcm packaging
> 8. design life >= 8 years, 5 years on-orbit.
>
> we welcome any ideas that you may have. also, if you have experience in
> this area, like a good challenge, and would like to be considered for this
> assignment, please contact me (info at the bottom).
>
> one concept we're exploring is to use, for example, the 1 GSample/second
> SPT ADC and RAMBUS DRAMS. This can give us a huge memory (and cheap
> redundancy) and is a bonus for the system design. for this, obviously, we
> would like a high-speed asic to provide the connection between the ADC (500
> MHz w/ the 1:2 on-chip demux) and the RDRAMs for acquisition and system
> logic for readout (which is relatively slow). spt adc and RDRAMS have
> already passed preliminary radiation tests and are currently undergoing
> construction analysis.
>
> other concepts are being explored and feel free to come with a clean sheet
> of paper.
This is a straightforward problem. The solution can be messy. The SPT
ADC
is an ECL device, and you have to use ECLinPS logic to multiplex the
data
out to a wide enough bus to match your 1 Gbyte/sec data rate to the
cycle
time of your memory.
The 1989 Gigabit Logic Databook had an advance data sheet on the 12G044
1024x4 3.onsec cycle/access time SRAM. If you have loads of money you
might try to find out what has happened to them, and check out the other
GaAs
sources. Gigabit's GaAs was defintely ECL compatible - Vitesse was more
TTL
oriented.
The fastest ECL memory I could find the last time I looked was the 4kx4
IDT100E474-2.7 which has a 2.7nsec access time, and should allow you
to work with a 32-bit bus, if you can actually buy them. The 100474 has
been
around for a good ten years now, but the suppliers I used in 1989 don't
seem
to be making the part any more.
IDT's Dutch agents failed to quote me either price or delivery last
year,
and e-mailing IDT direct got me a polite response, but no information.
Either they couldn't make them (and I wasn't actually interested in the
fastest version) or they thought I was Saddam Hussein in disguise,
buying
for a better radar system. If the latter was the case, you should do
better.
Failing that, you are looking at fast TTL SRAM. Paradigm and Motorola
both
advertise synchronous CMOS SRAMs that can be cycled at up to 100MHz -
which leaves you with an 80-bit wide bus - butlast year they weren't any
more
obtainable than the IDT parts.
Actel's ACT3220DX-1 offers 5nsec SRAM in a fast, one-time programmable
FPGA, which is probably the way to go if you can afford the price - $250
per FPGA, and $2,500 for the programming software. The prices were
quoted by the Dutch agents, so you might well get the stuff cheaper.
I ended up settling for 15nsec CMOS SRAM - which I could buy from
Farnell -
and cycling it at about 26nsec with 4x multiplexing to give me 6.5nsec
in the ECL, which was enough to keep the client happy. Loads of
components
though, and lots of worst case tolerancing on propagation delays.
The Timing Designer CAD softeware might have made that easier, if we
could
have justified the price.
Bill Sloman | Precision Analog design.
TZ/Electronics, Science Faculty | Fast analog design and layout.
Nijmegen University, The Netherlands | Very fast digital
design/layout.
| e-mail for rates and
conditions
Article: 7133Georg: You don't actually say whether this is a gate or rtl level. Like Thomas i will also assume that this is a gate level model. From your description it appears you have either hit a bug / pathological case for VSS or have some sort of runaway recursion in your model. Under normal circumstances a single FPGA worth of gates should be easy to simulate in VSS. I have run 100k gate asic in interpreted VSS on a Sparc 2 with 64 MB physical memory, and perhaps 400 MB swap. (Don't the think all the swap was needed, just that the configuration had it). So insufficient hardware is not your problem. I would suggest trying to simulate block by block going bottom up from small blocks in your design to isolate the problem. Also look very closely at any warnings that show up along the way. Another place to look is the library; how efficiently it is coded etc. Is it possible you have runaway recursion in a test bench or some such ? It is sort of amusing that Thomas suggests a emulator as a solution to a single FPGA design. You might as well program the target FPGA and start simulating ? of course the emulator would provide better visibility. However, i think emulation is serious overkill for a single fpga design. Thomas Berndt wrote: > > Georg Diebel <g_diebel@lis.e-technik.tu-muenchen.de> writes: > > > Hi everybody, > Hi too, > > > Now the Problem: > > > > I have a VHDL design targeted for a Altera FLEX FPGA (10K50). > So far so good. > > > When I try to simulate these designs (Synopsys VSS), first everything > > looks good, but when I try to set a trace (view a waveform), the > > simulator gets to work (on what I don't know) and won't stop and > > won't react to anything (at least for the 4 hours I had the patience > > to wait). > What do think about Hardware/Software-Cosimulation. The partitioning > your design to components for simulation at all and components for > emulation at a prototyping board coupled to a HDL-Simulator is up to you. > The sight to the emulator partition is as a HDL entity. > But now, you can achive a significant speed up depend on the design. > > > OK, then I figured that this VHDL design simply was too large for > > the *interpreted* VHDL-simulator from Synopsys and hence tried to > > analyze the VHDL for the "compiled" mode. This took about 3 hours > > (yes, only analyze & compile) before the job ran out of memory and > > aborted. Oh, I was running it on a UltraSparc with 600 MB physical > > memory and about 1.2 Gig of swap space ... wouldn't know where to > > find a bigger machine here at the institute. > Our HW/SW-Cosimulation environment supports also the VSS from Synopsys. > > > Now, what to do? > Have a look at http://www.eas.iis.fhg.de/sim/projects/dfg/welcome_de.html > > > Looking forward to any ideas! > Hope this helps. > > Yours, > > Thomas -- regards, Ramesh (Ramesh Narayanaswamy)Article: 7134
[This followup was posted to comp.lsi and a copy was sent to the cited author.] In article <5rtcei$cof$1@news.rain.net>, lindab@qualis.qualis.com says... > > Qualis Design Corporation has published the Fall schedule for our many > hands-on, application-focused courses in VHDL- and Verilog-based design. > Our courses are like no other -- just take a look at our lineup: > > VHDL System Design > ------------------ > Introductory: > High Level Design Using VHDL > System Verification Using VHDL > VHDL for Board-Level Design > Elite: > ASIC Synthesis and Verification Strategies Using VHDL > Advanced Techniques Using VHDL > > VHDL Synthesis > -------------- > Introductory: > VHDL for Synthesis: A Solid Foundation > Elite: > ASIC Synthesis Strategies Using VHDL > Behavioral Synthesis Strategies Using VHDL > > For more info on our suite of HDL classes, to review our Fall schedule, > or if you're interested in an on-site class, check out our web site at > http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700. > > > Qualis Design Corporation > 8705 SW Nimbus Suite 118 > Beaverton OR 97008 USA > Ph: +1.503.644.9700 Fax: +1.503.643.1583 > http://www.qualis.com > > Copyright (c) 1997 Qualis Design Corporation > > Do we really need to see these posts every week? -wasArticle: 7135
In a previous article husby@fnal.gov (Don Husby) writes: : ;Wen-King Su wen-king@myri.com wrote: :>Oh the shackles that microsoft made us wear. It is sad to see a whole ;>lot of us getting driven to these contraptions in order to stay productive. :>The most attractive solution is to get UNIX boxes. With a site-wide... ; :This doesn't seem to be a Microsoft "shackle" since there are many ways to ;spawn a remote process under NT (and possibly even Win 95). This is more :limited by the ORCA software which requires a hardware key to run on a PC. ; :I can't think of a reason why ORCA wouldn't work with a dual-pentium PC. ;I have (accidentally) started two Place-n-Route processes on the same :uniprocessor PC and had them both complete successfully. Of course you can do anything if you were to be writing the program. The question is why doesn't the vendors do it. I would say that it is because of the absence of support in windows NT. The nature of the O/S contributed to the absence of software that allows you to work this way. For example, the idea for using a set of network connected computers certainly isn't foreign to the Lucent people. Their workstation version of the ORCA software has a multicomputing option. You first prepare a file containing a list of unix machine names. When invoked, the server automatically distribute the sub passes of a place and route job -- there can be 100 to each job -- to different machines and keep them busy all the time until the job is done. Why don't they do it for NT? I don't think dongle is what is limiting it because floating license is easily available, and dongles are cheap.Article: 7136
> I want to design a card with a PCI interface. > 1. Can I make use of the DMAC of any 486/Pentium machines for data > transfers ? Or do I have to use a DMAC on my card and develop > an arbiter as well ? You cannot use the DMAs in the PC for PCI. The DMAs used in a PC are slow and feeble, so you would not want to use them even if you could. > 2. If I can indeed use the DMAC of the 486/Pentium do I need a > PCI/ISA bridge ? (since I cannot find any signals related to > DMAC on the PCI interface) PCI doesn't use a concept like DMA, which is a 'third party' data transfer engine. PCI uses a thing called 'Initiator', which means the PCI device that wants to do the trasfer 'takes over' the PCI bus, and controls all the PCI signals for the duration of that transfer. > 3. And how do I get to know which of the channels of the DMAC have > been already used by the system (for eg. for floppy > disks/controllers ) and which are free to be used by a new I/O > device ? Not needed since you can't use them. You may want to get the Solari book on PCI from Annabooks (www.annabooks.com) and a copy of the PCI 2.1 spec from the PCI SIG. Austin Franklin darkroom@ix.netcom.comArticle: 7137
David Decker wrote: > ____ > I believe I could be more productive producing large, DSP, intensive, > Xilinx designs, with two or even more PCs. I believe it would greatly > reduce the dead time during long simulations, and place and routs. > <snip> > 1. If I do FPGAs all day long, and most evenings too, Extra PCs are > easily justified, Right? Even $8k or $9k PCs, right? In a network > environment, are two PCs enough? Please help me out here. I'm trying > to sell my boss. > I didn't know it was possible to do that with a boss:-) I can't speak for the PC environment, but I would like to stress a point about running M1 on multiple machines. We can run several UNIX machines in parallel on a single design. However, they are not truly parallel processes. The machines are all performing place and route on the same design, but using different constraints (or optimized for different goals). We then (manually) choose the best optimization. Unlike parallel processing, this will not reduce your simulation time or your place and route time (if it took 4 hrs on one machine, it'll take 4 hrs on two machines but you'll have two results to choose from). Apart from that, your machines have to be networked to share the project files, and you have to get a $pecial license from Xilinx. Tim. -- You better be doing something so that in the future you can look back on "the good old days" My opinions != Nortel's opinionArticle: 7138
wen-king@myri.com (Wen-King Su) wrote: >:2a. There is also the possibility of controlling multiple PCs on a >;network, remotely, from one PC. Carbon Copy, I think. Is this a better >:way? If you want to control PCs remotely, there is an excellent tool called LapLink for Windows '95. It works over networks, modems and direct connect cables. I've also seen multiprocessor PC's in VMEbus racks. There are a bunch of people who make VMEbus PC's, and you just plug them into the rack. This solves the hardware problem, but not the software. ----------------------------------------------------- Wade D. Peterson | TEL: 612.722.3815 Consultant to Industry | FAX: 612.722.5841 3525 E. 27th St. No. 301 |---------- EMAIL ---------- Minneapolis, MN 55406 | peter299@maroon.tc.umn.edu ---------------- Committed to Quality ---------------Article: 7139
Philip Freidin wrote: > > In article <amaraju-2807971248030001@ppp11-5.dllstx.onramp.net> amaraju@onramp.net (Executive Search) writes: > >Due to explosive growth in our FPGA product line, this Microelectronics > >group of a $23billion Communications company is seeking a very talented > >engineer for a MTS FPGA Field Applications Engineering position. > > Potential applicants should contact ATT/Lucent directly and bypass the > middle man who doesn't have the courtesy to keep job postings out of a > technical news group, and put them where they belong. By going direct you > will save Lucent big bucks, and so will be able to ask for a great signing > bonus. (negotiate 50% of the head hunter's fee you are saving them). > > Philip Freidin Touche!Article: 7140
In article <33e49f99.1960147@nntp.netcruiser>, s_clubb@netcomuk.co.uk says... > >On Sat, 2 Aug 1997 23:46:44 GMT, fliptron@netcom.com (Philip Freidin) >wrote: > >>To a lesser extent, all of the Xilinx 4000 series (and derivatives, >>including the Lucent devices that have RAM capability in the function >>generators), have some reconfigurability possible by writing to the >>function generators as ram, then using them as logic. But the first >>mentioned devices are designed for partial config while running, whearas >>the use of the function generator RAM is a bit of a stretch. > >ORCA is partially reconfigurable and was designed so to be. It has >been that way, practically since day one. It's just that the idea of >pertial reconfiguration sounds great, until you start doing it for >real. Then you come up against all kinds of "issues" that need careful >design optimisation to acheive a working solution. > >Most reconfigurable systems still seem to use one-shot total >reprogramming. How long takes an 'one-shot total reprogramming' ? Milli seconds ? Seconds ? Greetings ArminArticle: 7141
Help! I've got a tough problem.
I've taken over a large Verilog design targeted at Xilinx.
I have run the usual script commands to process the design,
including the replace_fpga commang to get the IOB's converted
to gates. But I get this error on one module of my design:
Error: Cell instance 'U793' in design 'mbibcmbusif' is an IOB. Xilinx
does not allow IOB symbols in XNF for their 4000 family FPGAs.
Please run the command 'replace_fpga' to convert the IOBs
in this design to gates. (XNFO-11)
An experts know what might be the problem?
I've looked at the source, the gen'd schematics & don't quite know
how to tie the instance # back to anything I can change.
The schematic has a half dozen IOB on the sub-modules, one of
which is the one it complaining about. nothing obviously different
than the other on the page.
Only thing I can figure out is some how
IOB's have ben inserted at a lower level than the top module.
Here's my script:
---------------------------------
TOP = "evs_mcib"
PART = "4020epq240-4"
read -format verilog TOP + ".v"
current_design = TOP
set_port_is_pad "*"
set_pad_type -slewrate HIGH all_outputs()
insert_pads
remove_constraint -all
create_clock "CLOCK" -period 50
link
uniquify
compile
uniquify
write -format db -hierarchy -output TOP + ".db"
replace_fpga -group_cells
set_attribute TOP "part" -type string "4020epq240-4"
xnfout_library_version = "2.0.0"
write -hierarchy -format xnf -o TOP + ".sxnf"
quit
-----------------------------------------------
Article: 7142On 5 Aug 1997 11:35:35 -0700, Armin Steinhoff <Armin@Steinhoff.de> wrote: >How long takes an 'one-shot total reprogramming' ? Milli seconds ? >Seconds ? Depends how you do it. Serial can be long if you run at a low data rate, however, using Slave Parallel mode for byte wide programming every clock cycle, you can stuff data in at one byte every 66 nS. That enables typical programming times of: OR2C04A <1 mS OR2C40A <6 mS Pretty quick. StuartArticle: 7143
John, bob elkind wrote: > > Also, in general the only two available (64KB) pages in the > lowest 1M of system address space are D000:xxxx and E000:xxxx. > It would be well for you to maximise your chances of success > by limiting yourself to one of these pages, and not use both. > My experience with using D000:XXXX recently was that it caused a Trident ISA graphics card to fail. I found that this was only at boot time when using the byte-wide extended BIOS at C000. A solution which worked was to hold off MEM_CS16 use until well after boot time, when the BIOS had been copied into shadow RAM. This may be a bit too machine-specific for you. Hope this works for you. Tim Shuttleworth, (tim_shuttleworth@discreet.co.uk) Discreet Logic, Newbury, EnglandArticle: 7144
Tim said... > bob elkind wrote: > > > > Also, in general the only two available (64KB) pages in the > > lowest 1M of system address space are D000:xxxx and E000:xxxx. > > It would be well for you to maximise your chances of success > > by limiting yourself to one of these pages, and not use both. > > My experience with using D000:XXXX recently was that it caused a > Trident ISA graphics card to fail. I found that this was only at > boot time when using the byte-wide extended BIOS at C000. A solution > which worked was to hold off MEM_CS16 use until well after boot time, > when the BIOS had been copied into shadow RAM. This may be a bit too > machine-specific for you. I believe it. Why am I not surprised? There's a message here for anyone "wanting" to do ISA bus design! Tim, thanks for the wakeup call... -- Bob **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 7145
Paul, > This was several years ago. The ACT1280A ran around C$300. The replacement > ASIC in PPGA was around C$70. If you looked at industrial or mil temp the > cost difference was even more pronounced. I don't know that this information from several years ago is really applicable to the cost of doing a conversion today...though it might track linearly that a current $300 FPGA would cost $70 in ASIC...but I don't know any ASIC house that will make you only 100 chips without a huge NRE, or amortizing the NRE on top of the price of the chip. 100 chips at $70 is only $7000, and this is just not profitable for an ASIC house to want to do. That sounds more like a 6 layer PCB price than a 10k ASIC price...and is a lot less work for the fab house. > It took a lot longer than that but most of the effort was putting stuff > back into the design that was stripped to fit the FPGA. I also simulated > the ASIC to death to ensure no spin. Sounds to me like you took even more time to do this than I figured into my speculative cost analysis.... > > If you could post your actual numbers (actual NRE, minimum number of chips > > you had to order, and at what price, how many hours it took for you to do > > this 'conversion') this would make your numbers more 'compelling'. > > Do you want the bill of materials and customer list as well ? ;-) Nope, just truth in advertising. I just wanted to see your claim substantiated that all the time you put in to this conversion, plus the NRE etc. was paid for with only 100 chips. I am not saying you are not telling the truth, please do not take my questioning your claim personally...but my experience does not bear out your cost analysys, and I would like to understand why. The truth will bear it self out in the numbers, not in speculation or opinion (this IS an engineering group...:-). You made a conclusion, and I asked if you would provide the data on how you arrived at that conclusion. I just want the TRUTH! (Tom Cruise) You CAN'T handle THE truth! (Jack Nickelson) Austin Franklin darkroom@ix.netcom.comArticle: 7146
David, > I believe it would greatly > reduce the dead time during long simulations, and place and routes. I can't reduce your simulation time, and I don't know if you already do this, you can reduce your place and route time to 1/10th or more what it could be.... use a constraint file (or what ever it is in what ever software you are using) to place the regular items in the design optimally, and also lock all your bussed pins (data bus I/O, and address I/O etc, if not all your I/O pins) 'intelligently'. I haven't seen any router software that does anywhere near as good a job as manual placement of registers, counters, tbufs, muxes, basically any data path item...and 'most' I/O pins. I have taken designs that have a 32 bit bus running through them in a Xilinx 4013 and run them without my constraints file, and they take hours and hours on a PPro 200 machine, and don't get very good results. They take 20 minutes max on the same machine, and always make timing, with the constraints file. I've never had a route run more than 30 minutes (these days) with good placement as I have suggested above. There are many ways to reduce your simulation time....but I don't know exactly what you are simulating. Simulations are based on previous results, and therefore by definition are mostly a serial process (quite design dependent though...), and usually would not benefit from multiple processors very much. There are instances where this would not be quite true though.... Austin Franklin darkroom@ix.netcom.comArticle: 7147
I'm totally blown away by the price of serial eeproms. It seems I can buy a micro, parallel eprom, and a pal cheaper than a serial part. Am I missing something? (I hope). Bruce Nepple remove .nospam to emailArticle: 7148
eteam.nospam@aracnet.com (bob elkind) wrote: >Tim said... >> bob elkind wrote: >> > >> > Also, in general the only two available (64KB) pages in the >> > lowest 1M of system address space are D000:xxxx and E000:xxxx. >> > It would be well for you to maximise your chances of success >> > by limiting yourself to one of these pages, and not use both. >> >> My experience with using D000:XXXX recently was that it caused a >> Trident ISA graphics card to fail. I found that this was only at >> boot time when using the byte-wide extended BIOS at C000. A solution >> which worked was to hold off MEM_CS16 use until well after boot time, >> when the BIOS had been copied into shadow RAM. This may be a bit too >> machine-specific for you. > >I believe it. Why am I not surprised? There's a message here >for anyone "wanting" to do ISA bus design! Digging deep into my memory the 16 bit ISA bus extension has some duplicated high order address lines which appear earlier than the normal ones. You are supposed to decode these to drive MEM_CS16. The lines can only decode 128k blocks so you can't mix 8 and 16 bit areas within a 128k block - it used to be a problem when installing 8/16bit VGA and 8 bit monochrome adapters - the presence of the mono adapter always forced the VGA into 8 bit mode (under control of it's BIOS I supposed) and slowed it down. Cheers Terry...Article: 7149
Thanks for your comments, Austin, but I'm not asking about multiprocessors, I'm asking about multiple PCs where I could do simulation on one machine, Place and rout on another and schematic capture on another. I know you can do all this on one machine, but Win95 has a way of killing the job one way or another. Sometimes I do get away with doing more than one thing at a time, but it's dangerous. I do RLOC the data paths, and LOC the I/O pins, but I'm working on three big DSP designs, all with multiple 4025Es. Most place and rout in about 1 hour (not counting 'translate') on a 133MHz. Pentium. I would just like to keep busy, and not have to wait for the machines. I'm upgrading my one machine and just wondered if I should get a second or third. The biggest speed up for functional simulation is to use the fxc libraries instead of the xc. Some simulations still take a long time because I have to integrate results over thousands of bits using some algorighm or another. Some times you have to wait for a digital PLL to lock up. Some times I'm using many 'check' loops to create many files, one for each test point. These test points are 8 or more bits wide, 2's compliment numbers which are best observed graphically, using MatLab or Excel, since ViewTrace is crippled in that respect. There really are many reasons why some simulations take a long time. Thanks again to those who have responded to my query. Dave Decker Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost House
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z