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Martin Mason wrote: > > How about comp.arch.fccm This one, I like. Makes some sense to me. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 6601
FS: CADKEY '97 -100+ Available- Save $HUNDRED's EACH!!! Hello! A new copy of Cadkey 97 is selling on the street for $1,195. To guarantee updates for the next year costs $350 more, bringing it up to $1,545 total! We have available over 100 NEW unopened, shrinkwrapped copies of Cadkey 6.0 on CD for DOS which can be upgraded to Cadkey 97, INCLUDING the year's worth of free updates, for the street price of $595; that's $950 less than the normal street price! Or, maybe Cadkey 6.0 has enough power for you with no upgrade at all! (Cadkey '97 is basically Cadkey 8.0) I'm selling these for best offer, one or all. If you would like more info on Cadkey 97, here's Cadkey 97's Web page: http://www.cadkey.com/cadkey/index.htm Thanks! Karl KristiansonArticle: 6602
Stuart, The Xilinx PCI design is a good starting point to some degree. It is 'well' documented, and has some nice 'features'. I don't know what kind of a deal they cut with High Gate for them to do the design, but I didn't really want much $$$ from them in the first place (I believe it was 10k), so I never really understood what happened, they just literally dropped it on the floor and never got back to me. 'Someone' probably told Xilinx they could do a 'better' job or something like that... ;-) It is tough to make a 'generic' PCI interface for a Xilinx. Most of the work (%70) is in interfacing the PCI to the back end. You can make 'generic' configuration registers and a kind of generic target state machine, but there is a lot of logic that has to be tailored to the back end functionality/design that can't really be made generic, if you want to make it fast (PCI cycle wise) and make timing. Master timing is the hardest to make, because you have to use almost all the signals straight off the PCI bus. I just found an interesting PCI bug having to do with the Intel chip sets. When a target issues STOP, it is required that the master (Intel chip set) release FRAME in the next cycle. Well, some Intel chip sets don't. What this means is a target state machine can spin on it self if it assumes FRAME will be removed (per spec) deterministically! In order to avoid this situation, you need to use the raw FRAME right off the PCI bus, which, requres you to only go though one FMAP and make sure the logic is placed correctly if you want to make timing. The probable reason this has not been a problem for most designs, is because there is another requirement to keep STOP issued until FRAME is de-asserted...therefore most target state machines will spin in state BACKOFF until FRAME is de-asserted, instead of just 'visiting' backoff 'knowing' FRAME will only be valid for one more cycle.... Austin Franklin darkroom@ix.netcom.comArticle: 6603
Adam J. Elbirt wrote:
>
> Viewlogic will be presenting the Advanced FPGA Design Demonstration at DAC.
>
[deleted]
or ...
Got G.E.T.?
Galileo Extreme Technology
See us at Booth 852 - Design Automation Conference
June 8-10 in Anaheim, California
and ...
bring the designs with you,
you know, the ones
that you were never able to run through
with other systems!
--
-----------------------------------------------------------------------
Dr. Nils Endric Schubert schubert@exemplar.com
Exemplar Logic
815 Atlantic Avenue, Suite 105
Alameda, CA 94501
Tel.: (510) 337 3761
Fax.: (510) 337 3799
http://www.exemplar.com
-----------------------------------------------------------------------
Article: 6604
Martin Mason <nospam_mtmason@ix.netcom.com> writes:
> How about comp.arch.fccm
>
> Those of us remotely involved in the industry know this term - right ???
Yes. But you also see how an FCCM need not be an RPU and therefore
would not fit the original proposal. I have some sympathy for this
idea, but the proponents would need to rework their agenda for it to
fly.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 6605We are doing a survey on anti-virus software for one of the major manufacturers and would like to include your opinions,IF YOU HAVE PURCHASED VIRUS DETECTION SOFTWARE WITHIN THE PAST THREE MONTHS. In return for your participation, you have the chance to receivea free copy of the latest virus detection software from one of the leading manufacturers. IF YOU ARE ONE OF THE FIRST 200 PEOPLE TO COMPLETE THE SURVEY, AND GIVE US EITHER A VALID EMAIL ADDRESS OR PHONE NUMBER, YOU WILL BE ENTERED INTO A DRAWING FOR THE ANTI-VIRUS SOFTWARE. The survey is located at: http://www.market-research.com/triton/HRC103/index.html Please, we are not trying to sell you anything. All we want is your help. You will not be contacted by anyone except (in some rare cases) to validate responses, or to deliver the software you have won. All of your answers will be kept completely confidential. Horizon Research Corporation is an independent research firm, not associated with any particular manufacturer. For further information about our company, email us at info@market-research.com . Thanks in advance for your help.Article: 6606
> >From reading this posting, it looks like Altera documentation has > been > >misread by another NG member. > > > >Read the documentation fully. I did. So I would suspect have most > >others following the thread where we started and finished this one. > > > >Altera FLEX10K is not PCI compliant. > >Every device they have shipped is not compliant. > >Every part sitting with their disti network is not compliant. > >Every piece coming off the line is not compliant. > > > >End of story. Dead, buried, WORM FOOD. Alright, but what exactly makes Altera's non-PCI compatible ??? Here, we have used both FLEX8000 and FLEX10K successfully to make prototype PCI boards. I do agree, that if does work, is NOT necessary PCI-Compiant. We have used our own VHDL PCI interface and not Altera's Free or Megacore. > Stuart > A Lucent distributor speaking for himself. You may be pleased to hear since then, we have switched to ORCA 2C40s which IMHO are by far more sophisticated FPGAs/CPLD. Regards JacArticle: 6607
I wholeheartedly support Michael's proposal for a comp.arch.rpu group. I do not regularly read comp.arch.fpga for precisely the reason he mentions - the substantial emphasis on FPGA hardware and CAD - and so I no doubt miss out on interesting contributions on reconfigurable computing, which is my main research area. So, the sooner the better, as far as I'm concerned. Gordon.Article: 6608
Qualis Design Corporation has released the Fall schedule for our many
hands-on, application-focused courses in Verilog- and VHDL-based design.
Our courses are like no other -- just take a look at our lineup:
Verilog System Design
---------------------
Introductory:
High Level Design Using Verilog (5 days)
System Verification Using Verilog (5 days)
Verilog for Board-Level Design (5 days)
Elite:
ASIC Synthesis and Verification Strategies Using Verilog (5 days)
Advanced Techniques Using Verilog (3 days)
Verilog Synthesis
-----------------
Introductory:
Verilog for Synthesis: A Solid Foundation (5 days)
Elite:
ASIC Synthesis Strategies Using Verilog (3 days)
Behavioral Synthesis Strategies Using Verilog (3 days)
For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site at
http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700.
Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700 Fax: +1.503.643.1583
http://www.qualis.com
Copyright (c) 1997 Qualis Design Corporation
Article: 6609
Qualis Design Corporation has released the Fall schedule for our many
hands-on, application-focused courses in VHDL- and Verilog-based design.
Our courses are like no other -- just take a look at our lineup:
VHDL System Design
------------------
Introductory:
High Level Design Using VHDL (5 days)
System Verification Using VHDL (5 days)
VHDL for Board-Level Design (5 days)
Elite:
ASIC Synthesis and Verification Strategies Using VHDL (5 days)
Advanced Techniques Using VHDL (3 days)
VHDL Synthesis
--------------
Introductory:
VHDL for Synthesis: A Solid Foundation (5 days)
Elite:
ASIC Synthesis Strategies Using VHDL (3 days)
Behavioral Synthesis Strategies Using VHDL (3 days)
For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site at
http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700.
Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700 Fax: +1.503.643.1583
http://www.qualis.com
Copyright (c) 1997 Qualis Design Corporation
Article: 6610Mailloop v3.0 is an industrial strength bulk mailer. Mailloop v3.0 is a bulk mailing program for the internet. It can take a single message and broadcast it to either a listing of e-mail addresses or to a listing of newsgroups. Creates custom newsgroup lists by filtering NNTP servers. Creates custom e-mail lists by extracting them from newsgroups. Can also extract e-mail addresses or newsgroup names from other protocols. Built-in NNTP, SMTP, POP, FTP, HTTP, EXEC, CGI, WHOIS and FINGER clients. Anti-cancelbot feature. Automatically processes remove requests. Includes extensive on-line help. The most powerful bulk mailer available. Requires Windows 95 or NT 3.51+ and internet access. The "Program" Mailloop is only available in English. For more info goto: http://205.199.4.219 http://205.199.4.219 Using it is easy: 1) Create a message ( http://205.199.4.219/editor.htm ) ...by using the pull down menus or ...by using any editor 2) Create a newsgroups list ( http://205.199.4.219/news3.htm ) ...by filtering an NNTP server or ...by importing from any text file or ...by manually creating with any editor or ...by extracting from any FTP file or ...by extracting from any HTTP file 3) Create an e-mail list ( http://205.199.4.219/em3.htm ) ...by extracting from newsgroups or ...by importing from any text file or ...by manually creating with any editor or ...by extracting from a WHOIS response or ...by extracting from a fingering response or ...by extracting from a UNIX response or ...by extracting from any FTP file or ...by extracting from any HTTP file or 4) Broadcast the message ...to the e-mail list or ( http://205.199.4.219/embc.htm ) ...to the newsgroup list ( http://205.199.4.219/ngbc.htm ) 5) Then process the remove requests ...by using the mailbox processor ( http://205.199.4.219/pop.htm ) 6) If you want you can use the Newsletter Sever ...The Newsletter Sever will allow you to have an topic-specific newsletter that other can subscribe and unsubscribe to. ...Customizing this server response files ( http://205.199.4.219/response.htm ) ...Creating a new newsletter ( http://205.199.4.219/create.htm ) ...Creating and Updating a newsletter the actual newsletter ( http://205.199.4.219/update.htm ) For more info visit http://205.199.4.219 http://205.199.4.219Article: 6611
On 3 Jun 1997 18:56:37 GMT, johnm@Newbridge.COM (John McDougall)
wrote:
>>>>2) What is the feeling about attempting to re-solder such pins if a
>>>>connection seems to be flakey? Am I wasting my time trying to fix it?
>>>>Maybe if some pins have flakey connections then others on the same
>>>>chip are likely to (eg. if some are bent down too much, then obviously
>>>>the others are at a different level...).
>>>>
>>>
>>Resoldering can be done, but I am no good at it. Sometimes the chip has
>>to be removed and the board traces will only handle 3-4 removals before
>>the traces separate from the board.
>>
>>The easiest solution for me was to go with the Altera 208PQFP socket since
>>I'm using an OTP FPGA.
>
>I use a hot-air gun with a small nozzle. Works great.
>
Emulation Technology makes a produces called ChipQuik which consists
of a heavy-duty flux and special low-temp alloy. All you have to do
is apply the flux to the pins of a part you want to remove and then
apply a bead of the alloy, effectively shorting all the leads
together. You then heat the PWB from the back-side with a heat gun
and pick up the offending device with a vacuum pen. I'm sure an IR
rework station would also work. Remove the excess alloy with solder
wick and it's ready to go.
It's quick, easy, and results in ZERO damage to the PWB. If you are
careful you can even re-use the device you are removing. Cost of the
kit is $47Cdn. I can remove a 144-pin TQFP and have the sight clean,
ready for new part, in 10 minutes.
Garnett
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Tel.: 613-731-6788 ext 120 Ottawa ON K1C 1V1
Fax: 613-731-1013 http://www.chrysalis-its.com
Eml: ghamilton@chrysalis-its.com
Article: 6612In article 1@sahand.usc.edu, jlou@sahand.usc.edu (Jinan Lou) writes: > Hi, all, > > We are about to make a decision on purchasing a FGPA synthesis tool. > The candidates are FPGA Express from Synopsys and Synplify from > Synplicity. The target FPGA is Lucent OR2C40A (40k gates), and the design > is about 100k in size. > > We would like to know which one can handle the size of the design well, > which one will produce a better result, and which one will run faster. > Your comments are really appreciated. > > > Please send your comments to Jinan.Lou@tanner.com. > > > Thank you in advance > > > Jinan > > Hi Jinan, You should also take a look at ViewSynthesis by Viewlogic. Viewlogic has worked extensively with Lucent, as well as other FPGA vendors, to optimize designs to the specific vendor family. ViewSynthesis will have no problem handling your 100k gate design. ViewSynthesis is available as part of the Workview Office tool suite. In addition to FPGA synthesis there is schematic capture, VHDL and gate level simulation, and an FPGA design flow manager called IntelliFlow. IntelliFlow integrates the simulation, synthesis and the vendor place and route in to one design environment. It effectively creates a push button FPGA design process. Check out ViewSynthesis and IntelliFlow at DAC or visit the Workview Office website at www.workviewoffice.com. You can also download a demo of ViewSynthesis from www.workviewoffice.com/WVOffice/viewsynthesis /synthdownload.asp. ChrisArticle: 6613
Why not comp.arch.fpga.rpu ? ...which would keep it close to the current group and would make the name more understandable, since "rpu" is not yet a well known acronym.Article: 6614
In a previous article "Austin Franklin" <darkroo4m@ix.netcom.com> writes:
;I just found an interesting PCI bug having to do with the Intel chip sets.
:When a target issues STOP, it is required that the master (Intel chip set)
;release FRAME in the next cycle. Well, some Intel chip sets don't. What
:this means is a target state machine can spin on it self if it assumes
;FRAME will be removed (per spec) deterministically! In order to avoid this
:situation, you need to use the raw FRAME right off the PCI bus, which,
;requres you to only go though one FMAP and make sure the logic is placed
:correctly if you want to make timing.
Rule 5 on page 42:
Whenever STOP# is asserted, the master must deassert FRAME# as soon
as IRDY# can be asserted.
There is no rule that says IRDY# must be asserted in the next cycle, so
FRAME# does not have to be deasserted in the next cycle. So the Intel
chip set is not technically in error.
However, I do PCI implementation on FPGA as well, and what I find is that
due to the constraints of FPGA, we are forced to operate in a region of
legal PCI behavior space that is rarely visited by the more common ASIC
PCI implementations. Thus we keep running into bugs in systems that
otherwise works well with devices using ASIC PCI implementations.
Article: 6615Garnett Hamilton wrote: > Emulation Technology makes a produces called ChipQuik which consists > of a heavy-duty flux and special low-temp alloy. All you have to do > is apply the flux to the pins of a part you want to remove and then > apply a bead of the alloy, effectively shorting all the leads > together. You then heat the PWB from the back-side with a heat gun > and pick up the offending device with a vacuum pen. I'm sure an IR > rework station would also work. Remove the excess alloy with solder > wick and it's ready to go. A hot air gun is cheaper, and won't leave you with some questionable alloy on the pads. I loop some non-insulated wire (26 AWG) under the pads of the device, and hold up the board by the wire. When the chip gets hot enough, it will come off without board damage. -------------------------------------------------------------------- Pascal Dornier pdornier@pcengines.com http://www.pcengines.com Your Spec + PC Engines = Custom Embedded PC Hardware --------------------------------------------------------------------Article: 6616
HTD said... > On Mon, 26 May 1997 20:47:42 GMT, stuart.summerville@practel.com.au > (Stuart Summerville) wrote: > > >Hi all, > > > >I have a 208pin PQFP fpga (0.5mm pitch) on a board. I am having > >problems with pin connections to the board. Attempting to re-heat the > >solder to make a clean connection seems to create problems with > >surrounding pins - it doesn't take much to get a minute solder bridge > >between two pins. ... > Apparantly you can get soldering iron adaptors which have a sphere on > the end which makes the solder pearl thus preventing shorts. I've > never seen one but everybody who has thinks it's the best thing since > sliced white. > > Check Weller and Ersa maby they can help. Anything else is a mess. If you want to get serious about soldering/desoldering fine-pitch surface mount parts, you *really* need to check out *METCAL*. You will live longer, your blood pressure will go down, etc. Once you try a Metcal, you realize once again the value of having the "right tool for the job". -- Bob **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 6617
In <3389f515.2357106@news.on.net>, stuart.summerville@practel.com.au (Stuart Summerville) writes: >Hi all, > >I have a 208pin PQFP fpga (0.5mm pitch) on a board. I am having >problems with pin connections to the board. Attempting to re-heat the >solder to make a clean connection seems to create problems with >surrounding pins - it doesn't take much to get a minute solder bridge >between two pins. > To engineers and technicians concerned with QFP208 soldering problems/techniques - QFP208s and QFP240s are soldered by hand by technicians in the South Bay (SF bay) by a drag technique which some in this thread have described. I'm going to add my two cents by describing our procedures. I believe our procedures need significant improvement, and I'm eager to hear from those who can offer advice toward better techniques, but I can see from this discussion that we have some useful experience to offer here. QFP240s are applied with stencil and reflow on our "G900" PCI interface cards. QFP208s are applied to our "Xmod" FPGA-computing modules by hand in a second stage of assembly after the rest of the card is robot pick-and-placed and reflowed. Inspection is done under 10x or 20x microscope with a fiberoptic ring lamp. Using a "probe" (a flexible scribe, or a needle in an Exacto chuck) every pin on the FPGA is pushed on the side of the foot with about 12-16oz. of pressure. The probe's flexing can be calibrated against a scale. With a little practice the inspector can repeatedly produce 14oz, +-1oz, even with his eyes closed. This probing reveals solder joints which were inadequately heated, usually by the reflow oven, occasionally by hand. The joint may look perfect to visual inspection, with well-sloped fillets all around the foot, but underneath the foot there may be un-fused solder paste, or no solder. With pressure held on the side of the foot for 1-2 seconds, the foot in a defective joint will slowly twist or slide off the land. It does not pop off; it slides as if held by soft fudge. Usually the toe holds best while the heel lets go. I have a design in mind for doing this probing by machine, and I'm told I'm not the first to do it. Motorola is said to have had such a device for in-house use many years ago. Xray would also be revealing, but this equipment is usually beyond the reach of a technician in an engineering dept. We are looking for better joint testing methods. Hand soldering is done here with a Haako 939 station ($360) using an "A1249" tip, which is a cone with a beveled elliptical face as described earlier in this discussion. Our assembly technicians in the South Bay tend to use Metcal stations which are three times more expensive. Both stations exhibit good temperature control with fast recovery times. The first time I saw an assembler apply a QFP208 with the drag technique, my jaw dropped open. It is very fast and it works well if it is done at the right speed and with just the right amount of solder. Some technicians produce consistently high quality results with good heel fillets and no bridging. Other techs are not so consistent. We are choosy: we specify particular techs for this work and it pays off at inspection time in much-reduced re-work. However, it is a skill which can be learned with some practice and some well-focused attention. As mentioned before, liberal fluxing of the territory is mandatory. The liquid flux causes the solder "wetting", and the resulting surface tension of the solder on the joint is very powerful. That and the correct amount of solder are the keys to freedom from solder bridges. The solder we use for this hand work is Kester organic core flux "331" with an .020" diameter. The flux used is a water soluble flux "2331-ZX" from Kester. These products make a big difference. We clean with Citra-Solv and hot water, followed by a distilled water/alcohol rinse, and a hot air dryer. The drag technique is to pull a small solder pool across the toes of the pins from one end of the row to the other, using the elliptical bevel of the tip with its long axis in line with the row. The solder is shared by two to three pins at a time. As the elliptical bevel of the tip slides across the toes, the surface tension of the solder ball pulls most of the solder with the tip, leaving the joint behind with its own solder without a bridge. Each new joint sucks up a little more solder from the pool. Since as many as three joints may be sharing a molten pool as it passes, the solder tends to distribute evenly by virtue of the balance of surface tension as each new joint heats up and "wets" and each old joint pulls free and cools. As you see each pin heat up, a silver sheen will climb up the leg a ways, as the heat, flux, and solder "tin" the pin. When that happens, it is time to keep moving along. A row of 52 pins can be soldered in about 30 seconds by this method. Since three pins are heated simulatneously this gives about 2 seconds dwell on each pin. (30/(52/3)). Tip temperature here is set at 670F/354C. Too much solder will produce bridging in spite of liberal flux. Too little solder will produce inadequate heel fillets. As several here have observed, you may be left with a bridge to clean up on the last pair of pins, if you've added too much solder. Often, the last bridge can be removed by distributing the solder back up the row for a few pins, or by sliding the tip down off the ends of the toes of the last pair of pins, which takes the excess solder with the tip. The standard we use is ANSI/IPC-A-610, rev B, class three. This is documented with excellent color prints and available from The Institute for Interconnecting and Packaging Electronic Circuits (IPC) in Northbrook, Illinois, 1-708-509-9700. We have also reviewed NASA's "NAS 5300.4(3M) workmanship standard for surface mount technology" and adopted only one item from it which is curiously missing from the IPC standard: Figure D-5 specifies that no part of the foot may be more than 0.010" from the land. Otherwise, the NASA standard seemed pretty similar to the ANSI/IPC. The IPC standard document is well worth buying. To see what you are doing, I recommend some magnification, 2x-4x lenses for soldering and 10x-20x microscope for inspection. I see technicians working without magnification, but they are young and experienced, so they have better eyesight than I do, and they know what they are looking for. Reza Ghaffarian at JPL has done, and is doing, long-term extreme thermal cycling of these gull wing joints. He reports that, after 1500 cycles, they are quite robust, but the usual place of failure is across the heel fillets. You can find some reports of his work on the web. I hope this information is of use to technicians new to 20 mil pitch gull wing parts. And I hope someone who knows better ways to do this, especially solder joint inspection/testing, will contribute to this thread and/or email us directly. A testing lab would be appreciated, and probably hired. Rhodes Hileman Director of Manufacturing GigaOperations Corporation Berkeley, California rh@smsys.com www.gigaops.comArticle: 6618
Everyone designing with FPGAs or CPLDs should stay away from altera if
they expect a long product life for their design. I am sure that I am
not the only person who is being burned by the discontinuing production
of the EPX 880 EPX 8160... Altera is completely irresponsible shutting
off production with minimal notice. What are we supposed to do. Redesign
working items in production because Altera refuses to support their
customers.
Think about what life would be like if all the semiconductor companies
acted like Altera. I guess they do give EE job security. But I have
better things to do than migrate designs from one device to another
because of Altera marketing decisions.
Robert Bible
San Diego
Article: 6619Wen-King Su <wen-king@myri.com> wrote in article <5n73dt$c2v@neptune.myri.com>... > In a previous article "Austin Franklin" <darkroo4m@ix.netcom.com> writes: > > ;I just found an interesting PCI bug having to do with the Intel chip sets. > :When a target issues STOP, it is required that the master (Intel chip set) > ;release FRAME in the next cycle. Well, some Intel chip sets don't. What > :this means is a target state machine can spin on it self if it assumes > ;FRAME will be removed (per spec) deterministically! In order to avoid this > :situation, you need to use the raw FRAME right off the PCI bus, which, > ;requres you to only go though one FMAP and make sure the logic is placed > :correctly if you want to make timing. > > Rule 5 on page 42: > > Whenever STOP# is asserted, the master must deassert FRAME# as soon > as IRDY# can be asserted. > > There is no rule that says IRDY# must be asserted in the next cycle, so > FRAME# does not have to be deasserted in the next cycle. So the Intel > chip set is not technically in error. > > However, I do PCI implementation on FPGA as well, and what I find is that > due to the constraints of FPGA, we are forced to operate in a region of > legal PCI behavior space that is rarely visited by the more common ASIC > PCI implementations. Thus we keep running into bugs in systems that > otherwise works well with devices using ASIC PCI implementations. In the bug I found, IRDY was already asserted, and therefore, /FRAME should have been de-asserted in the next cycle following /STOP. It is shown in the PCI spec in the diagram on page 45, Disconnect B that /FRAME must be de-asserted in the next cycle following the assertion of /STOP. It shows an edge sampled /STOP, and /FRAME de-asserted off this edge… Since /IRDY is asserted when /STOP is issued, rule 5 says that too. Go to p. 335 of Solari, PCI Hardware and Software… Section DISCONNECT WITH DATA ACCESSES. Last paragraph says "The assertion of the TRDY# and STOP# signal lines indicates that the present access is the last access of data for this cycle. The Disconnect with data termination request causes the PCI bus master to immediately deassert the FRAME# signal line…" If you go to the next page, it discusses the conditions under which FRAME# may not be immediately de-asserted, and that is only when IRDY# is not asserted yet….which is not the case here. I do not assert TRDY# until IRDY# is asserted, so I will never have to account for IRDY# not being asserted, and it cannot be pulled until at least one data phase has completed (p. 40, #4 states "Once a master has asserted /IRDY, it cannot change /IRDY or /FRAME until the current data phase completes.". The bug I found had nothing to do with this being an FPGA implementation, it had to do with a literal interpretation of the spec, and a bug in the Intel chip sets. This bug has not shown up in other designs (that I know of) because most people just blindly copy the PCI state machines as done in the PCI spec with out understanding in great detail how they function. And, this is the only bug I have ever run into in a PCI implementatin that I have been using for 4 years now. No, I believe this is a bug in the Intel chip sets, not a technicality. Austin Franklin darkroom@ix.netcom.comArticle: 6620
Now that you have beat that to death, got anything to say about the summary judgement? (My originial topic....) That might actually be interesting. ;-) <Blair@QuickLogic.com> wrote: > Let me see, you signed your name and your company and your domain and you > are in the MN phone book and you supplied your email address, yep you > are correct you did supply that information. I just wanted to clarify > your identity without users having to search for your name, company, > domain, email or the MN phone book in order to be aware of that > particular piece of un-obvious information. Now, if that is a personal > attack then you are a pretty sensitive kind of guy. > > Regards, > Ben Blair > Manager Field Applications > QuickLogic Corporation > > The above comments are my own and in no way express the views of > QuickLogic Corporation. (Typical legal disclaimer) :^) > > > In article <19970531210528300253@1cust93.max1.minneapolis2.mn.ms.uu.net>, > john@customer1st.com (John Sievert) wrote: > > > > Nothing hidden here! > > > > Let me see, I signed my name, my company name is in my domain name, both > > my name and my company's name are in the phone book, and the POP I > > connected from is listed right in the email. What's wrong with being > > the sales engineer here? Aren't you a QL employee? Aren't we all > > involved in this industry? > > > > The issue isn't who works for who, but what's in the summary judgement - > > and therefore, who owns what. That isn't mud slinging, its a fact and > > now a matter of public record. How is that mud slinging? What's your > > problem? > > > > If you've got something to say on this case, I'd be interested in > > hearing it. This court case is complex, but interesting and worthy of > > discussion. If you want to make personal attacks, I guess I'd consider > > that a waste of time. But, if that's the image you want to project for > > you and your company, I guess that's your business. > > > > Regards > > John Sievert > > Customer 1st, Inc. > > > > <Blair@QuickLogic.com> wrote: > > > > > In article <19970526224329123272@cust4.max1.minneapolis.mn.ms.uu.net>, > > > john@customer1st.com (John Sievert) wrote: > > > > > > > > Technology, which it appears, probably came from Actel (per summary > > > > judgement against QuickLogic on patent infringement.). > > > > > > > > <kevintsmith@compuserve.com> wrote: > > > > > > > > > In this case, it's not marketing hype, just superior > > > > > technology. > > > > > > > > -- > > > > Regards, > > > > John Sievert > > > > > > Aren't you the Actel Manufacturers Rep in the MN area? > > > > > > It would behoove you to not sling mud and try to hide your identity. > > > > > > Regards, > > > Ben Blair > > > Manager Field Applications > > > QuickLogic Corporation > > > > > > -------------------==== Posted via Deja News ====----------------------- > > > http://www.dejanews.com/ Search, Read, Post to Usenet > > > > -- > > Regards, > > John Sievert > > -------------------==== Posted via Deja News ====----------------------- > http://www.dejanews.com/ Search, Read, Post to Usenet -- Regards, John SievertArticle: 6621
Does anybody know how to get Designer Series 3.1 working under NT4.0? Perhaps too much to ask, what about WorkView Office 7.2 under NT 4.0? Thanks, Hans TiggelerArticle: 6622
alexander@eecs.wsu.edu wrote: : Do people agree that there's a difference between reconfigurable : computing and FPGAs? Do these topics warrent separate discussion : spaces? (Comments?) I think that the two topics overlap, but neither is a subset of the other. The overlap is clear, because much reconfigurable computing work is done using e.g. Xilinx 4000 series devices, and so understanding the devices and the tools needed to program them is part of the reconfigurable computing toolkit. An example of reconfigurable computing not overlapping with FPGAs is UCB's GARP reconfigurable computing architecture, which could not really be described as an FPGA because it's optimised for implementing arithmetic and other multi-bit operations, rather than gates. So I support the idea of a separate group for reconfigurable computing in principle, though I don't think the volume of traffic in comp.arch.fpga at the moment is high enough to make it urgent to split the group. The multiple uses of the term "reconfigurable" in the computing world is a pain in general. It would be useful if somebody in the FPGA-based computing community came up with a different term for that approach. But failing that, comp.arch.reconfig(urable) seems to be a good name for the new group. As to whether the pure FPGA group should then be pushed out of comp.arch as having nothing to do with computing, I don't have a strong opinion. -- Alan Marshall *--------------------------------*---------------------------------------* | | Alan Marshall, | | ######## / ######### | Hewlett Packard Laboratories, | | ####### / ####### | Filton Road, Stoke Gifford, | | ###### /__ ___ ###### | Bristol BS12 6QZ UK | | ##### / / / / ##### | | | ##### / / /__/ ##### | Email: adm@hplb.hpl.hp.com | | ###### / ###### | HPDesk: Alan MARSHALL / HPC600 | | ####### / ####### | Phone: +44 (117) 922 8207 | | ######## / ######### | FAX: +44 (117) 922 8925 | | | Telnet: 312-8207 | *--------------------------------*---------------------------------------*Article: 6623
Hans Tiggeler wrote: > > Does anybody know how to get Designer Series 3.1 working under NT4.0? Perhaps > too much to ask, what about WorkView Office 7.2 under NT 4.0? > > Thanks, > Hans Tiggeler Hans, Actel tech support has a document on how to get Designer 3.1 working under NT 4.0. The upshot is: 1. Set the system variables ALSDIR, OS_ROOTDIR to C:\ACTEL 2. Set the system variable ODI_SERVER_DIR to C:\TEMP 3. Set the system variable to OS_LOCAL_HOST=LOCAL_HOST 4. Include C:\ACTEL\BIN in your path. 5. If you NT machine does not have a network installed, set OS_AUTH=12 6. From a DOS shell run: start osserver -con -i and answer yes to initializing the transaction log file. 7. Create an icon in your startup menu that runs: c:\actel\bin\osserver.exe -con This should solve the Actel problem. Workview Office 7.2 runs on NT 4.0 out of the box. If you have any troubles, see our web site for known NT 4.0 interaction issues since the OS wasn't released when WVO 7.2 was released. Regards, Adam J. Elbirt Senior Programmable Solutions Engineer Viewlogic Systems, Inc.Article: 6624
I have been studing the datasheet og the Altera flex10k and have some questions regarding global nets / clocknets. The chip have 6 dedicated input pins connected to fast I/O-blocks that can be connected to 4 global nets. The I/O-blocks are connected through a peripherial net with 12 lines the can be used as clock, clear or output enable. There are also 2 clock nets thar connect the I/O-blocks. Are the 2 clock nets in the I/O-blocs 2 of the 4 global nets? If I want to connect a internally generated clock-signal to one of the global nets, do I have to go through a I/O-block? I have also not been able to find information regarding konfiguration through JTAG pins. I hope someone have got a clearer understanding of the global nets and the pheripheral net (with the 2 clocknets) of the I/O-blocks in the flex10k. Dag Magne
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