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Hi, One thing to consider with this code is that the process is only triggered by W changing, but it actually depends on both W and nz. This is because assigning to a signal does not take effect immediately (unlike a variable) Assigning a signal to itself should only be done when you wish to infer a register, not to create combinatorial feedback loops. XST is probably crashing as this code is not what it would normally expect to see. What would work is declaring a variable in the 'cond' process to use in the loop. Once the loop is complete, then assign the variable to the signal. This might cause too long a combinatorial path though.. Try simulating the code first to see how it behaves, but bear in mind that synthesisable code is a subset of simulatable code. cheers, Chris brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0302110800.3b7cb342@posting.google.com>... > Hi all, > > I have a small piece of code that the XST synthesis tool in Xilinx ISE > 5.1 Webpack chokes on: > > signal W: std_logic_vector(n+1 downto 0); -- generic n=15 > signal nz: std_logic; > ... > cond: process(W) begin > nz <= '0'; > for i in W'range loop > nz <= nz or W(i); > end loop; > end process cond; > > FATAL_ERROR:Xst:Portability/export/Port_Main.h:126:1.13 - This > application has discovered an exceptional condition from which it > cannot recover. > > Meanwhile, this version of it works: > > nz <= W(16) or W(15) or W(14) or W(13) > or W(12) or W(11) or W(10) or W(9) > or W(8) or W(7) or W(6) or W(5) > or W(4) or W(3) or W(2) or W(1) or W(0); > > Does anyone know why this happens?Article: 52501
> > > > "Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message > > news:5c4d983.0302081113.48392c92@posting.google.com... > > > Is there anything equivalent to JBits for Altera devices? I'm dearly > > hoping so ... > > > > > "Eric Pearson" <epearson@lsil.com> wrote in message > news:b28bov$6od$1@news.lsil.com... > > Hi Pete... > > > > How does Jbits help one get better Altera designs? > > > > Eric Pearson > > "Steve Casselman" <sc@vcc.com> wrote in message news:<Jpa2a.482$UL6.53376127@newssvr14.news.prodigy.com>... > There are all sorts of reasons to do this. Just go and look up all the paper > written about JBits. Most of it has to do with using the configuration > infrastructure to change and update a small part of a devices configuration Thanks for the summary. There is alot of info when you just google 'jbits'. > often at runtime. If you think about it there are a lot of resources that go > into configuring these devices and it is a waste to only use that once. I agree that being able to really take advantage of virtual hardware one needs to keep the configuration port busy, however I'd like to discuss 'how' further.... I disagree that partial reconfigurability is the immediate answer. To use proven tool chains, it would be much more pratical if efforts (Altera+) to make the configuration infrastructure more useful were focused on shortening reconfiguration times. A sub mSec full chip reconfiguration time would go a long ways towards virtual hardware. Imagine the applications available with a mere 90% temporal utilization. > one time Altera and Xilinx had the same market cap (number of shares times > share price) and that changed the day EETimes ran the headline "Xilinx > believes in reconfigurable computing and Altera thinks it is a red herring." > It told investors and engineers that Xilinx believed in a future and Altera > did not. Algorithmic programming of fpga's for wild-a$$ genetic search machines is a great application, but it seems a ways off before its ready for the masses of programmers writing software that manipulates hardware in realtime. > JBits gives users a direct programming model, something that Altera does not > have. In my opinion if Altera wants to capture the imagination of the top > engineers in the world they should design a part starting with a bit level > programming model that makes sense and then make that public. It would be > great if there were a part that I could give a partial bitstream that would > just program the lookup tables and not have to include any routing bits. Yes, being able to program lookup tables saves space when you need to cram a bit more in, but that level of reconfiguration is more often a part of the real design rather than a side effect. > > We are coming into the age where 10's of thousands of programmers are going > to start using FPGA's. Access to, and knowledge of, the bitstream will allow > companies to be successful quicker and add value beyond what HDLs and > standard programming models of today can offer. I think the biggest > challenge that faces FPGA companies is not more gates or bigger ram or > faster embedded processors those things all come with more transistors. But > rather how to design a part that starts with a straight forward, well > documented, bit level programming model that will allow programmer to write > software that can manipulate the hardware during runtime. > > Steve I can see you vision, but with the Xilinx 6000 demise, (too early to market?) as an example, potential backers of open bitstream fpga architectures should think long and hard. There is perceived value in having your hardware designs distributed in a traditional confusticated form, produced and verified by commodity toolchains (sim,syn,par, and timing). Respectfully,... Eric PearsonArticle: 52502
"Welcome to the machine............" In this simple two part experiment you will demonstrate instantaneous propagation of electric field gradient change. Part A demonstrates instantaneous signal propagation over 2m long copper wire. Part B demonstrates signal propagation speeds 7 to 15 times faster than speed of light using ordinary 50Ohm coax cable! You need..... One 2 m long pierce of bare copper wire 1.5 or 2mm diameter. One 2 m long pierce of 50Ohm coax cable. One 50Ohm 0.5W resistor. HP 33120A waveform generator with frequency set at 1MHz sin waveform 10Vp-p. Oscilloscope HP 54602A or similar one. Use 10X high impedance scope probes (standart). Two peace of nylon string. Part A............................................................. Stretch horizontally the 2m copper wire across your room about 1m above the floor using two pierce of nylon stings as an insulators. Connect Oscilloscope HP 54602A channel 1 to one end of the 2m copper Connect 1MHz sin waveform 10Vp-p signal cable to the same end that channel 1 probe connects. Connect the ground lead of channel 1 scope probe with the ground lead of 1MHz sin waveform 10Vp-p cable. Set the scope trigger source on channel 1. Connect channel 2 probe to the other end of 2m copper wire using the tip only, the ground tip should hang loose. The scopes time base should be set to max speed which is 2ns/div (large grid and 100ps small) for the HP 54602A scope. Also stretch the vertical signals on bough channels using the gain function. You should see no delay at all at any point on the 2m wire. Switch the hookup position of the channel 2 probe to verify any delay. Remember not to touch the copper wire with you hands or any metal objects. Einstein claimed the electric field propagates with speed of light which is about 1ns per 30 cm of the copper wire length. Your calculated delay should be about 6ns. I did not see any delay at all! Part B............................................................. Connect 50Ohm resistor to one and of coax (one end of the resistor to coax core and the other to coax shield) Connect Oscilloscope HP 54602A channel 1 to the other end of the 2m coax cable ( hot tip to coax core and ground tip to coax shield) Connect 1MHz sin waveform 10Vp-p signal cable to the same end that channel 1 probe connects ( hot tip to coax core and ground tip to coax shield) Connect Oscilloscope HP 54602A channel 2 to the end that has 50 Ohm resistor termination. ( hot tip to coax core and ground tip to coax shield) The scopes time base should be set to max speed which is 2ns/div (large grid and 100ps small) for the HP 54602A scope. Also stretch the vertical signals on bough channels using the gain function. You should observe about 10 ns delay between the two 1MHz sin waveforms. Now disconnect the 50Ohm resistor and observe the delay. There delay now should be from 400ps to 800ps dependent of quality of coax that you have. This correspond to the signal propagation speed 7 to 15 times faster than speed of light! According to Einstein it is not possible to ecocide the speed of light. But I was able to do it in such a simple way! Sincerely, Mathew Orman ps. Share this experiments with your colleagues and university professors or any one that it interesting in the science of true physical reality!Article: 52503
>Some would argue that if designs are properly synchronous and >the static timing report is OK then post P+R simulation is >not necessary. You forgot the part about "Tools are bug free". It's just CPU cycles rather that man-power. Seems like a good investment. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 52504
Been a long time microcontroller man, but I'd really like to start getting into fpga's. Can anyone recommend good starting places? Good books? Thanks MattArticle: 52505
Hi, To implement the ROMs you could also try instantiating the LUTs manually and setting their INIT generic to the content of the ROM. cheers, Chris "Norbert Hermann Pramstaller - nhp" <prammi@sbox.tugraz.at> wrote in message news:<3e496626$0$24278$3b214f66@aconews.univie.ac.at>... > Hi all, > > > > I work with the Spartan II and I need a small RAM (16x8). Due to the fact > that one LUT provides a 16x1 synchronous RAM I only need 8 LUTs (2 CLBs) > for the 16x8 RAM. By using this distributed LUT RAM I have all on-chip Block > RAMs unused and that's what I want. But now my question: "Do other FPGAs, > e.g. Altera, also provide this kind of LUT based RAM or is this feature > Xilinx specific? > > > > Next I also need a ROM and as before I would like to implement it as a > distributed ROM instead of using a Block RAM. During synthesis (ISE Webpack) > XST detects the Rom but during optimization the ROM is replaced by Logic > (MUXs). This depends on which values I define within the ROM. How can I turn > off the optimisation for a single component in my VHDL code? > > > > Has somebody experience with Dual Port RAMs? I heard that concurrent reading > and writing from/to the same address is problematic (not for simulation but > for implementation)? > > > > Thx > > > > -NorbertArticle: 52506
Matthew Fowle wrote: > Been a long time microcontroller man, but I'd really like to start > getting into fpga's. Can anyone recommend good starting places? Good > books? Better to read data books and app.notes on smallish popular chips such as spartan2, acex1k, 22v10 varieties etc, then find free tools to download and try something out. You'll need books for learning HDL such as VHDL/verilog. If you already can program s/w, it'll take at least 3months to learn decent HDL implementation and know what you're doing, and have your tools running right.Article: 52507
Hi Mathew, if that's a serious challenge, reproduce it with a single pulse generator, and come back here with your results. if it's a joke (I hope so), I'll show you my favorite one (I've received this from a mailing list, and I really like it :-)) Bernhard This bloke is working on the buses and collecting tickets. He rings the bell for the driver to set off when there's a woman half getting on the bus. The driver sets off, the woman falls from the bus and is killed. At the trial the bloke is sent down for murder and seeing as it's Texas he's sent to the electric chair. On the day of his execution he's sat in the chair and the executioner grants him a final wish. "Well" says the man, "is that your packed lunch over there?" "Yes" answers the executioner. "Can I have that green banana?" The executioner gives the man his green banana and waits till he's eaten it. When the man's finished, the executioner flips the switch sending hundreds of thousands of volts through the man. When the smoke clears the man is still alive. The executioner can't believe it. "Can I go ?" the man asks. "I suppose so" says the executioner, "that's never happened before." The man leaves and eventually gets his job back on the buses selling tickets. Again he rings the bell for the driver to go when people are still getting on. A man falls under the wheels and is killed. The bloke is sent down for murder again and sent to the electric chair. The executioner is determined to do it right this time so rigs the chair up to the electric supply for the whole of Texas. The bloke is again sat in the chair. "What is your final wish ?" asks the executioner. "Can I have that green banana in your packed lunch ?" says the condemned man. The executioner sighs and reluctantly gives up his banana. The bloke eats the banana all up and the executioner flips the switch. Millions of volts course through the chair blacking out Texas. When the smoke clears the man is still sat there smiling in the chair. The executioner can't believe it and lets the man go. Well, would you believe, the bloke gets his job back on the buses. Once again he rings the bell whilst passengers are still getting on, this time killing three of them. He is sent to the electric chair again. The executioner rigs up all the worlds electricity to the chair, determined to get his man this time. The man sits down in the chair smiling. "What's your final wish ?" asks the executioner. "Well" says the man, "Can I have that green banana out of your packed lunch." The executioner hands over his banana and the man eats it all, skin included. The executioner pulls the handle and a zillion million trillion volts go through the chair. When the smoke rises the man is still sat there alive without even a burn mark. "I give up" says the executioner, "I don't understand how you can still be alive after all that?". He stroked his chin. "It's something to do with that green banana isn't it?" he asked. (are you ready for this ... . . . . . . "Nahh" said the bloke, "I'm just a really bad conductor." +==================================================================+ Phil Daly, NOAO/AURA, 950 N. Cherry Avenue, Tucson AZ 85719, U S A -- before sending to the above email-address: replace deadspam.com by foerstergroup.deArticle: 52508
Valeri, the instruction and data caches can be loaded with program and data without the use of any BRAM or external memory if (and only if) you are configuring through JTAG. In particular, you can build a system in which you don't need to have any other memory to execute the program from or store data in, i.e. your program can directly run out of the instruction cache and stack, bss, and data is stored in the data cache. Possible configuration solutions are System ACE CF or any other JTAG based configuration solution as described in XAPP058. How is it done? When you write your code you will have to include information in the linker script where the instruction and data cache are mapped in the memory space. You don't need to have physical memory in these locations. When you use GDB to download the code, or when you generate a SVF or ACE file with the tools included in V2PDK (Virtex-II Pro developer's kit), GDB or the tools will recognize the mapping of the caches and generate JTAG sequences that loads the instruction and data cache. People who own V2PDK can have a look at source/sw/mapfiles/mapfile5 and source/sw/apps/xrom for an example of a linker script and a program that is compiled and linked so that when loaded it directly runs out of cache. Currently, there is no way to include the cache contents in the bitstream itself, i.e. there is no way to load the caches if you configure with slave/master serial or slave/master selectmap. This all sounds more confusing than it is. For the user it is a transparent process. Map the code in the right location and everything else will happen in the background. - Peter Valeri Serebrianski wrote: > In Virtex-II Pro datasheet stated that PowerPC processor has 16 KByte > of instruction and 16 KByte of data cache onboard. For my application > that amount of memory is more than enough (processor speed is far more > valuable). > Is this possible to store both the program and data tables solely in > those caches without any use of Virtex-II Pro SelectRAM or external > RAM? It assumes that initial content for both caches will be stored in > main Virtex-II Pro configuration RAM and will be loaded at startup. > > Valeri Serebrianski.Article: 52509
Aurash, Does Xilinx have a TCP/IP stack available for the Microblaze or did you use a third party solution? Thanks, Dave Aurash Lazarut wrote: > Terry, > > You can use EDK ( embedded dev. kit) and spartan2e (xc2s400e or > xc2s600e) and build a small system around MicroBlaze > with Ethernet 10/100 MAC and use BRAM for the SW (tcp/ip stack) I've > used this "receipe" and it works fine. > > Aurash > > "Theron Hicks (Terry)" wrote: > > > > Hi, > > I am looking at design upgrade of an existing instrumentation > > project. Currently the design talks over a high speed bus to a rather > > expensive (~$1600 US) parrallel digital input board. The data rate > > would be on the order of 50M bits per second not including any > > overhead. I do not think I want to go to an all FPGA based solution. > > Currently the FPGA in the system is the smallest Spartan2e series > > device. By the way, quantities are very small, on the order of less > > than 50 pieces per year. > > > > So here are my questions... > > > > 1. Does anyone happen to know what the USB2 or firewire is rated for > > in terms of the longest cable length? I had thought USB2 was limited to > > about 2 meters but I have seen USB cables about 5 meters long recently. > > A longer length interconnect would appear to be desireable. I know that > > ethernet is good for several hundred meters. That would be far beyond > > my needs. > > > > 2. Has anyone had any experience with either USB2 or 100mB or > > firewire as an interconnect to an FPGA based design? > > > > 3. Do you happen to have any recommendations as to a possible > > off-the-shelf solution (either a small board or a 1 or two chip > > solution, ideally something with a demo board available)? > > > > Thanks, > > Theron Hicks > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324Article: 52510
>> Been a long time microcontroller man, but I'd really like to start >> getting into fpga's. Can anyone recommend good starting places? Good >> books? How much hardware background do you have? If not much, then try to find a friend who does know hardware to give you a quick lesson. You need to understand the timing limitations - what setup, hold, and prop times mean. And about clock skew. You can probably do it in 10-30 minutes at a white board. Work out a few examples, like a counter or a state machine. Figure out how fast they will run. (Look up the numbers for LS or HC chips.) >Better to read data books and app.notes on smallish popular chips >such as spartan2, acex1k, 22v10 varieties etc, then find free tools >to download and try something out. You'll need books for learning >HDL such as VHDL/verilog. If you already can program s/w, it'll take >at least 3months to learn decent HDL implementation and know what >you're doing, and have your tools running right. Data sheets are good. Modern FPGAs are very complicated. 22V10 or smaller CPLD might be a better place to start. The older Xilinx data books (when they were actually paper books) had a good intro section that explained some of the economics. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 52511
> You should be able to use the same testbench in Modelsim to > test RTL and post P+R designs. The results should be > identical. The post P+R simulations are an Well, although it's principally correct, but basically it's not always the case! In simulation a RTL design, you don't talk about time and timing, but you just talk about clock events. Everything is propagated, computed, generated in just some few simulation deltas. In post P+R simulation, now, you face the time, timing and absolute times. There are cases that you have to modify the testbench to conform to the "valid" setup/hold times just as an example. Also, you may need to add much more to the automatic verifications like to check for jitters and calculate statistics on setup/hold times and more... Also you may as well need to write different stimulus as now the should mimic real-world signals with specific timings (like simulation the transactions of a bus). All this depends on the problems in hand; but the moral of the story is that the worlds of RTL and post P+R can be far and different worlds... Best Regards ArashArticle: 52512
Christian Plessl <plessl@tik.ee.ethz.ch> wrote in message news:<3e47e49e@pfaff.ethz.ch>... > Nicholas C. Weaver wrote: > > > In article <b235lh$n01$03$1@news.t-online.com>, > > Florian-Wolfgang Stock <f.stock@tu-bs.de> wrote: > >>S. Trimberger, D. Carberry, A. Johnson, J. Wong: A time-multiplexed > >>FPGA. In "Proceedings of IEEE Workshop on FPGAs for Custom Computing > >>Machines" (April 1997), pp. 22-28 > > > > This one, a Xilinx design for a multicontext XC4000, was basically > > killed as a potential product because context switching draws a LOT of > > power, especially in all the interconnect bits, and they envisionsed > > multicontext being used to virtualize larger circuits. > > Do you have any idea, why some multi-context devices are seem to consume a > lot of power when context switching? > > Any idea how the power dissipation related to context switching relates to > the power consumed by a 'typical' user application? I understand that a > context switch can potentially cause a lot of elements to switch at once, > but also a user application might generate quit a lot of signal toggling. The problem lies in changing the interconnect configuration during a "context switch". To fully understand the details you need to look at how those switches are implemented: typically some combination of pass-gates and buffers. The characteristics are typically so, that the actual signal propagation is quick (e.g. low resistance pass-gates and very quick buffers), however the turn on and off time are relatively slow. So what happens when you change the configuration ? Multiple pass gates can be closed at the same time and drive different logic values on the bus, creating a short. Count the nuber of interconnects and possible shorts, even in the smallest FPGA, and it becomes clear why you can cook coffee on them if constantly context switching. (I suspect this is the same reason why the "power-on-current" requirement is so high.) Of course the idea of context switching programmable logic is not new, I have worked on a proprietary "processor" that had 64 "time slices". This was basically an FPGA type of structure with its inputs and outputs going through a multilevel register file as well as to an IO ring. It was meant to be used as the hart in a Hardware Accelerator, and burned about 20 Watts each. (This was in 1995) Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV ----- > Regrads, > ChristianArticle: 52513
Hi,
is it possible to floorplan design written in verilog/Mentor HDL
Designer? I use Leonardo for synthesis and Xilinx ISE 4.2 for
Transl/Map/P&R. My problem is that I have to add new functionality to
existing design (Spatan2-150 ) and I need to make existing design run
faster. The design takes now 80% of FPGA. I know that I can assign RLOCs to
instantiated components like LUTs, FFs, IOBs ... but how can I do this in
Verilog? Is there any way to tell P&R tools that: "I want this 64x16 RAM to
be placed here and this counter there." ? I don't like the work that
automatical PAR does. And I noticed that it does different place each time i
PAR the design. I need to have control of PAR proces.
Can anybody help?
All answers are greatly appreciated.
Peter
Article: 52514David A Hand wrote: > > Aurash, > > Does Xilinx have a TCP/IP stack available for the Microblaze or did you use a > third party solution? > > Thanks, > > Dave > > Aurash Lazarut wrote: > > > Terry, > > > > You can use EDK ( embedded dev. kit) and spartan2e (xc2s400e or > > xc2s600e) and build a small system around MicroBlaze > > with Ethernet 10/100 MAC and use BRAM for the SW (tcp/ip stack) I've > > used this "receipe" and it works fine. > > > > Aurash > > > > "Theron Hicks (Terry)" wrote: > > > > > > Hi, > > > I am looking at design upgrade of an existing instrumentation > > > project. Currently the design talks over a high speed bus to a rather > > > expensive (~$1600 US) parrallel digital input board. The data rate In EDK (embedded dev. kit) thre is library XilNet - with ethernet, + TCP/IP (and UDP/IP of course) Aurash > > > would be on the order of 50M bits per second not including any > > > overhead. I do not think I want to go to an all FPGA based solution. > > > Currently the FPGA in the system is the smallest Spartan2e series > > > device. By the way, quantities are very small, on the order of less > > > than 50 pieces per year. > > > > > > So here are my questions... > > > > > > 1. Does anyone happen to know what the USB2 or firewire is rated for > > > in terms of the longest cable length? I had thought USB2 was limited to > > > about 2 meters but I have seen USB cables about 5 meters long recently. > > > A longer length interconnect would appear to be desireable. I know that > > > ethernet is good for several hundred meters. That would be far beyond > > > my needs. > > > > > > 2. Has anyone had any experience with either USB2 or 100mB or > > > firewire as an interconnect to an FPGA based design? > > > > > > 3. Do you happen to have any recommendations as to a possible > > > off-the-shelf solution (either a small board or a 1 or two chip > > > solution, ideally something with a demo board available)? > > > > > > Thanks, > > > Theron Hicks > > > > -- > > __ > > / /\/\ Aurelian Lazarut > > \ \ / System Verification Engineer > > / / \ Xilinx Ireland > > \_\/\/ > > > > phone: 353 01 4032639 > > fax: 353 01 4640324 -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 52515
John,
The issue only arises when the write data is different than the current data and
you are simultaneously reading the same location. In the case where you are
writing garbage to your next write location until you have valid data, you
presumably have already finished with any valid reads of that location, and you
don't do any further valid reads at that location until after the write is
completed.
If you are holding the last write data and last write address going into the
BRAM, then the only real conflict with the read is on the first cycle that data
is getting written, and that is no different than when you use the enables.
John_H wrote:
> This is what I was referring to.
>
> For verilog type folks,
>
> always @(posedge clk) // slower write performance due to .WE
> begin
> reg_data_placed[15:0] <= in_data;
> reg_addr_placed[7:0] <= in_addr;
> write_ctrl <= in_data_valid; // pipeline matching
> if( write_ctrl ) mem[reg_addr_placed] <= reg_data_placed;
> end
>
> always @(posedge clk) // faster write performance with "effective" write
> enable
> begin
> if( in_data_valid ) reg_data_placed[15:0] <= in_data;
> if( in_data_valid ) reg_addr_placed[7:0] <= in_addr;
> mem[reg_addr_placed] <= reg_data_placed;
> end
>
> No garbage location required. The concern I had was that the data bypass
> ciruitry might mess things up.
> From one port to the other, it probably doesn't care what the address on
> port A is when reading from port B as long as the clock to clock constraints
> are met. If the address "goes away" on the other port, as long as the the
> old address is on the old clock and the new address is on the new clock and
> the old data stays the same, the old data will be read. I don't know if
> this is guaranteed. A garbage location would eliminate the match of a read
> address to the last-written write address many cycles before but I can get
> better utilization if the bypass works.
>
> I certainly won't try to read data that's freshly changing on the write port
> but I'd continue to write at the same port over and over even when reading
> the last value written (e.g. an empty FIFO condition). I won't have an
> address match on the read and write when the value is first written, but I
> will afterwards and it's the behavior of the BlockRAM at this tail end I'm
> concerned about.
>
> "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message
> news:3e48c33f$0$29909$fa0fcedb@lovejoy.zen.co.uk...
> > Ray Andraka <ray@andraka.com> wrote in message
> > news:3E486125.AC4E29E3@andraka.com...
> > > That works just fine as long as you don't mind overwriting the data at
> the
> > > current address with garbage. In FIFOs and other similar buffers this
> is
> > rarely
> > > a problem. In random access buffers, you might need valid data present
> at
> > all
> > > normal write locations at all times, in which case you will need to
> either
> > use
> > > the enable ( :-( ) or you'll have to substitute an address where it is
> > > acceptable to push the garbage.
> >
> > Ray,
> >
> > You could also push the enabling back one level to a set of registers
> > which would store the last valid address/data combination.
> >
> >
> > Nial.
> >
> > ------------------------------------------------
> > Nial Stewart Developments Ltd
> > FPGA and High Speed Digital Design
> > www.nialstewartdevelopments.co.uk
> >
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52516
This is only true if the write data is different than the current
contents.
RISC taker wrote:
> Well,
>
> there IS a hazard case in which it WILL go wrong:
>
> if one port is writing to an address, and the other port is reading
> from that same address at the same clock cycle (or shortly after), the
> reading port WILL read garbage.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52517
Depends on your hardware background. FPGA design _IS_ digital hardware
design, not programming. if you don't have a hardware background, the first
step is learn about digital design. There are important concepts to do with
timing, asynchronous operation, concurrency, etc that are quite foriegn to
the software world. You can get lucky and get something that works (at
least most of the time) without a firm basis, but you are alse very likely
to trip over one of these without even knowing it. Most of these are not
covered or are covered fairly far into an entry level digital logic design
course, so you really need to go a little deeper than introductory level
learning.
Russell wrote:
> Matthew Fowle wrote:
> > Been a long time microcontroller man, but I'd really like to start
> > getting into fpga's. Can anyone recommend good starting places? Good
> > books?
>
> Better to read data books and app.notes on smallish popular chips
> such as spartan2, acex1k, 22v10 varieties etc, then find free tools
> to download and try something out. You'll need books for learning
> HDL such as VHDL/verilog. If you already can program s/w, it'll take
> at least 3months to learn decent HDL implementation and know what
> you're doing, and have your tools running right.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52518On Tue, 11 Feb 2003 00:21:29 GMT, "John_H" <johnhandwork@mail.com> wrote: >I'm wondering: would there be any problems if - rather than using a trash >location - the last address and data were just kept? The .CEs on the CLB >registers that feed the BlockRAM are easily manipulated. Would I give >myself any problems? If the same data is written to a location (and the contents have not been changed from the other port), then the location contents do not change. >My gut says it's fine but I worry that the logic that bypasses the portA .D >input to the portB .Q output when the two port addresses match might get >confused either by the nature of the bypass logic or - more probable - if >the load address and data change away from the common value on the high >speed write port around the clock edge of the lower speed read port. What bypass logic are you talking about? in your HDL or in the BRAM itself? There is no such path in the BRAM, and there is no address match logic in the BRAM either. The two ports are totally independent, and only share the storage array. If a location is being written with the same data as it already has, a read on the other port will get the current contents regardless of the relationship of the two clocks. >Any thoughts or experiences would be appreciated. >- John_H Philip Freidin Philip Freidin FliptronicsArticle: 52519
On 11 Feb 2003 05:04:35 -0800, RISC_taker@alpenjodel.de (RISC taker) wrote: >Well, > >there IS a hazard case in which it WILL go wrong: > >if one port is writing to an address, and the other port is reading >from that same address at the same clock cycle (or shortly after), the >reading port WILL read garbage. Only if the contents is changing from one value to another. >If you can guarantee that this never happens in your design, you have >no problem :) I've designed a similar thing which is pipelined and you >never know... > >Solutions: >- this applies to Spartan-II. If you use Virtex-II instead, you can >configure the RAM to "read first" mode. That way, you'll read the old >data for one clock cycle, later the new data. Better than garbage :) Woaaaa. The "read first" only relates to reads on the same port as the write is occuring on. The other port is totally independent except for the storage array. (but see below for special case of both ports using the same clock) If the contents of a location are not changing (writing the same data), a read on the other port will get the right value regardless of timing between the two port clocks. If the data is being written by one port to a new value, and the other port does a read, then you may/will have problems. If the two clocks are the same, then what you read on the read port will depend on the "read first" control of the write port (because this mode delays write while doing the read). Otherwise you will get the new data. If the two clocks are different, all bets are off. Old data, new data, some bits old/new, bits in transition, etc. Indicative of bad design if you depend on this to somehow "work". >But Spartan-II RAMs don't support that feature. >- you could build a logic that catches this hazard case and >multiplexes the output. I once did this. It works fine, but in your >case, having a dummy location for dump writing would probably be >faster and require less logic. This only works if both ports use the same clock. >Regards, >Dennis Philip Philip Freidin FliptronicsArticle: 52520
> Yes, I know what you mean and although you can move the label around, the > pin stays on the side. Annoying. ......and what a daft way to design it :-) > It's interesting that you use VHDL and graphical entry. This is the way I do > designs as I like a graphical top level although I think it's not the done > thing anymore (for some reason). I think it makes it easier to see the structure of the design even though its more time consuming, and in any case my project manager wouldn't be happy without a picture. > I'm glad your Quartus hangs up now and again as well. It's obviously not my > fault! Maybe later versions will improve its reliability. > > I'm having problems with simulation. Which simulator do you use? Either Quartus for little bits and pieces or ModelSim for verifying larger bits of code. RArticle: 52521
Rudy, It is sure amusing to read all of the conjectures..... Now that we are designing our 12th generation FPGA, we are able to control current quite well, thank you. Note: that is 12 successful FPGA designs. You get pretty good at something when you work on it for that long (and do some experimentation along the way). Virtex II and Virtex II Pro have no current surge on power ON, as we found what causes that, and addressed it. As for multi-context FPGAs, they were simply killed by FPGAs with million+ "gates" (who needs to switch?). As well, with partial reconfiguration in Virtex II and II Pro, you can at any time reconfigure parts and pieces (with no current issue). Austin Rudolf Usselmann wrote: > Christian Plessl <plessl@tik.ee.ethz.ch> wrote in message news:<3e47e49e@pfaff.ethz.ch>... > > Nicholas C. Weaver wrote: > > > > > In article <b235lh$n01$03$1@news.t-online.com>, > > > Florian-Wolfgang Stock <f.stock@tu-bs.de> wrote: > > >>S. Trimberger, D. Carberry, A. Johnson, J. Wong: A time-multiplexed > > >>FPGA. In "Proceedings of IEEE Workshop on FPGAs for Custom Computing > > >>Machines" (April 1997), pp. 22-28 > > > > > > This one, a Xilinx design for a multicontext XC4000, was basically > > > killed as a potential product because context switching draws a LOT of > > > power, especially in all the interconnect bits, and they envisionsed > > > multicontext being used to virtualize larger circuits. > > > > Do you have any idea, why some multi-context devices are seem to consume a > > lot of power when context switching? > > > > Any idea how the power dissipation related to context switching relates to > > the power consumed by a 'typical' user application? I understand that a > > context switch can potentially cause a lot of elements to switch at once, > > but also a user application might generate quit a lot of signal toggling. > > The problem lies in changing the interconnect configuration during > a "context switch". To fully understand the details you need to look > at how those switches are implemented: typically some combination of > pass-gates and buffers. The characteristics are typically so, that > the actual signal propagation is quick (e.g. low resistance pass-gates > and very quick buffers), however the turn on and off time are relatively > slow. So what happens when you change the configuration ? Multiple pass > gates can be closed at the same time and drive different logic values > on the bus, creating a short. Count the nuber of interconnects and > possible shorts, even in the smallest FPGA, and it becomes clear why > you can cook coffee on them if constantly context switching. (I suspect > this is the same reason why the "power-on-current" requirement is so > high.) > > Of course the idea of context switching programmable logic is not new, > I have worked on a proprietary "processor" that had 64 "time slices". > This was basically an FPGA type of structure with its inputs and outputs > going through a multilevel register file as well as to an IO ring. It > was meant to be used as the hart in a Hardware Accelerator, and burned > about 20 Watts each. (This was in 1995) > > Regards, > rudi > ------------------------------------------------ > www.asics.ws - Solutions for your ASIC needs - > FREE IP Cores --> http://www.asics.ws/ <--- > ----- ALL SPAM forwarded to: UCE@FTC.GOV ----- > > > Regrads, > > ChristianArticle: 52522
I take it that you have already tried to export your vwf files as a vht file and used the vht file as the testbench in modelsim to get you started?Article: 52523
hello everybody, On the software maxplus+ II, I try to use the symbol "constant" of the "maxplus2\max2lib\prim" library in a graphic description file (.gdf). I give a name on the left of the symbol, CST for example, a value on the right, 2 for example, and I try to affect the constant on an output (output symbol of the prim library) named CST[3..0] to have 4 bits on this output. The output is connected to a bus line named CST[3..0]; When I compil, I have always error message like "node missing name" or "mismatch pinstub" etc..(I have tried serveral solutions). What is the syntax for use this symbol (with the lpm_cosntant of lpm library, there is no problem, but the software recommand "constant" for a best fitting). Thank you for your help.Article: 52524
Hi, I am designing a butterfly processor.But the issue is the professor wants to pipeline on each CLB stage so he can get the maximum speed.Since butterfly processor is manily consisted of adders and multipliers,I have to design the bit-level adder.The multiplier is made too big because the clock rate is the propogation delay of a single CLB.Does anyone have any suggestions? Thank you very much! sincerely ------------- Kuan Zhou ECSE department
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