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Ray Andraka wrote: > You might also look at the distributed arithmetic tutorial page on my > website. Will do, thanks. I have found your website very useful so far, especially the CORDIC paper. -- DAB sounds worse than FM, Freeview, Digital Satellite and Cable -- http://www.digitalradiotech.co.uk/ Subscribe for free to the Digital Radio Listeners' Group NewsletterArticle: 56001
In article <3ed28769$1@news.iconz.co.nz>, James Fitzsimons <jamesf@intergen.co.nz> wrote: > >> U1 is a clock oscillator module, I should have made that clear > >Um, at the risk of sounding stupid, what part are you using for this? Ben >Jackson posted a link to a Xilinx app note that uses a 555 timer to generate >a 14Hz clock signal, but this seems kinda slow. I thought these CPLD's were >supposed to operate in the ~100Mhz range? They *can* but it depends on what you're doing. I thought the same thing about the 555 in that appnote. I built my board with a socket for a half- size clock oscillator (same size as 8pin dip, but only 4 pins, one at each corner). The slowest oscillator I bought was 1Mhz. So if you want to do a blinky-light demo, the first thing you'll want to do is divide by nearly 1M (about 2^20). Ok, there's 20 macrocells for a clock divider! Yes, half of your XC9536. So a clock source in the handful-of-Hz range is perfect for experiments. As for how fast you *can* go, look at the datasheet. It shows how to read the partnumber to find the gate speed. The slow parts are "-15" (or even -20 for the XC95108, I think). That means 15ns gate speed, or about 1/15ns = about 66Mhz (probably the practical limit is slower). And note that there are THREE global clock inputs on a XC9536/72, so you can run different parts of your logic at different speeds. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 56002
Hi, Anybody out here knows if the EDK 3.2 works with Webpack ? If this information is somewhere on their webpagees, they are hiding it pretty well ;-) cheers & thanksArticle: 56003
Ben Jackson wrote: > > Why is there such a large difference between the ratio of "flops"/IO > on a CPLD vs a FPGA? Something like a UART takes a trivial amount > of space in an FPGA, but would fill a medium sized CPLD (which will > only be available in packages with 100+ IOs). The 'Why' is historical. The PLD family geneology traces back to 22V10 and 16V8. Few registers, and wide product terms, plus add in some skew from meeting the old 'prep' benchmarks :) Adding registers to this topology costs many fuses, because of the fan-in logic seen in PLDs. FPGAs are more granular - finer grained, and the regsiters come at low cost. There are no _technical_ reasons preventing : a) A CPLD with more registers shipping in a smaller package or b) Improving PLD architecture to give higher FF/Product term ratios. There is a market opening for a Wide Voltage, Low Power, PLD device family that is 'timing chain' friendly, so can tackle tasks like UART / Watchdog / PowerSequencing / IO expansion. Packages down to 3mm x 3mm. -jgArticle: 56004
emanuel stiebler wrote: > Hi, > Anybody out here knows if the EDK 3.2 works with Webpack ? > If this information is somewhere on their webpagees, they are hiding it > pretty well ;-) It should do - EDK 3.2 is shipped with a copy of Webpack in the same package! JohnArticle: 56005
> There is a market opening for a Wide Voltage, Low Power, PLD device >family that is 'timing chain' friendly, so can tackle tasks like >UART / Watchdog / PowerSequencing / IO expansion. Packages down >to 3mm x 3mm. How much of that opening is covered by software and things like PICs? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56006
and will need how many FFs ?Article: 56007
rickman wrote: > I am finding JTAG to be a major hassle to try to use for both debug and > production boundary scan. Seems there are conflicting requirements > which the two camps are not generally interested in dealing with. > > The biggest problem is the fact that a lot of debugger tools don't like > having anything extra in the scan path. I have never gotten a clear > answer from TI about this on their DSPs. They have lots of app notes > telling you how to do it, the software has hooks for describing the > other devices, but support tells me not to try! I have not looked into > the issue with the ARM tools yet. I can understand why. It's a pain in the butt to do it right. But you'd definitly expect TI to be able to deal with it. > My design will have three separate voltage sections where the first > turns on/off the second and the second controls the third. So I am > using a separate JTAG chain for each section. The first will have just > a small CPLD. The second will have an ARM MCU and a large CPLD. The > third section will have the DSP and an FPGA. The DSP and FPGA will be > daisy chained, two jumpers can be used to isolate the DSP for debug. > The ARM and the CPLD will also be daisy chained. I am thinking about > using a combination of resistors and jumpers to try to minimize the > number and size of the jumpers (very, very small, crowded board). > > > +-----+ +------+ > TDO ---+---| ARM |--+--/\/\/-+--| CPLD |-----/\/\/---+-- TDI > | +-----+ | | +------+ | > | | | | | | > | | +--------)------)-----------0 0--+ > | | J1 | | J2 > +------)---------0 0--+ | > | | > | | > TRSTarm--/\/\/-+ TMScpld--/\/\---+ > | | > o o > J3 J4 > o o > | | > V V > > I figure that a 1K resistor driving a 10 pF load will create a 10 nS > (roughly) rise time. That should not create a problem with the 10 MHz > clocks typically found on JTAG. Anyone know if this will be a problem? > The stubs should all be pretty short since the entire circuit is only > about two or three inches long. The short stubs are important, and the traces shouldn't have any sharp angles - you want a really clean signal all around. I assume you've got ground planes and not a 2 layer board? That'll help a lot too. > I have also considered running all the JTAG through a single device > which will act as a JTAG "roundtable". But I really don't want to add > yet another chip to the board if I can help it, plus the signal routing > gets a bit long. I might be able to use the large CPLD for this, but it > is in the "far" corner of the board from the rest of the JTAG. Jumpers should work just fine. If you can put multiple jtag headers next to each part that'd work great too, but it also takes up more space. Debuggers don't do boundary scan for reason - it's hard enough to make the debugger work! But I'd really like to know how many people would buy a combined device. I've thought about it, but it just seems like the market is too small and the effort too large. Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 56008
Hal Murray wrote: > > > There is a market opening for a Wide Voltage, Low Power, PLD device > >family that is 'timing chain' friendly, so can tackle tasks like > >UART / Watchdog / PowerSequencing / IO expansion. Packages down > >to 3mm x 3mm. > > How much of that opening is covered by software and things like > PICs? I was looking for exactly this, including low power, low voltage (for battery backup of the RTC operation) and wide temperature. Seems none of the micros are very good at meeting all of the requirements at the same time. At least I couldn't find one. The people at Microchip (who had the best chance of filling this socket, IMHO) would not or could not search their own product line to find such a device. Motorola and National both had poor performance in their ADCs (about five effective bits) and still could not meet the voltage and temp requirements at the same time. The only device I could find was an automotive temp CPLD part from Lattice that comes in a small TQFP48 package (9x9 mm) and a Xilinx part in a larger VQFP44 package (12x12 mm). I am also planning on using the Semtech "MicroBuddy" part designed for exactly this function. It also comes in a 3x3 mm QFN package. If the reset function was a bit more flexible and the fast clock generator was a bit faster, I could eliminate a couple more parts from my board. This is a really interesting part. I am going to meet with the FAE this week to give him my suggestions about how to make this part more flexible, although in a slightly larger package. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56009
Hal Murray wrote: > > > There is a market opening for a Wide Voltage, Low Power, PLD device > >family that is 'timing chain' friendly, so can tackle tasks like > >UART / Watchdog / PowerSequencing / IO expansion. Packages down > >to 3mm x 3mm. > > How much of that opening is covered by software and things like > PICs? Some, but not all. Many of the SW solutions are 'forced' because there is little alternative. Rick covers many of the reasons, in his reply, I'll add some more: CPLDs are sub 100uA, but not sub 1uA, and they have narrow Vccs. FPGAs are moving away from 'low power' even static: the newest ones are now tens of mA, and I'm waiting on the 90nm figures to see what their Static Icc has done. uC are good at slow, sequential work, but if you need a hard reset path, or a WDOG, you ideally need that in logic. PLDs can be 'in many places at once', and can support much higher slave comms speeds, and more reliably, than soft solutions. On the Icc front, PIC class uC struggle to go sub 15uA, which is still well above Icc's of the better RTC chips. Imagine a ((RTC+NE555+4060+4093+22V10) * many), with the wide 1.65-5.5V Vcc of TinyLogic and you get the target I envisage. Would end up as widely used as EEPROMS :) -jgArticle: 56010
"James Fitzsimons" <jamesf@intergen.co.nz> wrote in message news:3ed28769$1@news.iconz.co.nz... > Hi Leon, > > > You've spurred me on to update the page. 8-) > > Good to know ;-) > > Please let me know when you've done it, as I would like to read your > updates. > The page has been updated: http://www.geocities.com/leon_heller/pld_starter.html It now includes the artwork for a simple PCB design for the circuit, which may easily be made at home. It needs some more work, so check it from time to time. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 56011
Hi Ralph No not directly. I think that it is a more elegant solution. Furthermore, you could save some area by using existing clockgrids, at least from what I have understood. But the most important reason is that I am doing this for an assigment in school. Regards JohanArticle: 56012
Hi latest Xilinx iMpact doesnt seem to support the old style Parallel III cable any more, and it seems there is no way to get the bitstream into Spartan - the iMpact generated STAPL file does not work with JAM player 2.3 gives bound error. We just received some Spartan II evaluation boards only to find out that there are no means to get them configured. any good advice? download software that takes the .bit and supports parallel cable III? or a hint where to find STAPL player that doesnt get upset on xilinx generated files? tnxArticle: 56013
Antti Lukats <antti@case2000.com> wrote:
: Hi
: latest Xilinx iMpact doesnt seem to support the old style Parallel III
: cable any more, and it seems there is no way to get the bitstream
: into Spartan - the iMpact generated STAPL file does not work with JAM
: player 2.3 gives bound error.
: We just received some Spartan II evaluation boards only to find out that
: there are no means to get them configured.
: any good advice?
: download software that takes the .bit and supports parallel cable III?
: or a hint where to find STAPL player that doesnt get upset on xilinx
: generated files?
Try appended patch. Please report if it helps.
Also perhaps naxjp might be used for downloading.
Bye
--- jamexec.c~ 2000-11-13 18:58:26.000000000 +0100
+++ jamexec.c 2002-12-03 22:05:25.000000000 +0100
@@ -816,6 +816,23 @@
long *long_ptr = NULL;
JAM_RETURN_TYPE status = JAMC_SUCCESS;
+ /* remove all white space */
+ while (statement_buffer[in_index] != JAMC_NULL_CHAR)
+ {
+ if ((!jam_isspace(statement_buffer[in_index])) &&
+ (statement_buffer[in_index] != JAMC_TAB_CHAR) &&
+ (statement_buffer[in_index] != JAMC_RETURN_CHAR) &&
+ (statement_buffer[in_index] != JAMC_NEWLINE_CHAR))
+ {
+ statement_buffer[out_index] = statement_buffer[in_index];
+ ++out_index;
+ }
+ ++in_index;
+ }
+ statement_buffer[out_index] = JAMC_NULL_CHAR;
+ in_index = 0;
+ out_index = 0;
+
while ((status == JAMC_SUCCESS) &&
((ch = statement_buffer[in_index]) != '\0'))
{
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 56014Hi I have a design where i have to multiply a 19.44MHz clock signal by four. I have tried to use a DCM. I connect my 19.44MHz signal to CLKIN and uses the CLKFX output as my new 77.76MHz clock. No other input/outputs are used. The 19.44MHz source is a crystal oscillator. The CLK_PERIOD attribute is set to 51.44 ns When I have downloaded this to my prototype board the DCM doesn't lock. What can be wrong? -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 56016
Hi Leon, Yes, you can implement a NIOS processor in the EP1C6 (or EP1C3 for that matter). How many LEs it will take depends on the number of peripherals and such that you want to build. My memory tells me that a basic processor takes on the order of ~1500 LEs (about 1/2 a 1C3 or 1/4 a 1C6). Regards, Paul Leventis Altera Corp. "leon qin" <leon.qin@2911.net> wrote in message news:baumve$3k73p$1@ID-185326.news.dfncis.de... > and will need how many FFs ? > > >Article: 56017
I agree, well said! "Brian" <usenet@carlsonclan.com> wrote in message news:bv8scv04vafonm72orb3aa92gqi29hg96u@4ax.com... > Describing hardware with text doesn't make it software.... > > To me, the big difference is that a software designer describes the > behavior he wants. That behavioral description is turned into > instructions to be executed by pre-defined hardware. > > A hardware designer takes the same problem and solves it by describing > the hardware that he wants. He could describe that hardware with a > schematic for ICs on a PCB, a schematic for a FPGA, HDL for a FPGA, > or whatever. It doesn't matter, he's still describing the same > hardware. The FPGA (or CPLD) just gives us a way to implement that > hardware without using a solding iron to make changes :) >Article: 56018
"Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0305270412.307530aa@posting.google.com... > Hi > > latest Xilinx iMpact doesnt seem to support the old style Parallel III > cable any more, and it seems there is no way to get the bitstream > into Spartan - the iMpact generated STAPL file does not work with JAM > player 2.3 gives bound error. You could download the older programmer software. I had to do this to program the XC9536 with the newer WebPack software. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 56019
Patrik, Should work fine. Check to see that the clock is making it to the DCM without any glitches (by pinning it out and monitoring it). Also, try resetting the DCM directly (thru a switch or pushbutton). Starting up the DCM sometimes doesn't work without a reset due to how the external clock oscillator starts up, and what the IOs are doing after configuration. Austin Patrik Eriksson wrote: > > Hi > > I have a design where i have to multiply a 19.44MHz clock signal by > four. I have tried to use a DCM. I connect my 19.44MHz signal to CLKIN > and uses the CLKFX output as my new 77.76MHz clock. No other > input/outputs are used. The 19.44MHz source is a crystal oscillator. > > The CLK_PERIOD attribute is set to 51.44 ns > > When I have downloaded this to my prototype board the DCM doesn't lock. > > What can be wrong? > > -- > Patrik Eriksson | patrik.eriksson@netinsight.net > Net Insight AB | phone: +46 8 685 04 89 > Västberga Allé 9 | fax: +46 8 685 04 20 > SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 56020
I have two answers (opinions) 1) It is not possible. The contract between Xilinx and the synthesis vendor was terminated over a year ago. There is NO HDL software support for this device from Xilinx. See if Digilent will trade the board for a SpartanII board. 2) The software is good, but the board is useless. All it has is the chip on a PCB; no oscillator, stake pins for I/O, and not even a voltage regulator. (I was going to make an expansion for mine, but decided that getting a different board would be cheaper.) $.02, SH7 PS: Take a look at Tony's products: www.burched.com On Tue, 27 May 2003 12:54:38 -0700, "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote: >Hi everyone, > >I have 2 questions: > >For the past few weeks I've been trying to get started with VHDL and FPGA's. >I've purchased a Spartan board from Digilent and I've also purchased the >Student software from XILINX. The problem im having is when I load the >XILINX software and select the Spartan device it won't allow me to select a >VHDL design flow, it only allows EDIF. If I select a Spartan2 device it >will allow VHDL. Does anyone know if its possible to get the XILINX Student >software to work with a Spartan in VHDL? > >My second question is: Does anyone have any opinions on the Cypress Delta39K >CPLD Evaluation Board? Im thinking of buying it so I can implement a >Digital Phase Locked Loop on it, in VHDL. Would it be capable of doing >this? It appeals to me because it comes with the Cypress Warp VHDL >software, is this software any good? > >Thanks for any help, >Article: 56021
Thanks, but that paper desscribes a state machine using a 4x oversampled clock, which isn't an option for me with a 300MHz data clock. -Kevin "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message news:bavk0a$qia$1@newsg4.svr.pol.co.uk... > Hi Kevin, > > Im not sure if its what your looking for but the website www.usb.org has a > document which describes how to extract the clock from an NRZI signal. It > includes a state machine. The document is called siewp.pdf. > > > "Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message > news:JAPxa.892089$F1.111144@sccrnsc04... > > Is there a good way to do clock recovery (from, say, an 8B/10B data > stream) > > on a 300Mbps data using a Xilinx without the use of any external PLL or > > analog components? > > -Kevin > > > > > >Article: 56022
Jim Granville wrote: > > Imagine a ((RTC+NE555+4060+4093+22V10) * many), with the wide 1.65-5.5V > Vcc of TinyLogic and you get the target I envisage. > Would end up as widely used as EEPROMS :) This is largely what I am going to suggest to Semtech. Their MicroBuddy is a very good start down that path. They just need to tweek some of the specs and add the programmable logic. I am not sure what the 4093 is, but I think the 4060 is a counter chain, no? The MicroBuddy has a FLL running from the watch crystal which may do what you want with the 555 and 4060. Since this chis is in a 3x3 QFN, if it had a higher freq range on the FLL, I would use it as clock generators scattered around my board. I don't know much about designing PLD chips, but it would seem to me that there is a market for very low power PLDs. While looking at discrete logic I noticed that the old 4000 series CMOS was much lower power than most of today's logic. I believe the quiescent current was in the nA range. For programmable, low power designs, that would be pretty amazing stuff to work with! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56023
On Tue, 27 May 2003 12:15:29 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Jim Granville wrote: >> >> Imagine a ((RTC+NE555+4060+4093+22V10) * many), with the wide 1.65-5.5V >> Vcc of TinyLogic and you get the target I envisage. >> Would end up as widely used as EEPROMS :) > >This is largely what I am going to suggest to Semtech. Their MicroBuddy >is a very good start down that path. They just need to tweek some of >the specs and add the programmable logic. I am not sure what the 4093 >is, but I think the 4060 is a counter chain, no? The MicroBuddy has a >FLL running from the watch crystal which may do what you want with the >555 and 4060. The 4093 is a quad nand schmitt trigger. I think this dream part would be easier to use if it had schmitt inputs, with guaranteed min and max hysteresis and threshold voltages. (No doubt Peter A. will point out his app note that shows how to use "spare" pins and some resistors to make a schmitt input. But I usually find I need a high input impedance (or can't spare the pins), and it's easier to put a '14 or '132 on the board.) Regards, Allan. >Since this chis is in a 3x3 QFN, if it had a higher freq range on the >FLL, I would use it as clock generators scattered around my board. > >I don't know much about designing PLD chips, but it would seem to me >that there is a market for very low power PLDs. While looking at >discrete logic I noticed that the old 4000 series CMOS was much lower >power than most of today's logic. I believe the quiescent current was >in the nA range. For programmable, low power designs, that would be >pretty amazing stuff to work with!Article: 56024
"Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag news:80a3aea5.0305270412.307530aa@posting.google.com... > Hi > > latest Xilinx iMpact doesnt seem to support the old style Parallel III > cable any more, and it seems there is no way to get the bitstream > into Spartan - the iMpact generated STAPL file does not work with JAM > player 2.3 gives bound error. > > We just received some Spartan II evaluation boards only to find out that > there are no means to get them configured. > > any good advice? Get the "old" JTAG programmer software. Its somewhere on the Xilinx Webpage. -- MfG Falk
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z