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On Tue, 27 May 2003 17:02:49 -0700, "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote: > >Do you know if the XILINX Student software places any restrictions on the >VHDL for the Spartan 2 FPGA's? For example code size etc. > IIRC, the limitation is that the 2 largest Virtex parts are missing. Why student edition? Why not down-load WebPack? It has similar limitations (none that you care about), it's up-to-date, and you can get a simulator to go with it. SH7Article: 56051
ararghNOSPAM@NOT.AT.enteract.com wrote: > > On Tue, 27 May 2003 23:52:22 GMT, CBFalconer <cbfalconer@yahoo.com> > wrote: > > >Brett Foster wrote: > >> "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > >> > > >> > The short stubs are important, and the traces shouldn't have > >> > any sharp angles - you want a really clean signal all around. > >> > I assume you've got ground planes and not a 2 layer board? > >> > That'll help a lot too. > >> > >> Why no sharp angles? > > > >Those electrons are moving at an appreciable fraction of the speed > >of light, and tend to oversteer. The rear end breaks loose going > >around those corners, and they are likely to go straight through > >the wall and injure somthing. :-) > > Gee, and I though that the smooth curves were not well thought of: > from back in the days of hand layout, and black plastic trace tape, > and the curves would move after some time as the tape shrunk after > being stretched to make the nice curve. > > -- > Arargh at [drop the 'http://www.' from ->] http://www.arargh.com > Basic Compiler Samples Page: http://www.arargh.com/basic/basic.html > > To reply by email, change the domain name, and remove the garbage. The requirements for tape staying in place and for good electrical properties don't coincide precisely. Are you surprised? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 56052
On Tue, 27 May 2003 22:14:01 -0400, Jerry Avins <jya@ieee.org> wrote: >ararghNOSPAM@NOT.AT.enteract.com wrote: >> >> On Tue, 27 May 2003 23:52:22 GMT, CBFalconer <cbfalconer@yahoo.com> >> wrote: >> >> >Brett Foster wrote: >> >> "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message >> >> > >> >> > The short stubs are important, and the traces shouldn't have >> >> > any sharp angles - you want a really clean signal all around. >> >> > I assume you've got ground planes and not a 2 layer board? >> >> > That'll help a lot too. >> >> >> >> Why no sharp angles? >> > >> >Those electrons are moving at an appreciable fraction of the speed >> >of light, and tend to oversteer. The rear end breaks loose going >> >around those corners, and they are likely to go straight through >> >the wall and injure somthing. :-) >> >> Gee, and I though that the smooth curves were not well thought of: >> from back in the days of hand layout, and black plastic trace tape, >> and the curves would move after some time as the tape shrunk after >> being stretched to make the nice curve. >> >> -- >> Arargh at [drop the 'http://www.' from ->] http://www.arargh.com >> Basic Compiler Samples Page: http://www.arargh.com/basic/basic.html >> >> To reply by email, change the domain name, and remove the garbage. > >The requirements for tape staying in place and for good electrical >properties don't coincide precisely. Are you surprised? Not really. I haven't been near PCB design for 20 years. Things change. -- Arargh at [drop the 'http://www.' from ->] http://www.arargh.com Basic Compiler Samples Page: http://www.arargh.com/basic/basic.html To reply by email, change the domain name, and remove the garbage.Article: 56054
I thought this was largely disproven. Or at least the effect rather minimal (negligible). "CBFalconer" <cbfalconer@yahoo.com> wrote in message news:3ED3F57F.DA151F5F@yahoo.com... > Brett Foster wrote: > > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > > > > > > The short stubs are important, and the traces shouldn't have > > > any sharp angles - you want a really clean signal all around. > > > I assume you've got ground planes and not a 2 layer board? > > > That'll help a lot too. > > > > Why no sharp angles? > > Those electrons are moving at an appreciable fraction of the speed > of light, and tend to oversteer. The rear end breaks loose going > around those corners, and they are likely to go straight through > the wall and injure somthing. :-) > > -- > Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) > Available for consulting/temporary embedded and systems. > <http://cbfalconer.home.att.net> USE worldnet address! > >Article: 56055
Here we go: http://www.ultracad.com/90deg.pdf Conclusions: The TDR data do not show any measurable reflections from either 45o or 90o corners in microstrip traces. In theory, there is a change in Zo caused by a corner, but the effect is not sufficient to be resolvable with a 17 ps rise-time pulse. The radiated emission measurements (up to 1.3 GHz.) do not show an increase for 90o corners, compared to 45o corners, that is larger than measurement uncertainty. All of the trace geometries measured produced radiated emissions that were 35-50 dB below the emissions of a 3-cm long monopole antenna and only slightly above those from a straight trace with no corners. For most circuit boards it is expected that discontinuities encountered at IC packages, connectors, and vias will produce much larger reflection or radiation effects than either 45o or 90o corners. "Brett Foster" <custserv@forums.ws> wrote in message news:bb1dbr$4i891$1@ID-184277.news.dfncis.de... > I thought this was largely disproven. Or at least the effect rather minimal > (negligible). > > "CBFalconer" <cbfalconer@yahoo.com> wrote in message > news:3ED3F57F.DA151F5F@yahoo.com... > > Brett Foster wrote: > > > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > > > > > > > > The short stubs are important, and the traces shouldn't have > > > > any sharp angles - you want a really clean signal all around. > > > > I assume you've got ground planes and not a 2 layer board? > > > > That'll help a lot too. > > > > > > Why no sharp angles? > > > > Those electrons are moving at an appreciable fraction of the speed > > of light, and tend to oversteer. The rear end breaks loose going > > around those corners, and they are likely to go straight through > > the wall and injure somthing. :-) > > > > -- > > Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) > > Available for consulting/temporary embedded and systems. > > <http://cbfalconer.home.att.net> USE worldnet address! > > > > > >Article: 56056
On Wed, 28 May 2003 00:21:55 -0400, "Brett Foster" <custserv@forums.ws> wrote: >I thought this was largely disproven. Or at least the effect rather minimal >(negligible). > >"CBFalconer" <cbfalconer@yahoo.com> wrote in message >news:3ED3F57F.DA151F5F@yahoo.com... >> Brett Foster wrote: >> > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message >> > > >> > > The short stubs are important, and the traces shouldn't have >> > > any sharp angles - you want a really clean signal all around. >> > > I assume you've got ground planes and not a 2 layer board? >> > > That'll help a lot too. >> > >> > Why no sharp angles? >> >> Those electrons are moving at an appreciable fraction of the speed >> of light, and tend to oversteer. The rear end breaks loose going >> around those corners, and they are likely to go straight through >> the wall and injure somthing. :-) Notice the last thing on this line? >> >> -- >> Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) >> Available for consulting/temporary embedded and systems. >> <http://cbfalconer.home.att.net> USE worldnet address! >> >> > -- Arargh at [drop the 'http://www.' from ->] http://www.arargh.com Basic Compiler Samples Page: http://www.arargh.com/basic/basic.html To reply by email, change the domain name, and remove the garbage.Article: 56057
Hi, With an N depth RAM, I could build a FIFO of depth N. Right? But this may not be true with asynchrnous FIFO. some where i heard that, for asynchrnous FIFO 1 location is wasted. why? and How? In general all the Circular FIFO documents also, saying that only N-1 depth is possible with N location RAM.? why? Thanks in advance Regards, MuthuArticle: 56058
"Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0305272041.4361c105@posting.google.com... > Hi, > > With an N depth RAM, I could build a FIFO of depth N. Right? > > But this may not be true with asynchrnous FIFO. some where i heard > that, for asynchrnous FIFO 1 location is wasted. why? and How? > > In general all the Circular FIFO documents also, saying that only N-1 > depth is possible with N location RAM.? why? > > Thanks in advance > > Regards, > Muthu You can never fill the FIFO to N because then the write pointer and the read pointer would be equal and it would look like the fifo was empty. RalphArticle: 56059
when I recompile an old design into Cyclone,it tell : Assertion error: Can't convert ROM for Cyclone device family using altsyncram megafunction -- at least one clock is needed in order to implement benchmarking mode for altsyncramArticle: 56060
> made some tests using iMPACT, version ISE 5.2.01i using Parallel cable III > (DLC5), worked fine in batch mode and worked fine using Impact GUI > interface - could not find a bug ... What version of iMPACT do You use ??? thank you all folks: really this maybe first time in my life to get real help after asking a simple :) question, mostly I when I ask I dont get (meaningful response). for general interest I describe a little more: 1) Tried maxjp (latest) does program the 18V02 but the programmed image does not work (xilinx done never comes) 2) tried JAM (syntax error), will check the patch, tnx 3) tried to convert SVF to JAM and play that JAM, failed 4) tried svf2xsvf and xsvfplayer, failed 5) tried iMpact ver 5.2.01i failed with following: "Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr.sys version = 5.2.0.0. Installing WinDriver... Failed. Cable connection failed." I dont understand if that is failure to install windriver or failure to detect cable. I made small PLD to LPT that 'detects' cable sensing (as sensing of cable III) and while impact is sensing I see no activity as if impact would not access parallel port (or sense cable III) - as per xilinx docs I see no mentioning of cable III support, only IV 6) when I do JAMID I get my chain tested OK, 18V02 and XC2S200 7) if I play JAM files that do not program XC2S200 then they work also 8) I have once tried PersonalJTAG but that doesnt work asmuch as I remember 9) right now did run the SVF with lattice ispVM SVF debugger this seems to work but I need to make then lattice cable to xilinx board :) thanks again! I think today I master it :) well I have myself done a selectmap downloader (to XC2S200 on PSoC ICE) and yesterday I almost finished my own SVF player, but hopefully I get iMpact (or possible older jtag programmer) to work! antti ps naxjp works real good with XC95xxXLArticle: 56061
ok I'l try. "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:nSJAa.65115$cK1.56454@news01.bloor.is.net.cable.rogers.com... > Hi Leon, > > Yes, you can implement a NIOS processor in the EP1C6 (or EP1C3 for that > matter). How many LEs it will take depends on the number of peripherals and > such that you want to build. My memory tells me that a basic processor > takes on the order of ~1500 LEs (about 1/2 a 1C3 or 1/4 a 1C6). > > Regards, > > Paul Leventis > Altera Corp. > > "leon qin" <leon.qin@2911.net> wrote in message > news:baumve$3k73p$1@ID-185326.news.dfncis.de... > > and will need how many FFs ? > > > > > > > >Article: 56062
> SVF is for serial vector formal => a nice format to describe a jtag > chain (have nice advantages for the config and download over JTAG and > assembly board test, but a little bit NOT apropriate for debug). > > Amontec Team is actually working on a low cost universal JTAG solution > based SVF format and over the USB1. I just worry about the TI svf support! just a comment on TI-JTAG ok, one line comment: TI-JTAG is TI-JTAG! read as following - TI chips do have JTAG but to use JTAG on TI chips (DSP) you need TI provided JTAG-Interface and software! if you dig deep on TI then you find that TI requires TI JTAG TAP master (or similar PLD desingn) to be used in JTAG interface that talks to JTAG on TI DSP. There is licensing possible to use some parts of TI API to support your own JTAG interface (based on TI TAP master!) but the fee is 1000$ per DSP family for binary license and not known under NDA for license to use source (of TI APIs). Also there are zillion of versions of those TI JTAG APIs, zillion of them are still in use, trying to support all that is a nightmare. Would be better if TI would make the TI-DSP JTAG Debug commands public, but they dont do that :( antti lukatsArticle: 56063
So my question is if there any alternate way to implement both DLL and DFS function when my input clk is less than 24MHz? or I have to change my application. "Austin Lesea" <Austin.Lesea@xilinx.com> ??????:3ED3C590.F0C93004@xilinx.com... > Jon, > > The DCM CLKFX feature works down to a 1 MHz input frequency (as long as > the output being synthesized is greater than 24 MHz). > > Note that you can not use "sync to DLL" (ie connect CLK0 to CLKFB) in > this mode (DFS only mode). > > AustinArticle: 56064
>> In general all the Circular FIFO documents also, saying that only N-1 >> depth is possible with N location RAM.? why? >You can never fill the FIFO to N because then the write pointer and the read >pointer would be equal and it would look like the fifo was empty. You CAN use that last word. But doing so generally makes the control logic a lot more complicated. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56065
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message > Try appended patch. Please report if it helps. I think the patch want help as the line that JAM reported error (bounds error) did not contain any special chars. at the fist I did think JAM dies at DRSCAN 1383000, because of buffer overflow but after recheck, the bounds error was before that long DRSCAN, so I assume the JAM (or STAPL) generated by iMpact must have been invalid. I finally succeeded somewhat in my attempts, when generating 18v02 STAPL with iMact then that works with JAM player (well its REAL slow!) - well at least I have minimal toolchain to test the XC2S200 on the memec spartan PCI board. antti lukatsArticle: 56066
Hi all, 1 - I want to use IL711 with LVDS. Is common ground wire required between transmitter and receiver? 2 - I want to run built in LVDS drivers of Spartan IIE on CAT5 cable. Cable length is about 30 meter. Is there any problem? Regards. M. NaderiArticle: 56067
Hello again, see following comments: best regards Peter Seng, SENG digitale Systeme GmbH "Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag news:80a3aea5.0305272156.4c8caa50@posting.google.com... > > made some tests using iMPACT, version ISE 5.2.01i using Parallel cable III now also tried with iMPACT, version ISE 5.2.02.i --> worked fine > > (DLC5), worked fine in batch mode and worked fine using Impact GUI > > interface - could not find a bug ... What version of iMPACT do You use ??? > > thank you all folks: really this maybe first time in my life to get real > help after asking a simple :) question, mostly I when I ask I dont get > (meaningful response). > > for general interest I describe a little more: > > 1) Tried maxjp (latest) does program the 18V02 but the programmed image give me some hint, what is maxjp - never heard, hardware, software, where from ???? > does not work (xilinx done never comes) > 2) tried JAM (syntax error), will check the patch, tnx > 3) tried to convert SVF to JAM and play that JAM, failed > 4) tried svf2xsvf and xsvfplayer, failed > 5) tried iMpact ver 5.2.01i failed with following: > "Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr.sys version = 5.2.0.0. have following output from iMPACT running in batch mode, programming xc9572xl CPLD: D:\Programme\SENG\dlk51>impact -batch _dlk51_impact.cmd // *** BATCH CMD : setMode -bs // *** BATCH CMD : setCable -port auto0 -baud 9600 AutoDetecting cable. Please wait. Connecting to cable (USB Port). Cable connection failed. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. LPT base address = 0378h. Cable connection established. '1': Loading file 'D:\SengData\Projekte\017\PLD\P017A002\p017a002.jed' ... done. INFO:iMPACT:1366 - Reading D:/Programme/Xilinx/xc9500xl/data\xc9572xl.bsd... INFO:iMPACT:501 - '1': Added Device xc9572xl successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- // *** BATCH CMD : addDevice -position 1 -file D:\SengData\Projekte\017\PLD\P017A002\p017a002.jed // *** BATCH CMD : erase -p 1 -o Validating chain... Boundary-scan chain validated successfully. INFO:iMPACT:452 - The device 'xc9572xl' is in 'read-protect' mode. The device contents cannot be read. INFO:iMPACT:453 - The device 'xc9572xl' is in 'write-protect' mode. The device contents cannot be altered. '1': Putting device in ISP mode...done. '1': Erasing device... done. '1': Erasure completed successfully. // *** BATCH CMD : program -p 1 -v -w -r Validating chain... Boundary-scan chain validated successfully. '1': Putting device in ISP mode...done. '1': Programming device...done. '1': Putting device in ISP mode...done. '1': Verifying device...done. '1': Verification completed successfully. '1': Setting Read-Protect bits. '1': Setting Write-Protect bits. '1': Programming completed successfully. D:\Programme\SENG\dlk51>copy _dlk51_ProgInitData.dat dlk51.dat > Installing WinDriver... > Failed. What kind of operating system do You use, what about hardware drivers for parallel port access ?? Your windrvr.sys driver is of different version, and you get the message that install of windrvr fails --> think someting is wrong with the driver or loading it. > Cable connection failed." > > I dont understand if that is failure to install windriver or failure to > detect cable. I made small PLD to LPT that 'detects' cable sensing without driver Parallel cable III can´t work using NT4.0 based OS, check driver !!! ========================================================== ========================================================== > (as sensing of cable III) and while impact is sensing I see no activity > as if impact would not access parallel port (or sense cable III) - > as per xilinx docs I see no mentioning of cable III support, only IV > > 6) when I do JAMID I get my chain tested OK, 18V02 and XC2S200 > 7) if I play JAM files that do not program XC2S200 then they work also > 8) I have once tried PersonalJTAG but that doesnt work asmuch as I remember > 9) right now did run the SVF with lattice ispVM SVF debugger this seems to > work but I need to make then lattice cable to xilinx board :) > > thanks again! I think today I master it :) > well I have myself done a selectmap downloader (to XC2S200 on PSoC ICE) > and yesterday I almost finished my own SVF player, but hopefully I get > iMpact (or possible older jtag programmer) to work! > > antti > > ps naxjp works real good with XC95xxXLArticle: 56068
ben@ben.com (Ben Jackson) wrote in message news:<ieSAa.1043647$S_4.1046948@rwcrnsc53>... > In article <80a3aea5.0305270412.307530aa@posting.google.com>, > Antti Lukats <antti@case2000.com> wrote: > > > >latest Xilinx iMpact doesnt seem to support the old style Parallel III > >cable any more, > > I just built one and just upgraded to the latest WebPack SP (which includes > an impact update) and used it to write XC9536/72. > > In what way is it "not supported"? my fault I guess, I did not get it working with iMpact (cable not detected) and after reading xil docs, did decide that cable III is not any more supported (what seems not to be the case) - in xilinx docs they only state that Parallel IV is supported, that was the misleading part for me antti P.S. still have not figured out why I cant download with iMpact, all other parallel port tools workArticle: 56069
I've just updated my web page on getting started with PLDs, using the Xilinx XC9536: http://www.geocities.com/leon_heller/pld_starter.html I've provided single-sided artwork for a PCB that may easily be made at home with rudimentary facilities. I hope it proves useful. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 56070
Hallo, I have a lot of signals, inputs, outpits and variables in my VHDL-code and want to simulate it. In my vector source file I have selected some ,e.g. clk(signal), data_in (signal), data_out (signal) etc. After simulation some signal will not show in simulation waveforms. In simulation message window a massage like: Compiler synthesized away node s_enable_ram_a. Ignored vector source file node. Ignored node in vector source file. Can't find corresponding node name s_adress_a in design. Compiler synthesized away node s_pa2se_tmp[0]. Ignored vector source file node. In my VHDL-code this signals exist. Why does this warnings occure? How to watch variables, signal etc. during sumulation? Best regardsArticle: 56071
In article <3ED3EB88.7020900@xilinx.com>, neil.jacobson@xilinx.com says... > All versions of iMPACT support the Parallel Cable III. All versions of > iMPACT support the SpartanII family. > If you could give some indication of the error message you see or the > log messages displayed then that might help isolate the problem. > Thanks. > There are problems with Parallel Cable III. A few weeks ago I reported that the usercode/signature for CPLDs is read differently by Impact than by JTAG-Programmer. It seems that the read value is bit-reversed. The answer I got from the hotline was that it has to do with PC III and that they have to investigate. Seems they are still investigating, I got not other answer since then ... Best regards -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMdurst.itArticle: 56072
In comp.arch.embedded Brett Foster <custserv@forums.ws> wrote: > I thought this was largely disproven. Or at least the effect rather minimal > (negligible). Depends on what kind of "trace" you're talking about. ;-P If it happens to be a proper race track for electrons, a.k.a. high-energy particle accelerator, you'll have a rather "interesting" time trying to survive standing on the outside of any of its curved segments without heavy shielding in between. Kids: please _don't_ try this at home! -- Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de) Even if all the snow were burnt, ashes would remain.Article: 56073
In article <2ba3bbea.0305272309.44e0205d@posting.google.com>, naderimisc@yahoo.com says... > Hi all, > 1 - I want to use IL711 with LVDS. Is common ground wire required > between transmitter and receiver? > Common mode range for LVDS receivers is usually small, so it is better to have a good ground connection between transmitter and receiver. > 2 - I want to run built in LVDS drivers of Spartan IIE on CAT5 cable. > Cable length is about 30 meter. Is there any problem? > Will depend on the frequency too. I'm running LVDS (but not Spartan) over a 10 m cable at 50 MHz and it works decently. The main problem is that it is a little bit sensitive to noise, see above. Grounding and shielding (or error correction) will be essential. > Regards. > M. Naderi > Why not use a optical fibre? Best regards -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMdurst.itArticle: 56074
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