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>I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am >wondering what the best way is to measure the power consumption. I'm >looking for something relatively simple, which doesn't need to be >extremely accurate. Can I just measure the current draw across all the >VCC inputs and multiply those by VCC? What is the easiest circuit to >do this, since the currents will be so low - a BJT current amplifier? Fun question. Thanks for making me think. Old mechanical meters were often 50 microamps full scale. One in the lab says 0.25V,50uA range at the same switch setting. So it should work in current mode if you can stand 1/4 volt drop. The manual for a handy Fluke handheld meter says > 10 meg ohms in voltage mode. So pick a resistor that's small relative to 10megs and big enough to give a voltage you can measure and small enough not to screw up your circuit. 1K seems reasonable. That's 30 mV at 30 uA. 10K gives a better reading with more drop. Our use a scope to see the dynamics. The spec didn't say anything about voltage drop in current mode. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49926
Software defect. JTAG verify does not work. Xilinx is "working on it". Turning off the FPGA resets it to blank; you need to reload it. SH7 On 25 Nov 2002 16:38:24 -0800, k_guichard@hotmail.com (Kyle Guichard) wrote: >Hi all, > >When I program my spartan 2 using the ISE software using JTAG, it >tells me that "programming succeeded." However, when I verify the >design, it comes up with thousands of discrepancies in the design >actually on the fpga. When I implement very simple logic like an AND >gate, it works sporadicaly and does not work at all after shutting >down the fpga. > >Any help or direction would be great. > >thanks! >kyleArticle: 49927
HI all experts, Can somebody say me , how to implement a frequency multipliers with digital hardware without using a any combinational logic Thanks & Regards, SKillieArticle: 49928
Hi all,
We are currently designing PCI Core. I am having some
clarifications regarding delayed transactions:
1. When will delayed transactions occur generally? Suppose if our PCI
Core is only Target core, will only single delayed transactions occur
or is it possible to design our core such that it can handle multiple
delayed transactions?
2. Delayed transactions - suppose if we have PCI Target core, what
role should it play in delayed transactions?
3. Suppose if we are implementing delayed transactions, and target
issued retry, in that case if master hasnt responded with same
transaction or other masters wants to access the target with different
transactions - I think without latching the data and address, target
needs to give retry. In that case, i think some of the clock cycles
will be wasted until the delayed transaction is completed? what will
be the advantage of this delayed transactions?
4. Do we need to keep a prefetched buffer memory in our core for
delayed transactions?
Please reply soon,
Thanks
Naveen
Article: 49929I can introduce you our new FPGA PCI Platform, the Komodo Platform. The Komodo Board, associated with our FireMez expansions modules, provides a complet solution for developing designs and applications based on the Xilinx FPGA families. In his universal PCI format use, the platform becomes a complet and low cost 32-bit PCI solution based FPGAs. The first advantage of an PCI interface via a FPGA is the design flexibility. The onboard Xilinx Spartan-II has a full pin compatibility with the Xilinx PCI32 core, and with the Amontec ezPCI32 core. Master and Slave PCI interface can implemented, and with our own PCI Slave core called ezPCI. The high gate density and the large number of user I/O allows complete solutions to be implemented in the low cost FPGA. In his stand-alone use, this Komodo board provides a great platform for the Xilinx MicroBlaze soft processor. The three onboard DC/DC regulators can provides true 3A current. The generated 3.3V 2.5V 1.8V (1.5V) voltages are driven to the FireMez expansion module slots The Komodo Package comes with free PCI interface binary file for the Spartan-II FPGA, with free ezPCI Windows drivers and with free High level software. This PCI interface is based on our ezPCI32 core and provides a full access to the FireMez Slot and to the other parts of the PCI platform see a picture on http://www.amontec.com/komodo.shtml If you need a specific application with AD/DA, with specific communication system, with specific motor control system, we can build your own FireMez Module in the first time, and for a high production, we can integrate the Komodo board and the FireMez Module on the same single board. Best regards Laurent Gauch, amontec www.amontec.com Seth wrote: > I am looking for vendors of PCI FPGA boards for production, not just > prototyping. > > So far I know of Annapolis Microsystems which offers boards with > Virtex chips and RAM. > > Can anyone recommend any others?Article: 49930
yes, I'd better go back and change it to make it right, which is absolutely the wisest way for me. thank you! And, in one of the errors is that: 40MHZ clock(clk40M) is used to generate a 20M clock(clk20M),(clk40M and clk20M have the falling-edges at the same time ), then I look on the clk20M as a signal , and use the clk40M as clock to feed the clk20M to a register. Thus ,you know , the "clock skew larger than data delay" appears. but , the function can be reached . Must i change it ? kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0211251024.8881d7c@posting.google.com>... > The quandary in which you find youself is repeated over and over in > digital design: > Should I go back and change it to make it right, or do I proceed > forward with the initial approach and patch the errors as they appear. > > I don't know all the particulars of your situation, however, It's been > my experience that you're better off going back and making it right. > The rewrite is a deterministic amount of time and work, and usually > proceeds faster than the initial design because after all, the hard > part is the learning and at that point you've already done it, the > easy part is the typing. Trying to move forward with hold violations > can set you up for failure due to an unpredictable design. Unrelated > changes can cause a previously working (you lucked out) circuit to > cease operation or because temperature sensitive. It's tough to debug > because the usual "cause and effect" way of finding problems does not > seem to apply. I always try for an error free compilation, even if it > means writting/changing source code with no other effect than to get > rid of warning messages. > > Regards > > President, Quadrature Peripherals > Altera, Xilinx and Digital Design Consulting > email: kayrock66@yahoo.com > http://fpga.tripod.com > ----------------------------------------------------------------------------- > > wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0211242015.2e44574b@posting.google.com>... > > well, there are mang things to do if i change to not do it. > > and ,However , some of my design's functions are not influenced by > > these errors"clock skew larger than data delay", can i let these > > errors alone? > > thank you ! > > kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0211241444.39f4003c@posting.google.com>... > > > You usually get this when you're passing signals between sequential > > > elements (flops, synchronous rams) clocked by different clock domains. > > > The best way to handle this is to not do it. Use a single high > > > frequency clock and then enables to get lower frequency operation. > > > Floorplanner is that last approach you want to do but can work if you > > > artificially increase the data delay by assigning the 2 sequential > > > elements far enough away from each other (timing wise) so that the > > > data delay is larger than the clock skew between the 2 domains. > > > > > > Regards > > > > > > President, Quadrature Peripherals > > > Altera, Xilinx and Digital Design Consulting > > > email: kayrock66@yahoo.com > > > http://fpga.tripod.com > > > ----------------------------------------------------------------------------- > > > > > > wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0211231852.33ba9a8f@posting.google.com>... > > > > hi,all > > > > i am a newer to fpga, and i am using QUARTUS to target > > > > EP20k200rc240-3v. > > > > the problem is that: when i complied the project the complication > > > > report always gave me the message "Circuit may not operate. 12017 > > > > non-operational path(s) clocked by clock gclk have clock skew larger > > > > than the data delay. See the Compilation Report for details." > > > > can you tell me what's the matter with "clock skew and data delay"? > > > > thanks a lot!Article: 49931
Hal Murray wrote: > > >I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am > >wondering what the best way is to measure the power consumption. I'm > >looking for something relatively simple, which doesn't need to be > >extremely accurate. Can I just measure the current draw across all the > >VCC inputs and multiply those by VCC? What is the easiest circuit to > >do this, since the currents will be so low - a BJT current amplifier? > > Fun question. Thanks for making me think. > > Old mechanical meters were often 50 microamps full scale. > One in the lab says 0.25V,50uA range at the same switch setting. > So it should work in current mode if you can stand 1/4 volt drop. > > The manual for a handy Fluke handheld meter says > 10 meg ohms > in voltage mode. So pick a resistor that's small relative to > 10megs and big enough to give a voltage you can measure and > small enough not to screw up your circuit. 1K seems reasonable. > That's 30 mV at 30 uA. 10K gives a better reading with more drop. > Our use a scope to see the dynamics. > > The spec didn't say anything about voltage drop in current mode. In practice it is not trivial to measure low-Icc on CPLDs, because you have to be able to deliver the peaks - eg during config, and during non-idle periods. The simplest bench method we have found, is to use a high resolution voltmeter ( 5+ digits ), and a LOW value resistor. eg 10 Ohms is 300uV at 30uA, and 100mV at 10mA, 300mV at 30mA So you are trading off the extra resolution for dynamic range, but even here the power supply impedance has been degraded. We plan to trial a custom linear regulator, using a TL431 and a MOSFET (simple follower), with the current meter in the drain. That should give low output impedance, and allow normal metering drops across the current sense element. - jgArticle: 49932
Hi all,
Can somebody tell me how to generate a signal frequency based on a count
input value.
say I have a 12 bit i/p which can be used to give binary inputs. I want to
generate an o/p signal frequency corresponding to each different i/p(2^12).
Thanks in advance
Skillie
Article: 49933For simulation, in Foundation you could just attach probes to the schematic to look at internal signals. In ISE (using the HDL Bencher), it appears that you can only look at signals on I/O markers... is there some way to look at internal signals without attaching an I/O marker?? Thanks AdrianArticle: 49934
There are various approaches, the simplest being just a counter, others might use the internal PLL of an FPGA ... What frequency range did you have in mind ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Skillwood wrote: > Hi all, > Can somebody tell me how to generate a signal frequency based on a count > input value. > say I have a 12 bit i/p which can be used to give binary inputs. I want to > generate an o/p signal frequency corresponding to each different i/p(2^12).Article: 49935
I need to implement a fastish DDS using a 32 bit accumulator (I need the resolution). However, I am hitting the carry ripple problem, and the fastest clock frequency I can manage at the moment is 20MHz Notwhitstanding using faster FPGAs or optimising the compilation (both of which can only help so far), are there any other techniques and tricks worth looking at? The application requires a very narrow range of frequencies in the 22-22.1MHz range, spaced a few Hz apart (hence the 32 bit accumulator). I could consider adding analogue frequency mixers and bandpass filters, but I'd rather avoid analogue circuits. Thanks in advance TheoArticle: 49936
On 26 Nov 2002 03:23:52 -0800, edaudio2000@yahoo.co.uk (ted) wrote: >I need to implement a fastish DDS using a 32 bit accumulator (I need >the resolution). > >However, I am hitting the carry ripple problem, and the fastest clock >frequency I can manage at the moment is 20MHz Sure you didn't slip a decimal place? A modern FPGA should be able to do a 32 bit accumulator using ripple carry comfortably at 200MHz, not 20MHz. Either you are using a very old and slow device, or there is something wrong with your design. ... but to help you, we will need to know which device and which design entry method you are using. It would also be a help if you posted your code. >Notwhitstanding using faster FPGAs or optimising the compilation (both >of which can only help so far), are there any other techniques and >tricks worth looking at? Make sure the carry chain is in the same slices as the phase accumulator flip flops. This will happen by default unless you have done something like add a preset to the accumulator. Pipeline everything. Don't worry about wasting flip flops. Regards, Allan.Article: 49937
i would like to add to that...towards my final year engienering project we were required to do a spartan2 pqfp203 based board. being amateurs that we were , we allowed orcad to do the autorouting for us and ended up with some integrity issues on TMS pin(we had a daisy chain of the fpga and a prom). i took us some "bloack magic" to get around that problem but the point is that it is really a BIG risk to jump into such a big design directly. the socket for pqfp costs a fiortune and we had to hard solder the fpga onto the board which caused additional headaches of their own. thought this might help. Nachiket Kapre Design Engineer. Paxonet Communications. Ray Andraka <ray@andraka.com> wrote in message news:<3DE2AA04.B165ECB1@andraka.com>... > Not a contradiction at all, besides I certainly make mistakes from time to > time. My point is that, yes, an FPGA can be successfully done in a wirewrap or > singlesided breadboard environment, BUT success may require alot of time > debugging signal and power integrity issues that the typical beginner is not > equipped to handle. Much depends on how many I/) you have switching, and how > much the power into the FPGA varies. If you only have a few I/O switching, and > you are careful to keep the power to the FPGA on low inductance runs with > bypassing right at the FPGA, plus a measure of luck, you'll likely get away > with it. If you've got lots of I/O switching, you've got a pretty poor chance > of success, especially if they all switch on the same edge. > > The design is much easier, and more likely to succeed if you have a good solid > board design to avoid corrupting your results. To wit, we've had several > designs this year that have had signal and power integrity problems on > commercially produced multi-layer boards. Clock frequency has little to do > with it, rather it is edge speeds coupled with the number of I/O switching that > cause the most problems. > > Markus Wolfgart wrote: > > > Hi Ray, > > > > I don't like to contradict you as I'm not a experienced fpga user, > > but from my hw know how it is very important and essential to have > > a good ground and power plane and of course a good blocking. > > As I noticed the XCS05 working up to 80mc, so I'm convinced that > > it's possible to work with self adhesive copper planes (sorry, I'm > > not quite sure if I use the right expression) on my bread board > > (with many holes, double faced, on top and bottom layer) and thin > > wires for the I/O's. > > I'm conscious that it's not the right design for a prototype pci > > card but its good enough for my first steps on fpga programming. > > > > In addition please could you tell me what you think about the > > printed board design of the following web project at: > > > > http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html > > > > When comparing the layout with my intention of wire the fpga > > directly, it's not a big difference from the layout point of view? > > > > Thanks in advance for your experience. > > > > Markus > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 49938
You can check www.dalanco.com David Seth wrote in message ... >I am looking for vendors of PCI FPGA boards for production, not just >prototyping. > >So far I know of Annapolis Microsystems which offers boards with >Virtex chips and RAM. > >Can anyone recommend any others?Article: 49939
This is a multi-part message in MIME format. --------------ED4FB938028C71DD4BAC321A Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Javier, Javier Fernández wrote: > Hello, > > I need advice on an FPGA & evaluation board to be used with System Generator > and MATLAB/Simulink. I would be most grateful if anybody could share his/her > experience on the subject. > > My boss wants to cover a couple of research lines with this equipment, > and he has decided that the FPGA must be a Virtex-II Pro for his research. > I should be able to use that hardware from MATLAB to speed computations up. > That would be the other line. Being a complete novice on the subject, > the only eval.board I haven been able to find is > http://www.insight-electronics.com/virtex2pro/ > That board is not to be connected to a PCI socket, is it? > Is there any Virtex-II Pro eval.board that connects to the PCI? There are no current boards that I know of that directly connect to PCI, but there are a number that can handle carrier cards that have V2P on board. > > > The MathWorks' courses for System Generator use the Nallatech BenADDA daughter > board. They don't explain which Nallatech motherboard is it connected to. > Could System Generator be used with the Insight's board? The BenADDA board can be connected to any of the Nallatech motherboards, including the one which is sold as part of the XtremeDSP kit. SysGen can be used with the Insight boards, but would be more useful with some form of ADC or DAC. Follow this link and you will find links to many other boards designed for DSP evaluation: http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protoboards_page Also - the Nallatech Xtreme Dev kit is found here: http://www.xilinx.com/ipcenter/dsp/development_kit.htm > > > Xilinx documentation also assumes "System Generator for DSP". There is another > "System Generator for PowerPC". I think I need the latter. Is that right? > For instance, in the "ISE Feature Matrix" comparing ISE Foundation to > Alliance, BaseX and WebPack, "SysGen for DSP" appears as an option to all but > WebPack. No mention is made to "Sysgen for PowerPC". > SysGen for DSP is the one you need. > > I have a lot of questions, but I wouldn't like to frighten anyone > willing to share experiences with a too lengthy list... ;-) > can anyone help me? > > Thanks a lot for any suggestion/remark/advice/help/whatever :-) > > -javier DaveArticle: 49940
Hi all, I switched my Xilinx tool from 4.2i to 5.1i. I opened the same project file in 5.1i which I had obtained using 4.2i. There was a dialog box asking for conversion of the project from 4.2i to 5.1i for which I opted YES. Eventhough there were no errors and warnings in the new tool synthesis and par, to my surprize I am getting finite hold times(which were zero in 4.2i), setup time violations and other timing constraint problems etc. Could any of you tell what the reason is? Waiting for a quick reply, NagarajArticle: 49941
Hello, I'm using a Xilinx XC5210 FPGA in my current project (based on a circuit that's a few years old). It works fine, but I'm wondering if anyone knows of anywhere in the UK to get spares? I'm tempted to migrate to a newer device regardless. Ideally though it should be in an 84-pin PLCC package so that replacement is easier if it blows, as it's only for development purposes. I'm thinking of the XCS10XL - would this be a suitable replacement for the XC5210? Also, does the XC18V00 series of PROM work with the XC5210? I know the former runs off 3.3v and the latter 5V, but in the datasheet it implied this shouldn't matter as the XC18V00 series are 5V I/O tolerant. Finally, how would the XC18V00 PROM be programmed from the Foundation software? (I have version 1.4 - it's old I know!) Would I simply connect the JTAG pins on the PROM to the download cable (I've got both parallel cable III and the serial cable)? Thanks in advance AngusArticle: 49942
We had to download an older version of the Webpack programming tool. Their website has these old versions available. Bob "Alderan" <renzo.busonera@tin.it> wrote in message news:CLwE9.54949$744.2016912@news1.tin.it... > Hello, i' ve some problem using Impact 4.2WP3.0 in win98SE. When i try to > program the device (an XC9536) a fatal error occurs (a not valid operation > occurs) and i must close the application. It's a very strange thing. What > may it be? > > THankyou > Giovanni > >Article: 49944
Ru-Chin Tsai wrote: > I prepare to implement MPEG-2 codec system for some application. > Does any one can give me some issues or suggestions about MPEG2 > implemetation on FPGA v.s. DSP? Which one can reach real-time > encoding/decoding? Which one has higher complexity and cost? The > MPEG-2 codec kernel modules, > DCT、Motion-estimation(compensation)、Variable-length > coding(VLC)...etc, do any SOFT-IP CORES are available now? Check the Xilinx and Altera web sites, they should have lots of cores to choose from. Also check the TI and ADI and Motorola web sites, they probably have reference designs you can look at as well. I suspect DSP will cost less in design time, but might be a touch more in hardware. Things are changing fast tho, FPGA's are getting more bang for the buck every day and the tools are improving a lot. I don't think it's an obvious choice, so you have lots of homework to do :-) Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 49945
Check to see that your global clock buffers are where you expect them relative to the clock pins. If you can still compile with 4.2i you can do a direct comparison of the clock delays through the timing analyzer. "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0211260612.7301fa8b@posting.google.com... > Hi all, > I switched my Xilinx tool from 4.2i to 5.1i. I opened the same > project file in 5.1i which I had obtained using 4.2i. There was a > dialog box asking for conversion of the project from 4.2i to 5.1i for > which I opted YES. Eventhough there were no errors and warnings in the > new tool synthesis and par, to my surprize I am getting finite hold > times(which were zero in 4.2i), setup time violations and other timing > constraint problems etc. > Could any of you tell what the reason is? > > Waiting for a quick reply, > NagarajArticle: 49947
Ripple carry? Isn't that where a Q output feeds the clock of the next stage up? A straight accumulator, fully synchronous, gives beautiful results. If there's some timing problems because the accumulation value (fractional phase amount accumulated each cycle) goes through some combinatorial stuff before hitting the adder, that just needs to be registered. If only registered values feed the accumulator, the results should scream. "Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message news:3de3611a.114493022@netnews.agilent.com... > On 26 Nov 2002 03:23:52 -0800, edaudio2000@yahoo.co.uk (ted) wrote: > > >I need to implement a fastish DDS using a 32 bit accumulator (I need > >the resolution). > > > >However, I am hitting the carry ripple problem, and the fastest clock > >frequency I can manage at the moment is 20MHz > > Sure you didn't slip a decimal place? A modern FPGA should be able to > do a 32 bit accumulator using ripple carry comfortably at 200MHz, not > 20MHz. > > Either you are using a very old and slow device, or there is something > wrong with your design. > ... but to help you, we will need to know which device and which > design entry method you are using. It would also be a help if you > posted your code. > > >Notwhitstanding using faster FPGAs or optimising the compilation (both > >of which can only help so far), are there any other techniques and > >tricks worth looking at? > > Make sure the carry chain is in the same slices as the phase > accumulator flip flops. This will happen by default unless you have > done something like add a preset to the accumulator. > > Pipeline everything. Don't worry about wasting flip flops. > > Regards, > Allan.Article: 49948
C A L L F O R P A P E R S THE ELEVENTH ANNUAL IEEE SYMPOSIUM ON FIELD PROGRAMMABLE CUSTOM COMPUTING MACHINES Napa Valley, California April 8 - April 11, 2003 http://www.fccm.org PURPOSE: To bring together researchers to present recent work in the use of reconfigurable logic as computing elements. This symposium will focus primarily on the current opportunities and problems in this new and evolving technology for computing. Contributions are solicited on all aspects of custom computing, including but not limited to: Architecture of reconfigurable computing devices and systems, including coprocessors, attached processors, reconfigurable systems-on-chip and hybrids; Languages, compilation techniques, tools, and environments for programming and run time support; Applications of reconfigurable computing, including the use of reprogrammable logic in mobile communications, network infrastructure and other embedded systems; Implications of nanotechnology and reconfigurable computing on one another, possible forms, system implications, use of reconfiguration to support fault avoidance; Novel use of reconfigurability, including evolvable hardware; Prototyping for system modeling and architecture emulation. SUBMISSIONS: FCCM has a tradition of presenting both full length papers and high quality posters. Authors are invited to send submissions for either full length papers (10 page maximum) or extended abstracts (2 page maximum) for posters by January 13, 2003, to Jeffrey Arnold. Please indicate whether you seek consideration as a full paper or as a poster. Notification of acceptance will be sent by the beginning of March. Final papers and poster abstracts will be due on the first day of the Symposium. The proceedings will be published following the Symposium. Authors are encouraged to submit PDF or Postscript manuscripts by FTP. Format and submission instructions are available on the FCCM web page (www.fccm.org), or authors can contact Jeffrey Arnold (jmarnold@ieee.org). Authors are also encouraged to bring demonstrations of their work. Space will be made available during the demo event to be held Wednesday, April 9. Details will be available on the web page. SPONSORSHIP: The IEEE Computer Society and the Technical Committee on Computer Architecture. CO-CHAIRS: Kenneth L. Pocek Intel Mail Stop RN6-18 2200 Mission College Boulevard Santa Clara, California 95052 Voice: 408-765-6705 Fax: 408-765-5165 kenneth.pocek@intel.com Jeffrey M. Arnold Stretch, Inc. 10686 Mira Lago Terrace San Diego, CA 92131 Voice: 858-547-9257 Fax: 858-547-9010 jmarnold@ieee.org PROGRAM COMMITTEE: Peter Athanas, Virginia Tech. Donald Bouldin, University of Tennessee, Knoxville Duncan Buell, University of South Carolina Michael Butts, Cadence Steve Casselman, Virtual Computer Corp. Andre DeHon, California Institute of Technology Apostolos Dollas, Technical Univ. of Crete Philip Friedin, Fliptronics Scott Hauck, University of Washington Brad Hutchings, Brigham Young Univ. Tom Kean, Algotronix, Ltd. Phil Kuekes, HP Labs. Philip Leong, Chinese University of Hong Kong Wayne Luk, Imperial College John McHenry, NSA Robert Parker, Institute for Information Sciences Viktor Prasanna, University of Southern California Herman Schmit, Carnegie Mellon University Mark Shand, HP Labs Satnam Singh, Xilinx Stephen Smith, Lochran Roger Woods, The Queen's University of BelfastArticle: 49949
Do you intend to take a 2kHz signal and multiply it to 33.5kHz using a fixed system clock of 40MHz? The question has some answers in it, too. If you want a slower frequency than some system clock, there are ways. If you have a reference clock - your only clock - which you want to increase the frequency, you need analog and/or combinatorial elements. If you want three output clocks for every input clock, how would you decide where to place the edge? A little more detail on a realizable problem will get you some good advice. "Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message news:arv489$me3js$1@ID-159866.news.dfncis.de... > HI all experts, > Can somebody say me , how to implement a frequency multipliers with > digital hardware without using a any combinational logic > > Thanks & Regards, > SKillie > >
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