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Rene, Please, do not discourage people from using internet based support tools. I can not speak for Altera (obviously), but email and web-based support is becoming a major means of asking and answering customer questions in a timely fashion. The fact that Altera has someone who watches the comp.arch.fpga forum indicates that they really do care about customer service, and 'caught' your inquiry in this forum. Our hotline group would prefer that a case gets entered into their system, as they will answer it quicker that way. But for those that wish to get other opinions, this newsgroup is also valuable. I know that Xilinx takes this all very seriously, and watches response time vs. how the case is entered to maintain quality of service target levels. Austin Rene Tschaggelar wrote: > Thanks for the quick reply. > Amazingly quicker than the mentioned 'MySupport', > but then again not - proves my point. > > Rene > > Subroto Datta wrote: > > Rene, > > A fix for this problem is under development. More details about its > > availability will be posted as soon as the fix is tested and released in the > > very near future (no later than end of this week). Thanks for bringing this > > problem to our attention. > > > > - Subroto Datta > > Altera Corporation > > > > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > > news:3E1B4021.2090607@dplanet.ch... > > > >>I found a bug in quartus2 Web V2.2. > >>When tring to place legacy components in schematic editor, > >>such as the 74165b shiftregister, its connectors are off > >>grid. This makes it somewhat hard to connect. > >> > >>Did anyone figure a workaround ? > >> > >>Their support is useless : login(!), place a question, > >>relogin(!) to get a reply, so I didn't ask there.Article: 51251
I really appreciate to have the major vendors here. Hoping to have now at least one reader in charge : As much as like to use the web based support, I am discouraged. I do have to log in, giving name adress and so on plus a password. The next time, I lost the password, then I enter the name = street = whatever = aaaaa. The only correct entry is my email. Then I get a mail back : company does not match or alike, after a day or two. There are error description forms to be filled out (forgot which company) but the message is truncated after 160 characters. Common, this is not useable at all. There is not even an email adress as alternative means. I don't want yet another entry in a postal mailing list. I have my distributor here, we know each other, I get the advertisements, I'm fine. Whenever Analog devices sends out a (postal)mailing on DSP, mixed signal or whatever, I get it three times, because every time I loged into their site I created a new user (password lost). No, I cannot wait for a password recovery, the message has to go out immediately. Therefore the reason to be user 'aaa', street 'aaa', state 'ak', zip '12345' and so on, because they know me already. Match the email. The solution is simple : provide an email adress and get rid of this form crap. It is a waist of time and aggravates when it takes too long, beside that I do not have a copy like in email. Yes, I know a public email adress is a point of SPAM attack. But a filters are so easy. Just watch for keywords : If the message doesn't contain at least one of : FPGA, PLD, and so on, -> to the bin. Rene Austin Lesea wrote: > Rene, > > Please, do not discourage people from using internet based support tools. > > I can not speak for Altera (obviously), but email and web-based support is > becoming a major means of asking and answering customer questions in a timely > fashion. > > The fact that Altera has someone who watches the comp.arch.fpga forum indicates > that they really do care about customer service, and 'caught' your inquiry in this > forum. > > Our hotline group would prefer that a case gets entered into their system, as they > will answer it quicker that way. But for those that wish to get other opinions, > this newsgroup is also valuable. > > I know that Xilinx takes this all very seriously, and watches response time vs. > how the case is entered to maintain quality of service target levels. > > > > Austin > > Rene Tschaggelar wrote: > > >>Thanks for the quick reply. >>Amazingly quicker than the mentioned 'MySupport', >>but then again not - proves my point. >> >>Rene >> >>Subroto Datta wrote: >> >>>Rene, >>> A fix for this problem is under development. More details about its >>>availability will be posted as soon as the fix is tested and released in the >>>very near future (no later than end of this week). Thanks for bringing this >>>problem to our attention. >>> >>>- Subroto Datta >>>Altera Corporation >>> >>>"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message >>>news:3E1B4021.2090607@dplanet.ch... >>> >>> >>>>I found a bug in quartus2 Web V2.2. >>>>When tring to place legacy components in schematic editor, >>>>such as the 74165b shiftregister, its connectors are off >>>>grid. This makes it somewhat hard to connect. >>>> >>>>Did anyone figure a workaround ? >>>> >>>>Their support is useless : login(!), place a question, >>>>relogin(!) to get a reply, so I didn't ask there. >>> > -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51253
Care bust be taken with bi-directional data bus. For more info do a google search for bi-directional bus vhdl. Also check for metastability. Good luck. "tk" <tokwok@hotmail.com> wrote in message news:avh0tg$s1q$1@www.csis.hku.hk... > Hi all, > > In my design, it needs to transfer 64-bit data between the Spartan II and > the PC via a 8-bit bus. > When the PC reads the hard-coded data(initialized in code segment 1), it > works fine. The PC can > read the hard-coded data. However, when the PC writes data to the board, it > can't read back. The > storage part code is in code segment 2. In segment 2, in the two lines: > > data_store(counter2) := tmp_bit; > debug_data <= to_StdlogicVector(tmp_bit); > > the 8-bit debug_data is connected to the FPGA's I/O pins so that the data is > viewed using logic > analyzer. It's found that the 8-bit debug_data is the same as the data > written to the board by > the PC. So, it's sure that the tmp_bit do contain the input data, but I > don't know why the > data_sotre can't store it, and each time the PC reads all zero. > > I've got 5 warnings of the following type in Xinlinx ISE 4.2i: > WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net N217 is sourced > by a > combinatorial pin. This is not good design practice. Use the CE pin to > control the loading of data into the flip-flop. > > Will the problem be related to the warnings ? > > Thx for ur kind attention and help. > > tk > > -------------- > VHDL code > -------------- > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity data_tran is > Port ( PC_R_nW_buf : in std_logic; -- PC Read/(Write)' > PC_Rcv_nDS : in std_logic; -- PC Receive/(Data strobe)' > PC_INIT_buf : in std_logic; > data : inout std_logic_vector(7 downto 0); > D2_nDS : inout std_logic := '1'; > D2_nRcv : inout std_logic := '0'; > debug_data : out std_logic_vector(7 downto 0)); > end data_tran; > > > architecture Behavioral_data_tran of data_tran is > component IBUF > port ( I : in std_logic; > O : out std_logic); > end component; > > > signal PC_R_nW : std_logic; > signal PC_INIT : std_logic; > signal d_in : std_logic_vector(7 downto 0); > signal d_out : std_logic_vector(7 downto 0); > signal q : std_logic_vector(7 downto 0); > signal pcwe : std_logic; -- PC write enable > signal pcnre : std_logic; -- (PC read enable)' > signal tmp_bit : bit_vector(7 downto 0); > > begin > BUF1: IBUF port map(I => PC_R_nW_buf, O => PC_R_nW); > BUF2: IBUF port map(I => PC_INIT_buf, O => PC_INIT); > > process(PC_INIT, PC_R_nW, PC_Rcv_nDS) > type data_array is array (0 to 7) of bit_vector(7 downto 0); > > variable counter : integer range 0 to 7; > variable counter2 : integer range 0 to 7; > variable data_store : data_array; > > begin > if (PC_INIT = '1') then > -- code segment 1 start > -- data_store(0) := "00000001"; > -- data_store(1) := "00000010"; > -- data_store(2) := "00000100"; > -- data_store(3) := "00001000"; > -- data_store(4) := "00010000"; > -- data_store(5) := "00100000"; > -- data_store(6) := "01000000"; > -- data_store(7) := "10000000"; > -- code segment 1 end > > if (PC_R_nW = '1') then > counter := 0; > D2_nDS <= '1'; > pcwe <= '0'; > pcnre <= '0'; > elsif (PC_R_nW = '0') then > counter2 := 0; > D2_nRcv <= '1'; > pcwe <= '1'; > pcnre <= '1'; > end if; > end if; > > > if (PC_R_nW = '1') then > if (PC_Rcv_nDS = '1') then > D2_nDS <= '1'; > end if; > elsif (PC_R_nW = '0') then > if (PC_Rcv_nDS = '1') then > D2_nRcv <= '1'; > end if; > end if; > > if (PC_R_nW = '1' and PC_INIT = '0' > and PC_Rcv_nDS = '0' and D2_nDS = '1') then > > d_out <= to_StdlogicVector(data_store(counter)); > > if (counter = 7) then > counter := 0; > else > counter := counter + 1; > end if; > > D2_nDS <= '0'; > elsif (PC_R_nW = '0' and PC_INIT = '0' > and PC_Rcv_nDS = '0' and D2_nRcv = '1') then > > -- code segment 2 start > data_store(counter2) := tmp_bit; > debug_data <= to_StdlogicVector(tmp_bit); > -- code segment 2 end > > if (counter2 = 7) then > counter2 := 0; > else > counter2 := counter2 + 1; > end if; > > D2_nRcv <= '0'; > end if; > end process; > > > d_in <= data when pcwe = '1' else d_out; > q <= d_in; > data <= q when pcnre = '0' else "ZZZZZZZZ"; > > tmp_bit <= to_bitvector(d_in); > end Behavioral_data_tran; > >Article: 51254
Rene, Thanks for the feeedback. Since I do not use our own system, I will find out how hard we make folks work to report a problem. You make some good points, but I would caution you that the reason for the userid and password is so that you can review your own case at any time, to see where it is (you get to see your internal case notes this way). I am sure you would not like if your competitor saw your case notes.... Austin Rene Tschaggelar wrote: > I really appreciate to have the major vendors here. > Hoping to have now at least one reader in charge : > > As much as like to use the web based support, I am discouraged. > > I do have to log in, giving name adress and so on plus a password. > The next time, I lost the password, then I enter the name = > street = whatever = aaaaa. The only correct entry is my email. > Then I get a mail back : company does not match or alike, after > a day or two. > There are error description forms to be filled out (forgot > which company) but the message is truncated after 160 characters. > > Common, this is not useable at all. > There is not even an email adress as alternative means. > > I don't want yet another entry in a postal mailing list. > I have my distributor here, we know each other, I get the > advertisements, I'm fine. > > Whenever Analog devices sends out a (postal)mailing on DSP, mixed > signal or whatever, I get it three times, because every time I > loged into their site I created a new user (password lost). > No, I cannot wait for a password recovery, the message has to go > out immediately. > Therefore the reason to be user 'aaa', street 'aaa', > state 'ak', zip '12345' and so on, because they know me already. > Match the email. > > The solution is simple : provide an email adress and get rid of > this form crap. It is a waist of time and aggravates when it takes > too long, beside that I do not have a copy like in email. > > Yes, I know a public email adress is a point of SPAM attack. > But a filters are so easy. Just watch for keywords : > If the message doesn't contain at least one of : FPGA, PLD, > and so on, -> to the bin. > > Rene > > Austin Lesea wrote: > > Rene, > > > > Please, do not discourage people from using internet based support tools. > > > > I can not speak for Altera (obviously), but email and web-based support is > > becoming a major means of asking and answering customer questions in a timely > > fashion. > > > > The fact that Altera has someone who watches the comp.arch.fpga forum indicates > > that they really do care about customer service, and 'caught' your inquiry in this > > forum. > > > > Our hotline group would prefer that a case gets entered into their system, as they > > will answer it quicker that way. But for those that wish to get other opinions, > > this newsgroup is also valuable. > > > > I know that Xilinx takes this all very seriously, and watches response time vs. > > how the case is entered to maintain quality of service target levels. > > > > > > > > Austin > > > > Rene Tschaggelar wrote: > > > > > >>Thanks for the quick reply. > >>Amazingly quicker than the mentioned 'MySupport', > >>but then again not - proves my point. > >> > >>Rene > >> > >>Subroto Datta wrote: > >> > >>>Rene, > >>> A fix for this problem is under development. More details about its > >>>availability will be posted as soon as the fix is tested and released in the > >>>very near future (no later than end of this week). Thanks for bringing this > >>>problem to our attention. > >>> > >>>- Subroto Datta > >>>Altera Corporation > >>> > >>>"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > >>>news:3E1B4021.2090607@dplanet.ch... > >>> > >>> > >>>>I found a bug in quartus2 Web V2.2. > >>>>When tring to place legacy components in schematic editor, > >>>>such as the 74165b shiftregister, its connectors are off > >>>>grid. This makes it somewhat hard to connect. > >>>> > >>>>Did anyone figure a workaround ? > >>>> > >>>>Their support is useless : login(!), place a question, > >>>>relogin(!) to get a reply, so I didn't ask there. > >>> > > > > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 51255
Anyone know how to make a excees 3 counter with parallel load? I know how to make a binary counter with paralle load, but the excess-3 part is throwing me for a loop... excess three basically meanse to add 3 right?Article: 51256
yes i remember seeing the same note about using wine tryed it , it didnt work instaled win xp (that i found wasnt suported then eather) so had to wait for the updates and after some months XP crashed losing around 4Gb of data (dew to auto update and device drivers within XP) so im back with linux so how do i get the web pack and xilinx tools to work in linux as i can't do much without themArticle: 51257
I did a google search on "excess 3" and found that an excess 3 code is just a BCD code with 3 added. Rather than counting 0-9, one counts 3-12. You know how to do a binary counter, do you know how to do a BCD counter? If so, shift everything by 3. "needhelp" <needhelp@attglobal.net> wrote in message news:3e1cbc38_2@news1.prserv.net... > Anyone know how to make a excees 3 counter with parallel load? I know how to > make a binary counter with paralle load, but the excess-3 part is throwing > me for a loop... excess three basically meanse to add 3 right? > >Article: 51258
needhelp wrote: > Anyone know how to make a excees 3 counter with parallel load? I know how to > make a binary counter with paralle load, but the excess-3 part is throwing > me for a loop... excess three basically meanse to add 3 right? Yes, BCD excess3 is just offset by three, so zero is 0011, one is 0100 etc. With 4-input LUTs, you can any 4-bit coded counter you could imagine. Peter AlfkeArticle: 51259
Hello! Is there a small (no larger than 8mmx8mm) FPGA/EPLD that can support 4 or more differential LVPECL interfaces? Appreciate if any reader aware of such an FPGA/EPLD will post a reply with information. Regards DarshanArticle: 51260
Hi, all
I got a problem here
I have used synplify to synthesize my program, but i want to use
MaxplusII to place and route, can i reach it via setting the
parameters of MaxplusII?
thank you !
siriuswmx
Article: 51261Hi, Can anyone point me to some good references on using external RAM with FPGA's (specifically Spartan IIE). Would it be possible to implement using a schematic design (which I prefer)? Thanks AdrianArticle: 51262
Hi, Yes, this is the common way to do it. You should only check that MP2 supports the selected device. I myself usally do the other way around using native link in Quartus to run syntesis in the tool in the background and then doing PR. You also have the possibility to use the synthesis tool to compile down to a edif file and taking this file into the MP2 enviorment and doing PR. Cheers Fredrik wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0301081830.16cb1dfe@posting.google.com>... > Hi, all > I got a problem here > I have used synplify to synthesize my program, but i want to use > MaxplusII to place and route, can i reach it via setting the > parameters of MaxplusII? > > thank you ! > > siriuswmxArticle: 51263
Hello, Caleb Hess schrieb: > I think your problem will be that the Trenz board has the transceiver > mode pin unconnected (mode 1, for differential input on VPO/VMO) while > Usselmann's design produces single-ended output requiring mode 0. You > should be able to fix this by adding a kludge wire to ground from pin > 1 of the PDIUSBP11A chip. Don't do this. The mode pin is already connected to gnd, so the transceiver runs in mode 0. Our Documentation is wrong here (thank you for the hint) and we will fix it. This applies to both, TE-XC2Se and TE-BL from TE-XC2S. However you never need to add a wire to the board, as you can simply sort out such things in the fpga. best regards Thorsten -- Dipl.-Ing. Thorsten Trenz Trenz Electronic GmbH, Brendel 20, 32257 Buende, Germany Tel.: +49 (0) 5223 41652, Fax.: +49 (0) 5223 48945 Mailto:t.trenz@trenz-electronic.de, http://www.trenz-electronic.de Amtsgericht Bünde, HR B 1747, Geschäftsführer/CEO: Thorsten TrenzArticle: 51264
Hello!!
We want to buy a simulator. We`ve already worked with Modelsim and
with Xilinx ISE, but we are now thinking about buying Active-HDL.
On the one hand, we like the Xilinx ISE integrated EDA tool. We
would like to do the design flow with the Project Navigator in the
Xilinx ISE.
On the other hand, we would like to simulate with Active-HDL but
inside the design flow of the Project Navigator of Xilinx ISE.
We have several questions about this:
1-Is the Project Navigator in Xilinx ISE able to launch the
simulator Active-HDL as it launches the Modelsim simulator?
2-How could we import a Xilinx ISE project to the Active-HDL?In
this case we would have to create two projects, one per tool, wouldn`t
we?
3-If we want to work with a design flow in a integrated EDA tool
and with the Active-HDL simulator, we only have a possibility wich is
using the desing flow in Active-HDL, haven`t we?
THANKS A LOT!!!
ITSASO.
Article: 51265Thanks a lot for looking into the subject, there is indeed some advantage in having the messages protected from the competition. At least some of the messages. Couldn't the user decide that ? Most tiring is the nitpicking of some scripts : please supply state : ok, 'AK'(topmost) then. Some even more clever script then know that my country(not topmost) and Alaska do not belong together : wrong state. Or : Zip must have 5 digits (depends on country). All while my 166MHz mail revieving machine is chewing very hard displaying these scripts. Rene Austin Lesea wrote: > Rene, > > Thanks for the feeedback. Since I do not use our own system, I will find out how hard > we make folks work to report a problem. > > You make some good points, but I would caution you that the reason for the userid and > password is so that you can review your own case at any time, to see where it is (you > get to see your internal case notes this way). > > I am sure you would not like if your competitor saw your case notes.... > > Austin > > Rene Tschaggelar wrote: > > >>I really appreciate to have the major vendors here. >>Hoping to have now at least one reader in charge : >> >>As much as like to use the web based support, I am discouraged. >> >>I do have to log in, giving name adress and so on plus a password. >>The next time, I lost the password, then I enter the name = >>street = whatever = aaaaa. The only correct entry is my email. >>Then I get a mail back : company does not match or alike, after >>a day or two. >>There are error description forms to be filled out (forgot >>which company) but the message is truncated after 160 characters. >> >>Common, this is not useable at all. >>There is not even an email adress as alternative means. >> >>I don't want yet another entry in a postal mailing list. >>I have my distributor here, we know each other, I get the >>advertisements, I'm fine. >> >>Whenever Analog devices sends out a (postal)mailing on DSP, mixed >>signal or whatever, I get it three times, because every time I >>loged into their site I created a new user (password lost). >>No, I cannot wait for a password recovery, the message has to go >>out immediately. >>Therefore the reason to be user 'aaa', street 'aaa', >>state 'ak', zip '12345' and so on, because they know me already. >>Match the email. >> >>The solution is simple : provide an email adress and get rid of >>this form crap. It is a waist of time and aggravates when it takes >>too long, beside that I do not have a copy like in email. >> >>Yes, I know a public email adress is a point of SPAM attack. >>But a filters are so easy. Just watch for keywords : >>If the message doesn't contain at least one of : FPGA, PLD, >>and so on, -> to the bin. >> >>Rene >> >>Austin Lesea wrote: >> >>>Rene, >>> >>>Please, do not discourage people from using internet based support tools. >>> >>>I can not speak for Altera (obviously), but email and web-based support is >>>becoming a major means of asking and answering customer questions in a timely >>>fashion. >>> >>>The fact that Altera has someone who watches the comp.arch.fpga forum indicates >>>that they really do care about customer service, and 'caught' your inquiry in this >>>forum. >>> >>>Our hotline group would prefer that a case gets entered into their system, as they >>>will answer it quicker that way. But for those that wish to get other opinions, >>>this newsgroup is also valuable. >>> >>>I know that Xilinx takes this all very seriously, and watches response time vs. >>>how the case is entered to maintain quality of service target levels. >>> >>> >>> >>>Austin >>> >>>Rene Tschaggelar wrote: >>> >>> >>> >>>>Thanks for the quick reply. >>>>Amazingly quicker than the mentioned 'MySupport', >>>>but then again not - proves my point. >>>> >>>>Rene >>>> >>>>Subroto Datta wrote: >>>> >>>> >>>>>Rene, >>>>> A fix for this problem is under development. More details about its >>>>>availability will be posted as soon as the fix is tested and released in the >>>>>very near future (no later than end of this week). Thanks for bringing this >>>>>problem to our attention. >>>>> >>>>>- Subroto Datta >>>>>Altera Corporation >>>>> >>>>>"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message >>>>>news:3E1B4021.2090607@dplanet.ch... >>>>> >>>>> >>>>> >>>>>>I found a bug in quartus2 Web V2.2. >>>>>>When tring to place legacy components in schematic editor, >>>>>>such as the 74165b shiftregister, its connectors are off >>>>>>grid. This makes it somewhat hard to connect. >>>>>> >>>>>>Did anyone figure a workaround ? >>>>>> >>>>>>Their support is useless : login(!), place a question, >>>>>>relogin(!) to get a reply, so I didn't ask there.Article: 51266
"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:<1042095472.447551@skink.ru.ac.za>... > Hi, > > Can anyone point me to some good references on using external RAM with > FPGA's (specifically Spartan IIE). Would it be possible to implement using a > schematic design (which I prefer)? > > Thanks > > Adrian Me too, please :) I've got BurchED SpartanIIE board with 256K 15ns RAM (2x CY7C1018CV33). It works fine but up until now I have been over-cautious with RAM timing. Now I want to push it harder and I'm a little confused about getting timing constraints right. In particular how to provide safety margin when changing the direction of the data bus without wasting extra clock cycle. I have another related question about RAM arbiter (sp?). Most of my desing will run at 16 or 32MHz. I've got several modules including CPU, display controller, ADC etc, and they all need to access RAM. Some of them (ADC, display) have predictable RAM access patterns where deadline cannot be missed, others (CPU etc) can be put into wait state at the expense of performance. I'm thinking about FIFOs, semaphores, priorities and the whole thing seems messy and complicated. I'm sure people have been through this before. I appreciate any suggestions. Thanks, DmitriArticle: 51267
Hi All The problem: The Stratix devices are not functioning after power-up. Symptom: 15A power-up current in the 1.5V power supply. Details: We just assembeled a board with three EP1S25F1020C6ES. During power-up, the Stratix device consume about 15A current for 20ms. It causes the power supply to raise its voltage to 2.8V. We had the Stratix device for about 2 month in our stock, so I belive they are engineering samples (ES suffix). The Stratix devices are the only ones that are connected to the 1.5V power supply. The power comes from external LAB power-supply with 10mm diameter cables. If the power supply is tuned to 1.8V then the stratix devices are waking correctly, then we set it to 1.5V. Did anyone encounter this problem?. Any suggetions ? kind regards AlonArticle: 51268
John_H wrote: > > I did a google search on "excess 3" and found that an excess 3 code is just > a BCD code with 3 added. Rather than counting 0-9, one counts 3-12. > > You know how to do a binary counter, do you know how to do a BCD counter? > If so, shift everything by 3. > > "needhelp" <needhelp@attglobal.net> wrote in message > news:3e1cbc38_2@news1.prserv.net... > > Anyone know how to make a excees 3 counter with parallel load? I know how > to > > make a binary counter with paralle load, but the excess-3 part is throwing > > me for a loop... excess three basically meanse to add 3 right? > > > > To do the excess 3 counter you just use a loadable binary counter. Detect the end count and use that to enable a load of the first count on the next clock. Anyone remember why an excess 3 counter is used? I very, very vaguely remember learning about this in school many, many years ago. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51269
"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:<1042095472.447551@skink.ru.ac.za>... > Hi, > > Can anyone point me to some good references on using external RAM with > FPGA's (specifically Spartan IIE). Would it be possible to implement using a > schematic design (which I prefer)? Xilinx has a number of app notes on their web site for interfacing to external memory. If I had a choice, I'd use ZBT (same as NBT or NoBL) SRAM. Just delay the data a few cycles after the address and you're done. Well, and mux read and write since it is single port. If that is a concern, pick one of the several SRAM styles have have separate read and write ports. Almost anything is possible to implement using a schematic tool. MarcArticle: 51270
Itsaso Zuazua wrote: > Hello!! > > We want to buy a simulator. We`ve already worked with Modelsim and > with Xilinx ISE, but we are now thinking about buying Active-HDL. > > On the one hand, we like the Xilinx ISE integrated EDA tool. We > would like to do the design flow with the Project Navigator in the > Xilinx ISE. > > On the other hand, we would like to simulate with Active-HDL but > inside the design flow of the Project Navigator of Xilinx ISE. > > We have several questions about this: > > 1-Is the Project Navigator in Xilinx ISE able to launch the > simulator Active-HDL as it launches the Modelsim simulator? no > 2-How could we import a Xilinx ISE project to the Active-HDL?In > this case we would have to create two projects, one per tool, wouldn`t > we? yes, you have to create a project for ISE, implement you design and then run "Generate Post-Place & Route Static Timing". This generates 2 files: your_design_timsim.v and your_design.sdf Then create an Active-HDL project and add these 2 files. Set accordingly the Timing simulation Options (you must also add manually the glbl.v) > 3-If we want to work with a design flow in a integrated EDA tool > and with the Active-HDL simulator, we only have a possibility wich is > using the desing flow in Active-HDL, haven`t we? > yes, but you loose some of the "knobs" of ISE. I have used Acvtive-HDL for 1 year, it's ok but I find Aldec a little slow/clumsy at providing models for the features of the new devices. The tech support is preatty fast. - Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 51271
Alon Z wrote: > Hi All > > The problem: The Stratix devices are not functioning after power-up. > Symptom: 15A power-up current in the 1.5V power supply. > > Details: > We just assembeled a board with three EP1S25F1020C6ES. During > power-up, the Stratix device consume about 15A current for 20ms. It > causes the power supply to raise its voltage to 2.8V. > We had the Stratix device for about 2 month in our stock, so I belive > they are engineering samples (ES suffix). > The Stratix devices are the only ones that are connected to the 1.5V > power supply. > The power comes from external LAB power-supply with 10mm diameter > cables. > > If the power supply is tuned to 1.8V then the stratix devices are > waking correctly, then we set it to 1.5V. > > Did anyone encounter this problem?. Any suggetions ? > I'm in the process of doing it. I was told the engineering samples are known for these high starting currents. I was told the smallest, the S10 takes 2.5Amps, and assume the bigger one take more. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51272
Please note that v2.1i XSE only provides support for FPGAs up to 150K gates. The full version would be required to target 800K gate Virtex device. Xilinx does not recommend porting a design from a newer version of software to an older version. As such, I would suggest that you have your Professor submit a donation request at university.xilinx.com to obtain the latest version of ISE for the engineering lab. Hope this helps! JeffArticle: 51273
Hi, I am trying to create a simple 16 bit CPU with 4 PIOs for LEDs. (This is on a custom board, not the Excalibur dev board). I have a small C program that does a binary count on the LEDs. I can't seem to get this to work. I've tried all sorts of combinations: a) ROM (preloaded with code) PIO b) ROM (preloaded with code) RAM PIO c) RAM (preloaded with code) PIO Nothing seems to work. What is the correct technique? The board I'm using does not have debugging capabilities and so I can't use the GERMS monitor. Any ideas? I know the PCB works because I made a simple combinatorial design to do the same thing and it works.... it's just NIOS I can't get to work. Jon JacoxArticle: 51274
> > The mode pin is already connected to gnd, so the transceiver runs in > mode 0. Our Documentation is wrong here (thank you for the hint) and we > will fix it. > This applies to both, TE-XC2Se and TE-BL from TE-XC2S. > > However you never need to add a wire to the board, as you can simply > sort out such things in the fpga. > > best regards > Thorsten Hello, I am using a TE-XC2S system. Could you please tell me exactly what is wrong in the TE-BL documentation? The MODE pin is shown to be connected to ground. What is exactly the problem and how should it be solved on FPGA side? Yours, FB
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