Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Utku Ozcan <utku.ozcan@netas.com.tr.spamela> wrote in message news:<3EDB13E8.A51C06D4@netas.com.tr.spamela>... > I'm in the same opinion Neeraj does. SDH implementations in FPGAs require > good FPGA engineering, especially at higher rates. I had been involved > for an STM-16 mapper device to be implemented in XCV2000E 2 years ago > and the design required extremous routing resources. > > The point is that OSI-layer 1 protocols like SDH require huge monitoring > functions. The protocol implementation is not a big issue. But payload > mappings are complex, alarm monitoring and other trace buffers require > enormous FPGA area (RAM mostly) + routing. > > You must think about which functions are necessary. Unnecessary functions > must be dropped out of design. > > A high-tech additional FPGA engineer is a must to map the design into an > FPGA technology. It is not easy to meet timing constraints SDH protocol > requires. > > Utku I agree with you that framing is a minor part of SONET/SDH compared to monitoring, mapping, and pointer processing. But meeting timing for such functions is completely a dependant of the coding style. IE, there is no reason that meeting timing has to be difficult. Just pipeline, pipeline, pipeline! After all, for functions like these, flops are free compared to LUTs. MarcArticle: 56276
Hmm, Not sure you can get it anymore if you don't already have it. Ask
your FAE for a copy. No, I don't believe 5.2 supports the Spartan I's. The
problem with 4.2's router is it makes every path a critical path, so although
you can see which path(s) fail timing, fixing those may not fix the
underlying problem.
email_address@message.end wrote:
> Ray,
>
> What is v3.3sp8, and how do I get it?
>
> I can't use ISE-5.2 with a 5V Spartan, can I?
>
> Thanks,
> Gary.
>
> On Sun, 01 Jun 2003 21:59:04 GMT, Ray Andraka <ray@andraka.com> wrote:
>
> >Use v3.3 sp8 instead. The router in 4.x is lazy. FWIW, I've had some
> >good results so far with 5.2 sp3. Seems Xilinx has fixed many of the
> >problems I saw with the 4.2 router (Thank you).
> >
> >email_address@message.end wrote:
> >
> >> Hi all,
> >>
> >> Xilinx ISE is giving me fits. I could swear that it hates me! This
> >> is version 4.2i, by the way. Version 5 does not support the part I'm
> >> using.
> >>
> >> Here's what's happening:
> >>
> >> The design is very close to -not- meeting the speed requirement, which
> >> is 50 MHz.
> >>
> >> If, when ISE runs, it does 'improving timing' passes, the speed comes
> >> out at 50.314 MHz. If it does not run these passes, I get 47.246
> >>
> >> The problem is, I can't figure out how to get it to run these passes!
> >> Some times it does, some times it doesn't. The help file tells me to
> >> check an option box, but that box doesn't exist!
> >>
> >> Please, how do I turn this option on? Right now, ISE is stuck in the
> >> mode where it does not run these cleanup passes. :(
> >>
> >> And, if someone has a tutorial-like document for guiding place and
> >> route, I would like to see it. Basically, I want to 'suggest' to P&R
> >> that certain (Verilog) modules belong in certain haves of the chip.
> >>
> >> Much Appreciated,
> >> Gary
> >> gwhelbig-at-yahoo-dot-com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56277Rick, Actually, the bonuses were good, the profit sharing adequate, and the fact that we had 0 layoffs, quite pleasant. Who else can say that they were: profitable, kept all of those inventive people happy, made lots of useful products for lots of customers (and sold them profitably), had no layoffs, and improved customer services, and introduced new products besides? No one. Sorry. Cheap shot on your part. But Peter is correct: the market decides, and it has voted overwhelming for our solutions. Austin rickman wrote: > Peter Alfke wrote: > > > > Then we have to ask ourselves: > > Why are all these companies so small and/or doing so poorly? > > The market is the final arbiter. Success in this industry is defined by > > a profitably growing sales volume... > > I remember a time when Xilinx stock was over 90. Last time I checked it > was still below 30. I bet there are some very unhappy investors out > there still. > > How was *your* bonus last year? ;) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56278
Luiz, As for the speed, one has to design to balance leakage current, and speed with the latest technologies. There is a larger market for a Spartan 3 that is less fast enough, and less power, than for a Spartan 3 that is really fast, and has more power. Also, if you want the speed, there is Virtex II Pro. Austin Luiz Carlos wrote: > XILINX website posts that MicroBlaze runs at: > 150MHz in Virtex2-PRO (-7) using 950 logic cells, > 125MHz in Virtex2 (-5) using 950 logic cells, > 85MHz in Spartan3 (-4) using 1050 logic cells, > 75MHz in Spartan2E (-7) using 1050 logic cells. > > Well, Virtex2-PRO uses 130nm technology, Virtex2 and Spartan2E use > 150nm, and Spartan3 uses 90nm. > As far as I know, Virtex2 doesn't use strained silicon, silicon on > insulator or low K dieletrics. > And finally, Spartan3 is based on Virtex2 architecture. > > So: > Why is Spartan3 slowly than Virtex2? (Very slowly!) > Why does Microblaze takes 1050 locic cells in a Spartan3? (Same as in > Spartan2!) > > Luiz Carlos > KHOMP SolutionsArticle: 56279
Hi, The reason is simple. MicroBlaze is using the primitive RAM32x1d which only exists in VII and VII-Pro. In the other architectures I have to create that primitive using RAM16x1d and multiplexors. The extra area is coming from these multiplexors. Göran Bilski Amontec Team wrote: > Luiz Carlos wrote: > > XILINX website posts that MicroBlaze runs at: > > 150MHz in Virtex2-PRO (-7) using 950 logic cells, > > 125MHz in Virtex2 (-5) using 950 logic cells, > > 85MHz in Spartan3 (-4) using 1050 logic cells, > > 75MHz in Spartan2E (-7) using 1050 logic cells. > > > > Well, Virtex2-PRO uses 130nm technology, Virtex2 and Spartan2E use > > 150nm, and Spartan3 uses 90nm. > > As far as I know, Virtex2 doesn't use strained silicon, silicon on > > insulator or low K dieletrics. > > And finally, Spartan3 is based on Virtex2 architecture. > > > > So: > > Why is Spartan3 slowly than Virtex2? (Very slowly!) > > Why does Microblaze takes 1050 locic cells in a Spartan3? (Same as in > > Spartan2!) > > > > Luiz Carlos > > KHOMP Solutions > > You can find a answer in the logic cell numbers : > If a combinatory pass is routed using 2 or 3 more logic cell levels for > spartan3, so your system clock will be some 10 ns bigger. > Microblaze maybe was designed for virtex2 architecture and not for > Spartan3. Maybe ? > > You have to think ARCHITECTURE ! > > Laurent Gauch > Amontec Team > www.amontec.com > > ------------ And now a word from our sponsor ------------------ > Do your users want the best web-email gateway? Don't let your > customers drift off to free webmail services install your own > web gateway! > -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 56280
Ray, Spartan goes for the low leakage, moderate performance, and Virtex goes for the higher speeds, and a little more leakage. If we went "whole hog" we could be like Intel, with 50% of the power in DC leakage. Austin Ray Andraka wrote: > There is a also a leakage current which is the static portion of the power > dissipation. There is a tradeoff for leakage current vs speed, and in the case > of the FPGA vendoers, speed is king. > > Glen Herrmannsfeldt wrote: > > > The tradition of CMOS is that it only consumes power changing state. During > > a change both transistors are partially on, resulting in current flow, and > > also charging/discharging of the load capacitance of the metalization > > layers. This may be less true as density increases, but as far as I know > > it is still true. Some devices spec. the power consumption as proportional > > to clock frequency. > > > > -- glen > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 56281
> But when I want to access to the Nios microprocessor directly from my > NDK Shell, I push the SW4 button while I reset the board as it appears > in the manual, but it doesn't work. > > I don't know why, but it only works with the tutorial applications > such as "standard 32", etc... Button MUST be connected to specific port & address (look into GERMS surce). In other words, GERMS is checking SW4 pin state through specific PIO. You must make this PIO with correct address in SOPC-Builder. Hope this helps. -- jerry "The day Microsoft makes something that doesn't suck is probably the day they start making vacuum cleaners." - Ernst Jan PluggeArticle: 56282
Ray, I only saw a link to 5.2i sp2 on the Xilinx website. - Newman Ray Andraka <ray@andraka.com> wrote in message news:<3EDA783F.170F47BD@andraka.com>... > Use v3.3 sp8 instead. The router in 4.x is lazy. FWIW, I've had some > good results so far with 5.2 sp3. Seems Xilinx has fixed many of the > problems I saw with the 4.2 router (Thank you). > > email_address@message.end wrote: > > > Hi all, > > > > Xilinx ISE is giving me fits. I could swear that it hates me! This > > is version 4.2i, by the way. Version 5 does not support the part I'm > > using. > > > > Here's what's happening: > > > > The design is very close to -not- meeting the speed requirement, which > > is 50 MHz. > > > > If, when ISE runs, it does 'improving timing' passes, the speed comes > > out at 50.314 MHz. If it does not run these passes, I get 47.246 > > > > The problem is, I can't figure out how to get it to run these passes! > > Some times it does, some times it doesn't. The help file tells me to > > check an option box, but that box doesn't exist! > > > > Please, how do I turn this option on? Right now, ISE is stuck in the > > mode where it does not run these cleanup passes. :( > > > > And, if someone has a tutorial-like document for guiding place and > > route, I would like to see it. Basically, I want to 'suggest' to P&R > > that certain (Verilog) modules belong in certain haves of the chip. > > > > Much Appreciated, > > Gary > > gwhelbig-at-yahoo-dot-com > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 56283
parallel_case is used to tell the synthesis tool that it needn't worry about
priority of one case item over another because they are exclusive by design.
Consider this potential RTL code for a one-hot state machine:
case (1'b1) // parallel_case
R_state[0] : do_something;
R_state[1] : do_something_else;
R_state[2] : do_another_thing;
endcase
I know that by design, only one bit of my R_state vector will ever be hot. The
synthesis tool, however, doesn't know this and will build a priority decoder
unless I tell it that the cases are exclusive (parallel).
If the case statement itself is exclusive, i.e.
case (R_state[1:0])
2'b00 : do_something;
2'b01 : do_something_else;
default : do_another_thing;
endcase
then no parallel_case directive is needed. There is another directive called
infer_mux that can be used if the target technology library contains multiplexor
cells that the synthesis tool will not infer by default. It can be used to force
the tool to use these mux cells rather than building a mux out of gates, which
may or may not be desireable depending on your synthesis objectives.
Mark
Muthu wrote:
> Hi,
>
> What is the need for Parallel_case directive.
>
> I know that, it is to infer a MUX for case statement rather if/else.
>
> But, isn't implied that case statement itself a MUX?
>
> If so, why this synthesis directive again?
>
> Am i missing anything?
>
> Regards,
> Muthu
Article: 56284"Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag news:3EDB6220.5E6F03FE@xilinx.com... > If we went "whole hog" we could be like Intel, with 50% of the power in DC leakage. ??? Sure? You mean, all those Pentiums -III/IV/whatever to come burn 50% of their power, eben if the clock is disabled?? Hmm, one more reason for the californian power crisis, I guess . . .;-) -- MfG FalkArticle: 56286
I was wondering if anyone could give me a pointer to find some comparative study of latest FPGAs. I am particularly interested in evaluation Virtex II Pro - against its industry equivalents. Thanks in advance.Article: 56287
email_address@message.end wrote in message news:<sjmkdvo9n34acge8qne98kh6dsbundm8up@4ax.com>... > Hi all, > > Xilinx ISE is giving me fits. I could swear that it hates me! This > is version 4.2i, by the way. Version 5 does not support the part I'm > using. > > Here's what's happening: > > The design is very close to -not- meeting the speed requirement, which > is 50 MHz. > > If, when ISE runs, it does 'improving timing' passes, the speed comes > out at 50.314 MHz. If it does not run these passes, I get 47.246 > > The problem is, I can't figure out how to get it to run these passes! > Some times it does, some times it doesn't. The help file tells me to > check an option box, but that box doesn't exist! > > Please, how do I turn this option on? Right now, ISE is stuck in the > mode where it does not run these cleanup passes. :( > > And, if someone has a tutorial-like document for guiding place and > route, I would like to see it. Basically, I want to 'suggest' to P&R > that certain (Verilog) modules belong in certain haves of the chip. > > Much Appreciated, > Gary > gwhelbig-at-yahoo-dot-com Create a User Constaint File and set the 50MHz clock period constraint to 20 ns. Add the UCF to the Implement properties. Bill HannaArticle: 56288
I have one of the Memec eval boards, it should have what you need: http://www.memec.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=DESIGN&Reg=GENERICA&Country=XILINXCT&Lang=EN&isDetailPage=true&EDOID=204265&Manu=MD_XILINX About $700 US if I remember correctly. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Bram van de Kerkhof" <bvdknospam@oce.nl> wrote in message news:1054561920.762580@news-ext.oce.nl... > Hello, > > I'm looking for an evaluation board of the Virtex 2 (actually for the > Spartan 3 but as there are none available i will have to verify on the > Virtex 2) > I want to verify a ddr-sdram and 300 Mb's lvds link design. Two avaluation > boards is also ok (one for ddr and one for lvds). > > Who has some idea's ? > > Yours Bram > > -- > ================================================== > Bram van de Kerkhof > > OCE-Technologies BV > Building 3N38 > > St. Urbanusweg 43, > Venlo, The Netherlands > P.O. Box 101, 5900 MA Venlo > ================================================== > Direct dial : +31-77-359 2148 > Fax : +31-77-359 5473 > ================================================== > e-mail : mailto:bvdk@oce.nl > ================================================== > www : http://www.oce.nl/ > ================================================== > >Article: 56289
Rick, that's a cheap shot. The whole industry is down... But at least we did not lay off anybody, unlike some of our competitors. I was not gloating, just pointing out that there must be a fly in the ointment with all those glorious technologies that were mentioned. Peter Alfke ===================== rickman wrote: > > > I remember a time when Xilinx stock was over 90. Last time I checked it > was still below 30. I bet there are some very unhappy investors out > there still. > > How was *your* bonus last year? ;) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56290
Marc, if you know how to compress Xilinx bitstreams by a factor 20 or 30, please tell us. The best I have seen is a factor 2 or 3 for a reasonably used FPGA. Peter Alfke =========== jetmarc wrote: > > > The other problem, is that a little flash ram is not so little: 2.5 > > Mbytes. > > Why don't FPGA chips support compressed bitstreams? > > I recently did a such a thing in software (on a self-reconfiguring SoC). > The original bitstreams were in the range of 500 kbytes, and compressed > down to only 16-25 kbytes. I left out all framing information and then > used LZ77 and Huffman encoding. About 200 bytes of assembler code are > necessary to reconstruct the original bitstream. > > Now that FPGAs even DES-encrypt their bitstreams, one should really > think they have enough resources to support compression, too! > > MarcArticle: 56291
Followup to: <3EDAE3D1.D3C52713@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > So in summary, you consider firmware/software to be *any* alteration of > any form that can be performed on hardware as long as it is not > permanent, right? > > Where do you draw the line between software/firmware and simple > programming of registers? Many application specific, standard product > (ASSP) chips do pretty much nothing until they are setup by configuring > the various registers in the chips. This is not a lot different from > the typical sort of software/firmware that is programmed into a CPLD or > even a flash MCU. I have seen ASSP chips that have a manual on usage > that is easily as large as an MCU. > > How do you distinguish ASSP chips from FPGAs in regards to the > programming? Is the configuration of ASSP chips also called > software/firmware? > Yes, and that is not just me, either. In fact, a lot of these kinds of chips require the driver to upload firmware, which sometimes trigger copyright concerns. This is a common discussion topic on the Linux Kernel mailing list, and it's *always* referred to as firmware. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 56292
emanuel stiebler wrote: > But, anybody out here has an idea, why there is no bitstream encryption > on the spartan 3 ? With all this gates & memory, you could do impressive > designs, but to keep them for safe you still have to go to the virtex > chips ... It's really quite simple: The priorities for Spartan are: Low cost first, features and speed second. For Virtex the priorities are reversed. Makes a lot of sense, avoids unproductive overlap, and gives the user a fair choice. Cheap or fancy. There is no free lunch... Now, if encryption were a popular feature in the low-cost market (please tell us), then it would make sense to dedicate some silicon and a pin for the on-chip decryption. Peter AlfkeArticle: 56293
Earlier WebPacks are available at: <http://support.xilinx.com/webpack/classics/wpclassic/index.htm> 3.3sp8 is the earliest available there. To answer your original question about needing a checkbox that "isn't there": In Project Navigator, select the menu item Edit/Preferences. When the dialog box appears, select the tab labeled "Processes". Change "Property Display Level" to "Advanced" and hit the "OK" button. The checkboxes you need should now be visible. (I had the same problem, and it took a call to Xilinx support to figure it out. That trick is not in the documentation anywhere.)Article: 56294
Well, Pentiums (or should educated people say Pentia ?) usually do not stall their clocks, so the leakage current remains camouflaged under the dynamic power... And please no jokes about the California power crisis of 2 years ago. That was not due to lack of power, but due to greedy managers/manipulators and stupid politicians... Peter Alfke ==================== Falk Brunner wrote: > > "Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag > news:3EDB6220.5E6F03FE@xilinx.com... > > > If we went "whole hog" we could be like Intel, with 50% of the power in DC > leakage. > > ??? > Sure? > You mean, all those Pentiums -III/IV/whatever to come burn 50% of their > power, eben if the clock is disabled?? > Hmm, one more reason for the californian power crisis, I guess . . .;-) > > -- > MfG > FalkArticle: 56295
I've been trying to construct some RPM's in VHDL (thanks to Ray Andraka for inspiration!).
The problem I'm having comes when I try to do a functional simulation in ModelSim.
ModelSim doesn't like the "BEL" constraint. I get errors like the following:
# WARNING[10]: m2s.vhd(139): Making two objects with the name "bel" directly visible via use clauses results in a conflict, neither object is made directly visible.(LRM Section 10.4)
# ERROR: m2s.vhd(139): Attribute bel has not been declared.
The line numbers refer to lines like this:
attribute BEL of m2s_LUT : label is bel_luts(bel_i);
What I /think/ is going on is that the attribute name "BEL" conflicts with name of the character 'bel' (seventh character in the enumerated type "character").
Type "character" is part of the "std" library which is (by definition!) always loaded.
I would think these names should be in separate namespaces, but ModelSim apparently thinks otherwise, and quotes the VHDL Language Reference Manual ("LRM Section 10.4") in its error
message to prove its point.
Xilinx XST seems to treat these as
separate namespaces, and doesn't notice a conflict.
So what can I do about this?
I can't rename the attribute, because then the Xilinx mapper won't recognize the constraint.
I could move the BEL constraint from the VHDL source to a UCF file -- but I've been trying very very hard to move all the constraints to VHDL for portability, and that would be a step
backwards.
I can't rename the character 'bel',
because it's part of the IEEE standard (and probably a mil-spec to boot). It's also the historic ASCII name for that character, and changing it would confuse a lot of people.
I can give up functional simulation, and just rely on post-PAR simulation. I'd rather not do that, because I'm depending on functional simulation to debug some of my more complex RPM macros,
which disappear after synthesis.
If the problem were with XST and not Modelsim, I could surround the offending lines with "-- synthesis translate_off" constructs. But instead I have lines that XST needs to see and ModelSim
needs to ignore. Is there a "-- modelsim translate_off" construct?
The best solution I can think of is for Xilinx to provide an additional constraint named, say, "XBEL", that works the same way as the existing BEL constraint. But for that, I'd have to wait for Xilinx
to agree and then implement it.
Any suggestions for what to do in the meantime?
Cheers!
--Stu
Article: 56296
Hi Stu,
You may want to make sure you've declared BEL type.
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0050_11.html
Regards, Wei
============================================================
VHDL
Before using BEL, declare it with the following syntax:
attribute bel : string;
After BEL has been declared, specify the VHDL constraint as
follows:
attribute bel of {component_name|label_name}: {component|label} is
{F|G|FFX|FFT|XORF|XORG}”;
Stewart Cobb wrote:
> I've been trying to construct some RPM's in VHDL (thanks to Ray
> Andraka for inspiration!).
>
> The problem I'm having comes when I try to do a functional simulation
> in ModelSim.
> ModelSim doesn't like the "BEL" constraint. I get errors like the
> following:
>
> # WARNING[10]: m2s.vhd(139): Making two objects with the name "bel"
> directly visible via use clauses results in a conflict, neither object
> is made directly visible.(LRM Section 10.4)
> # ERROR: m2s.vhd(139): Attribute bel has not been declared.
>
> The line numbers refer to lines like this:
>
> attribute BEL of m2s_LUT : label is bel_luts(bel_i);
>
> What I /think/ is going on is that the attribute name "BEL" conflicts
> with name of the character 'bel' (seventh character in the enumerated
> type "character").
> Type "character" is part of the "std" library which is (by
> definition!) always loaded.
> I would think these names should be in separate namespaces, but
> ModelSim apparently thinks otherwise, and quotes the VHDL Language
> Reference Manual ("LRM Section 10.4") in its error message to prove
> its point.
>
> Xilinx XST seems to treat these as
> separate namespaces, and doesn't notice a conflict.
>
> So what can I do about this?
>
> I can't rename the attribute, because then the Xilinx mapper won't
> recognize the constraint.
>
> I could move the BEL constraint from the VHDL source to a UCF file --
> but I've been trying very very hard to move all the constraints to
> VHDL for portability, and that would be a step backwards.
>
> I can't rename the character 'bel',
> because it's part of the IEEE standard (and probably a mil-spec to
> boot). It's also the historic ASCII name for that character, and
> changing it would confuse a lot of people.
>
> I can give up functional simulation, and just rely on post-PAR
> simulation. I'd rather not do that, because I'm depending on
> functional simulation to debug some of my more complex RPM macros,
> which disappear after synthesis.
>
> If the problem were with XST and not Modelsim, I could surround the
> offending lines with "-- synthesis translate_off" constructs. But
> instead I have lines that XST needs to see and ModelSim needs to
> ignore. Is there a "-- modelsim translate_off" construct?
>
> The best solution I can think of is for Xilinx to provide an
> additional constraint named, say, "XBEL", that works the same way as
> the existing BEL constraint. But for that, I'd have to wait for Xilinx
> to agree and then implement it.
>
> Any suggestions for what to do in the meantime?
>
> Cheers!
> --Stu
Article: 56297ModelSim support has returned to HDLmaker as of version 6.6.1. HDLmaker is an open source Verilog/VHDL hierarchical code generator for FPGAs and ASICs. HDLmaker is available free of charge from Polybus Systems at http://www.polybus.com/hdlmaker/users_guide/Article: 56298
> > But when I want to access to the Nios microprocessor directly from my > NDK Shell, I push the SW4 button while I reset the board as it appears > in the manual, but it doesn't work. > > I don't know why, but it only works with the tutorial applications > such as "standard 32", etc... > > Does anybody know the reason of this strange situation? Hi, The reasoning behind this is that GERMS is programmed with some conditional compilation statements that check to see if you have a peripheral named "button_pio" in the design - the "standard" reference designs interfaces to the dev. board buttons are named this way. Without naming your button interface "button_pio", GERMS has no way of knowing which address to look at to determine if a switch is open or closed. You might also check the wiring of your switches... on the dev boards, the switches are pulled up to Vcc when open, and shorted to ground when closed... the GERMS code, therefore, will be looking for logic 0 on bit 3 (SW4 on the board) of your PIO peripheral to see if your button has been "pressed". Hope this helps! Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 56299
On Mon, 2 Jun 2003 15:52:00 +0200, "Bram van de Kerkhof" <bvdknospam@oce.nl> wrote: >I'm looking for an evaluation board of the Virtex 2 (actually for the >Spartan 3 but as there are none available i will have to verify on the >Virtex 2) >I want to verify a ddr-sdram and 300 Mb's lvds link design. Two avaluation >boards is also ok (one for ddr and one for lvds). > >Who has some idea's ? >Yours Bram You might want to have a look at: http://www.fpga-faq.com/FPGA_Boards.shtml =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COM
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z