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Dr. Anton Squeegee wrote: <snip> > Here's my recommendation for you. Poke around at whatever ham > radio/electronic swap meet(s) or electronic surplus places > are local to you, and on Ebay as well, for an older Tektronix > or HP logic analyzer. I think you'll find that a > dedicated-purpose instrument will be a much better choice, and > the older stuff is plenty cheap. <snip> The equipment has to meet the testing requirements, of course; and, given that, I look for low cost and portability. I like that my Ant8 and associated software (on a business card CD) can live in my attache case when I visit clients. For stationary (or more demanding) use I think your suggestion is excellent. -- Morris Dovey West Des Moines, Iowa USA C links at http://www.iedu.com/cArticle: 56526
"Dr. Anton Squeegee" wrote: > > In article <3ee1cb35$0$54853$a726171b@news.hal-pc.org>, "QBA" <bwang<AT> > hal-pc<DOT>org> says... > > > Looking for a logical anayzer (a pod connected to a PC via USB or printer > > port), Any recommendations? > > I have to say that I'm constantly amazed by the (apparently) > broadly-held misconception that the PC is the answer to so many test > equipment needs. > > One thing before I start; I'm venturing into territory I don't > often use. I would appreciate corrections from others in the group if I > screw something up. Yes, this becomes appearant as your comments are read. > Anyway: The maximum possible bandwidth for a USB port is 12Mb/s > (that's megaBITS, not bytes). Dividing that by 8 (assuming 8 bits per > byte) gives us 1.5 megaBYTES per second, which (for the sake of > discussion) can be considered equivalent to 1.5 MHz. You are thinking of USB full speed operation. USB high speed operation is 480 Mb/s or 60 MB/s. > This means that, if you assume a bus width of 8 bits being > monitored simultaneously (most logic analyzers I've seen are parallel- > input devices), your USB-connected "pod" would top out at 1.5 MHz, or > just a bit more than 1/100th the speed of a typical PC's microprocessor > clock. These two things are unrelated. All logic analyzers operate by capturing the sampled data into a buffer. The sampling stops some number of counts after a trigger condition. This trigger is also handled in the hardware of the analyzer. > The parallel port? Assuming a high-end (read: not something you > find on a typical motherboard) dedicated parallel port card on the PCI > bus, your top end would be around 3-5 MHz. A little better than USB, but > still pathetic in terms of what a dedicated analyzer can do. Again, not relevant. The speed of the interface controls the time required to display the data captured, it does not limit the capture rate. > Here's my recommendation for you. Poke around at whatever ham > radio/electronic swap meet(s) or electronic surplus places are local to > you, and on Ebay as well, for an older Tektronix or HP logic analyzer. I > think you'll find that a dedicated-purpose instrument will be a much > better choice, and the older stuff is plenty cheap. This is true, but you will also find that the affordable units are very large and clumsy. Modern devices are much smaller, even the ones with built in displays. But you will pay thousands for any of them unless you get the small units that use the PC for control and display which is what you are saying are "limited". > For Tektronix, check around for a 1240 or 1241 series. Even with > the low-speed cards, they're good to at least 50MHz. With the high-speed > cards, they're good to 100. > > For HP, the late-model 16xxx series would probably do just fine. > > Good hunting. > > -- > Dr. Anton Squeegee, Director, Dutch Surrealist Plumbing Institute. > (Known to some as Bruce Lane, KC7GR, Owner and Head Hardware Heavy, > Blue Feather Technologies -- http://www.bluefeathertech.com) > kyrrin a/t bluefeathertech dot c=o>m (Reassemble to use). > "Raf tras spintern. Raf tras spoit." (Keith Laumer, "The Galaxy > Builder") You might want to do a little reading on your own before offering uninformed opinions. Please don't take that as a "flame". I am mearly suggesting that you limit your posts to things you are more familiar with. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56527
"Dr. Anton Squeegee" wrote: > "QBA" <bwang<AT> hal-pc<DOT>org> says... > > > Looking for a logical anayzer (a pod connected to a PC via USB > > or printer port), Any recommendations? > > I have to say that I'm constantly amazed by the (apparently) > broadly-held misconception that the PC is the answer to so many > test equipment needs. > > One thing before I start; I'm venturing into territory I don't > often use. I would appreciate corrections from others in the group > if I screw something up. > > Anyway: The maximum possible bandwidth for a USB port is 12Mb/s > (that's megaBITS, not bytes). Dividing that by 8 (assuming 8 bits > per byte) gives us 1.5 megaBYTES per second, which (for the sake > of discussion) can be considered equivalent to 1.5 MHz. You are limiting yourself to systems where the entire operation is performed in the PC. However something like a logic analyzer or scope can be pretty complete in itself, without the need for display mechanism or control knobs, and rely on PC communications for that. With suitable data compression the interface can be quite capable over even a serial link. This allows all long term storage (e.g. for comparison purposes) to be relegated to the PC file system. -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net> USE worldnet address!Article: 56528
"QBA" <bwang<AT>hal-pc<DOT>org> writes:
> Looking for a logical anayzer (a pod connected to a PC via USB or printer
> port), Any recommendations?
We've got a few GoLogic devices. They're small, so you can combine it
with a laptop and get a very portable solution. They're inexpensive,
meaning you can buy several. And they do almost everything the
relatively immobile $50K HP analyzer does.
--
Darin Johnson
I'm not a well adjusted person, but I play one on the net.
Article: 56529Followup to: <3EE16356.DD83583F@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > To some people, that would push them over to a competitor. In our case, > this may be a consideration since it gives a large advantage to the > people who buy our boards if they can try their own FPGA development > with out having to invest in tools. > Indeed, for prototyping/hobbyist boards especially that's a big deal. Altera supports the entire Cyclone line in their webpack; this is what made me choose a Cyclone-based board over an only slightly more expensive Stratix board... -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 56530
Followup to: <MPG.194babd24173f0a99898ed@192.168.42.131> By author: Dr. Anton Squeegee <SpammersAreVermin@dev.nul> In newsgroup: comp.arch.fpga > > I have to say that I'm constantly amazed by the (apparently) > broadly-held misconception that the PC is the answer to so many test > equipment needs. > To some degree, it is. Even Tektronix logic analyzers, at least the 700 series, are PC-based these days. After all, at some point you need to display a user interface, and PCs are pretty darn good at it, and they're cheap. Furthermore, it makes it easy to add new interfaces -- I just bought a PC-104+ pod for a Tektronix 700, and it came as a board plus a floppy disk with software. So the question becomes what your acquisition solution looks like, and how you then shuffle data to the analysis/user interface computer. That, in turn, depends on what kind of analysis bandwidth you need. In terms of speed, you pretty much have from slowest to fastest: serial port (115 kbit/s), parallel port (~5 Mbit/s), USB 1.x (11 Mbit/s), 100Base-TX Ethernet (100 Mbit/s), USB 2.x or Firewire (400 Mbit/s), 32/33 PCI bus (1 Gbit/s), 64/66 PCI or 32/133 PCI-X bus (4 Gbit/s), 64/133 PCI-X bus (8 Gbit/s). Since this is comp.arch.fpga: a PCI card with an FPGA should make a good platform to build an inexpensive logic analyzer around... -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 56531
Hi all, I posted info and pictures about the FPGA board I built, following the feedback I received on my last post. Here are the pictures! http://www.fpga4fun.com/images/fpgapcbEP1K.JPG http://www.fpga4fun.com/images/pluto_musicbox.jpg My first board is based on a EP1K10TC100, hope to build one based on Xilinx device soon. Jean http://www.fpga4fun.com/ Feedback is welcome!Article: 56533
Are there more details lurking somewhere on the V2Pro-X? Apart from natively speaking 10 Gb ethernet (with just a transceiver), and the IOs being more flexible? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 56534
Peter Alfke <peter@xilinx.com> wrote in message news:3EE0E89B.868D3D4B@xilinx.com... > Sorry, this was not meant for public consumption. Just for a friend... > Shows my appreciation for a nifty USB interface Talking about nifty USB interfaces, if anyone wants to add USB connectivity to their existing FPGA prototype boards, have a look at ... http://www.nialstewartdevelopments.co.uk/downloads.htm As I say, nothing's in production, but if a few people wanted interfaces I could put a few together. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 56535
Ya rickman good idea. If all the masters candidates picked projects from opencores then at least their work would live on. Think of how many hours have gone into these projects just to be dumped down the drain. Steve "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EDF825B.526CEF91@yahoo.com... > Priyal wrote: > > > > Hi, > > I am a graduate student in Electrical and Computer Engineering. > > I still have 1 more year to graduate. > > I want to design hardware which has some practical application. > > I am looking for topics in Digital Design/VLSI on which i can do my final project. > > Can anyone suggest some related topics? > > I would suggest that you take a look at www.opencores.org. There are > lots of projects that you can work on. Or you can come up with your own > and get a lot of support there. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 56536
Pooja from LA <poojakumari69@hotmail.com> wrote in message news:RJ8Ea.554$Cn1.361@newssvr19.news.prodigy.com... > Hi all, > We are a fabless company and are interested in outsourcing hardware > verification. Am asking the question in this newsgroup as was not sure where > to post it. > What I am interested in knowing is that what could be outsourced, where do I > find companies who can do it for low price (India/china maybe ???) and what > are the going rates. > We are working with TSMC in Taiwan as our foundry. > Thanks in advance for your help > -poo It might be worth your while contacting Verilab at http://www.verilab.com They're a locally (Glasgow) based company specialising in hardware verification. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 56537
Hi, Have you resorted the output/the output sequence? You may need to utilize the INDEX signals in order to re-order the output sequence. Best regards, Basuki Keren -----Original Message----- From: David M. Palmer [mailto:dmpalmer@email.com]=20 Posted At: Saturday, June 07, 2003 11:31 AM Posted To: fpga Conversation: Xilinx FFT Core Problems Subject: Re: Xilinx FFT Core Problems In article <66c23f42.0306060731.6180ea01@posting.google.com>, SAF <safahmy@hotmail.com> wrote: > Hi, >=20 > I've been trying for days to get the Xilinx 1024point FFT core working > in the Single Memory Space configuration. I get answers, but they=20 > don't match MATLAB at all. I do get a peak for a sine-wave, but its a=20 > few samples to the left of the one in MATLAB, and I don't get a second > peak. But if I create a random vector of 1024 complex numbers (of=20 > fixed aplitude, eg. 32-32i, 32+32i...) it gies comeletely different=20 > answers. I'm not worried about the amplitudes, just the signs (using=20 > for OFDM demodulation). Has anyone used this core? I've used the=20 > CoreGen blockram thingy, is that okay? It's a Virtex II. I've attached > my code, sorry it's quite long. I really would appreciate any help, as > I'm running to a deadline. Nothing specific about the Xilinx FFT but-- In FFTs there are various differences in the order the data come out (e.g. bit reversal), the normalization (dividing by N), etc. You may want to try running a series of sine waves through your FPGA with 1,2,3... cycles per 1024 samples and looking at where the peak ends up and what its magnitude is. --=20 David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 56538
Steve Casselman wrote: > > Ya rickman good idea. If all the masters candidates picked projects from > opencores then at least their work would live on. Think of how many hours > have gone into these projects just to be dumped down the drain. > > Steve I have been watching opencores for a while and it really seems to be taking off. They even have a USB2.0 core that I expect we will take a hard look at when it comes time to add USB to our board. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56539
I am looking for Xilinx FPGA Development Board that has these features. 1. The board has several empty sockets. Each sockets support different family of Xilinx FPGA family. 2. If you want to test drive your design, you need to plug in the FPGA chip to one of the socket. Once your design is completely correct, you just need to unplug it, put it to your own board, wire-wrap it, and connect it to a PROM so it will be ready to be programmed each time you turn your board on. So, can anyone help me to find this development board? Most the board that I have seen has their FPGA chip soldered to the board. I don't like that! I want to have the flexibility of putting the FPGA chip to my own system. Thanks in advance! HendraArticle: 56540
"Jake Janovetz" <jakespambox@yahoo.com> wrote in message news:d6ad3144.0306041354.1a5760e2@posting.google.com... > Is anyone out there using a third-party schematic entry tool (or even > HDL tool) for Xilinx FPGAs? I'll exclude Synplicity from my poking > and prodding because I know it's used a lot. > > There are several situations where schematic entry would be a nice > alternative to HDL for building an RPM. ECS is a waste of bits in my > opinion and Viewlogic isn't so hot anymore. I know Protel offers > schematic entry with Xilinx primitives and I assume OrCAD has > something similar. Are they worth using? > > As always, you make yourself a slave to the tool by doing this and I > see that as one big advantage of the HDL route, but I thought I'd ask. > > Jake Altium(makers of protel) advertise nvisage for that http://www.altium.com/products/nvisage.htm http://www.nvisage.com/ supposedly does schematics and vhdl and simulations Haven't tried it yet, but have a demo cd floating around some where here. They also have an eda news page http://www.altium.com/products/edanews.htm AlexArticle: 56541
Hi! I have a crazy FPGA application idea for which I need precise timing inside the FPGA. My thought was to create a delay line of a couple of CLBs inside the chip, and measure the phase difference between it's input and output outside the chip. Using this as an error signal I can control the VCCINT regulator to keep the phase-shift (and consequently the speed of the FPGA) under control. I plan to use Xilinx Spartan 2E as the device, but I guess the technique can be used with almost any FPGA. So, my question is, how much the delay of a CLB is depending on the supply voltage? Where can I find (if any) documentation on this? How far can I deviate from the nominal VCCINT value without damaging the device? (the datasheet says 1.8V+-5% in my case, but also specifies 1.5V as the data retention limit) How constant is the delay over the entire chip? I mean, if I measure the delay of CLB A, will CLB B at the other side of the chip have the same delay? Has anybody done something like this, any recommendations? Thanks, Andras TantosArticle: 56542
There is a picture of the Ant8 and Ant16 intestines at http://www.rockylogic.com/files/AntGuts_LoRes.jpg The main purpose of the PAL is to load the FPGA quickly. The flip sides of the boards contain the FPGAs, where the clever stuff is loaded ;-) TimArticle: 56543
> You only control one aspect of delay: gate delay. The other ascpect is > routing delay, which is substantial too and you don't have any influence. That was one of my conerns. However for my particular application it would only mean a reduction in control range (i.e. total delay is x*<Gate delay>+y*<routing delay> where I can control only one element while the other is constant). Also, routing delay in an FPGA should be a complex thing on it's own I guess so I'm not completely convinced it's totaly independent from VCC. Andras TantosArticle: 56544
Hi. I'm trying to find information and approximate prices for the Insight Spartan-II PCI Development Kit and its options. It seems that the original Insight website has been replaced and reorganised by Memec, so a web-search for the kit turns up a load of broken links. Memec's site search engine seems particularly useless. If anybody could suggest a suitable web resource, I'd be grateful. -- Dave FarranceArticle: 56545
I finally worked out the answer. My input signal was not utilising the full dynamic range, it was only varying from -32 to +32. Because of the errors due to finite precision, the peaks in the output were not visible. When I increased the input to vary from -1023 to +1023, it worked. On another note, my results were coming in shifted to the right by one point. In the Single Memory Space configuration, the waveform in the documentation suggests that you can sample the first output on the clk rising edge following the forcing '0' of mrd, but this yields a shift. If you sample on the falling edge after that, it works fine. Anyone confirm this? I've tried this with a post-map and a post-p&r model and both exhibit this behaviour. Thanks to all. "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:<5pC$$3hLDHA.1160@exchnews2.main.ntu.edu.sg>... > Hi, > > Have you resorted the output/the output sequence? You may need to > utilize the INDEX signals in order to re-order the output sequence. > > > Best regards, > > Basuki Keren > > -----Original Message----- > From: David M. Palmer [mailto:dmpalmer@email.com] > Posted At: Saturday, June 07, 2003 11:31 AM > Posted To: fpga > Conversation: Xilinx FFT Core Problems > Subject: Re: Xilinx FFT Core Problems > > > In article <66c23f42.0306060731.6180ea01@posting.google.com>, SAF > <safahmy@hotmail.com> wrote: > > > Hi, > > > > I've been trying for days to get the Xilinx 1024point FFT core working > > > in the Single Memory Space configuration. I get answers, but they > > don't match MATLAB at all. I do get a peak for a sine-wave, but its a > > few samples to the left of the one in MATLAB, and I don't get a second > > > peak. But if I create a random vector of 1024 complex numbers (of > > fixed aplitude, eg. 32-32i, 32+32i...) it gies comeletely different > > answers. I'm not worried about the amplitudes, just the signs (using > > for OFDM demodulation). Has anyone used this core? I've used the > > CoreGen blockram thingy, is that okay? It's a Virtex II. I've attached > > > my code, sorry it's quite long. I really would appreciate any help, as > > > I'm running to a deadline. > > Nothing specific about the Xilinx FFT but-- > > In FFTs there are various differences in the order the data come out > (e.g. bit reversal), the normalization (dividing by N), etc. > > You may want to try running a series of sine waves through your FPGA > with 1,2,3... cycles per 1024 samples and looking at where the peak ends > up and what its magnitude is.Article: 56546
> I've found the Parallel cable III to be totally reliable on certain > computers, and > anywhere from marinal to totally nonfunctional on some others. I haven't > tried hacking the unit to find the specific signal that was the problem. > But, it clearly was associated with specific characteristics of the > parallel port chip on the motherboard. Yes it is, but xilinx is to blame. (See my previous posts) The parallel port standard guarantees the high voltage level to be at least 2.4V but xilinx uses buffers that switch at VDD/2 (2.5V minus half a diode drop for parallel cable III) result in a negative or very small positive noise margin. Additionally, most parallel ports have a very slow rising edge once they reached about 2V but the CMOS buffers react very fast. So if there is some noise on the parallel port, the CMOS buffers will switch multiple times for a single rising edge. The HCT125 buffers are available in version that switch at 1/3 VDD which helps a lot. Also you can use a feedback resistor between input and output of the buffer to build a schmitt-trigger. For JTAG you have the additional problem of noise and reflection on the wires between the parallel cable and the FPGA. Keeping this part short are adding proper termination will do the job.Article: 56547
Dave Farrance <davefarrance@yahooerasethis.co.uk> wrote: : Hi. : I'm trying to find information and approximate prices for the Insight : Spartan-II PCI Development Kit and its options. : It seems that the original Insight website has been replaced and : reorganised by Memec, so a web-search for the kit turns up a load of : broken links. Memec's site search engine seems particularly useless. : If anybody could suggest a suitable web resource, I'd be grateful. for the refernce designs try http://legacy.memec.com/solutions/reference/xilinx Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56548
Hi I am almost going nuts but it looks like a XST synthesis problem - a desing with 1) BSCAN_SPARTAN2 2) long shift register and latch connected to BSCAN when synthesized then XST sees large fanout and insert buffers driver with LUTs to drive the CLK inputs of the shift register and latches. I think this is due to the fact XST think BSCAN is not connected to any chip IO (as there are no connections in VHDL of course). on chip BSCAN of course has dedicated connections to JTAG pins. anyway the clock fanout buffers are driven with GND !! for the synthesis BSCAN outputs are GND, so it gets optimized away. I really think that this is XST bug because all works when registes lenght is small enough, so procticallay the same source stops working as soon as XST inserts clock fanout buffers. antti lukats P.S. has anybody some real example of how to use the BSCAN in VHDL maybe I am missing something (well doing it by the book)Article: 56549
I have been looking into : Xilinx : XtremeDSP Development kit Altera : APEX DSP Development kit DSP Development kit (Startix) NIOS Development Kit Too many different boards/complexities - all I need is to design simple QAM / FFT blocks, download it into target FPGA and output signals on the line ? Any recommendations regarding use of DSP libraries : System Generator / ISE vs DSP Builder / Quartus II / SOPC thanks, Dubi
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