Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
mnemo5@163.com schrieb: > Thanks for your help. > > Actually, what I want to do is to make a hardware implementation(FPGA) > of an Extended Kalman Filter of a tracking system(It works well in > Matlab). > > I am a beginner of FPGA,so can anybody give me some suggestios? > > Thank you ~~ > Hi mnemo, have a look at this page (especially the PDFs) http://www-user.tu-chemnitz.de/~beber/DA/da.php It's a thesis work, where a kalman filter is used for controlling an inverse pendulum. The really intresting point here is the way they use fixed point arithmetic to keep the hardware lean. You can do that in Matlab too, by using the fixed point toolbox (if available). Now comes the bad news, it's writen in german. Have fun EilertArticle: 97576
I want to do all sorts of things. After this I want to build an 8bit computer using transistors. I saw one on the internet, but it didn't look like it ran any decent software. I have no idea if I will ever actually build it. Right now I'm learning a lot about FPGAs and binary math, so its worth it just for that. :) I want a combinational multiplication circuit becase its a ton faster than sequential as far as I've been able to figure out. I don't mind if the schematic contains tons of parts and takes up 1.5 square feet of board. ;) But I'm not going to do division with that many parts. I guess the reason I came up with 75 is because that's the year of the Altair and other computers becoming "popular"? It will be fun to see what kind of computer I can design out of commonly available parts, what it would have cost, and how fast it is. So far my initial calculations are 4-4.5 million 32x32bit multiplications per second. That is pretty fast, comparable to a 50MHz 486. For a while I wanted to build a computer out of relays, but I'm not that brave yet. That's a LOT of time. :) I've just completed the soldering on a 19,008 LED display. Talk about current, the thing draws 130A! So, yes...I am crazy. :) http://www.stockly.com/images2/060129-LED_Display_Front_2718.jpg http://www.stockly.com/images2/060129-LED_Display_Back_2716.jpgArticle: 97577
i just want to configure a harware but also i should have the control .i want to interpret the configuration bitsand then want to configure the hardware .Article: 97578
Well the boards do physically exist, Silica had one S3e SK board at Embedded, but the actual shipping is slipping to March, ASFAIK Antti PS I did like page 3 on the Schematic! It takes one day to recover that missing schematic so why even bother hiding it?Article: 97579
Maybe we should get an offering out there. Question is could we get the silicon as fast as we can make the board? John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104Plus Spartan-3 Development Board. http://www.enterpoint.co.uk "Eric Smith" <eric@brouhaha.com> wrote in message news:qhpsldd3is.fsf@ruckus.brouhaha.com... > Does anyone else find the cover art of the 1Q2006 Xilinx Xcell journal > to be rather ironic, given how much Xilinx likes to trumpet their low > power consumption compared to the other leading brand (e.g., Xilinx > advertisement on page 28 of the same issue)? > > I'm still eagerly awaiting the February 2006 availability of the > Spartan-3E starter kit. Five more days to go, unless it slips again. > Today if I click on the Spartan-3E Starter Kit in the online store, > it takes me to a page declaring: > > A technical problem has interrupted your session. We apologize for > the inconvenience this has caused you.Article: 97580
Thanks you for the reply. I got it to work! Strange solution. By mounting a CPLD on my board and routing FPGA_TDO into CPLD_TDI and connecting the JTAG cable to: FPGA_TDI og CPLD_TDO Maby the CPLD is more tolerent? My JTAG system is running 2.5V Andreas BeierArticle: 97581
>Hi, >I am working on a 10 Gigabit Ethernet Projet. >I have to choose a High-Speed Development Board. >I don't know yet which kind of FPGA I am going to use. (Altera or >Xilinx). > >I saw on Altera's Web Site the "Stratix GX High-Speed Development Board" >http://www.altera.com/literature/ug/ug_stx_gx_hs_dev_kit.pdf > > >I saw on Altera's Web Site a second High Speed Development: "Stratix II >High-Speed Development" >http://www.altera.com/literature/ds/ds_stratix.II_hs_dev.board.pdf > > > >I found the equivalent on Xilinx's Web Site. But I found nothing. >Can you confirm me that nothing equivalent of these 2 High Speed >Development Board of Altera is realised by Xilinx? > > > Nobody can help me?Article: 97582
well 3 companies are known to be shipping s3e based boards for some time already, Xilinx seems to be simply delaying what is very strange as it really hard to belive that other companies are getting Xilinx silicon earlier than Xilinx himself!! shipping are s3-100e based board from Avnet http://www.cesys.com/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53 http://www.zefant.de/de/products/index.php there are possible even more boards already shipping AnttiArticle: 97583
Hello, I'm trying to develop an USB 2.0 OTG interface with a FPGA (Xilinx or Altera). Therefore I think I'll have to make some sort of IP with UTMI(+) or ULPI interface to communicate with an external PHY. As PHY i was thinking about the ISP150x frow Philips or the USB3300 from SMSC. Maybe someone else better suggestions? Buying a IP is expensing if you're not planning to make lots of the product, unless there is a free USB 2.0 OTG IP-core. I also need a development/evaluation kit. I found a few interesting boards: hydraXC with the LEEB or the one from asics.ws. Wich one can you recommend? Hope you can help me. MartinArticle: 97584
If you can afford it have a look at equivalence checkers, relative easy for RTL <-> RTL and an absolute pain to do between gatelevel<->RTL. Equivalence checkers are formal tools (hence the $$$$), so no testvectors and the comparison is exhaustive. Another much easier and cheaper solution is to use waveform compare, run 2 simulation and compare the outputs, this can be done automatically and scripted by most simulators (I use Modelsim), Hans www.ht-lab.com "Emanuel Machado" <Emanuel-Machado@cytonome.com> wrote in message news:ee985a4.-1@webx.sUN8CHnE... > Hi, > > We're trying to move our development and testing of VHDL code towards an > automatic testing and validation system. Here's the idea: if I change > something in the code, I would run something that would compile and test > the whole thing and give an alarm if something else broke. I'm curious as > to what you guys in the industry use. An obvious approach would be to > build a very thorough test vector file and run it every time and look for > mismatches between expected data and actual results. Is this the best > approach? How about running it automatically? Do you have any > ideas/experience on this matter that you could share? > > Thanks in advance, > > EmanuelArticle: 97585
"it's writen in german. " it's really a bad news. :( Thank you all the same!!Article: 97586
all hydraxc modules have USB OTG connector on them so the LEEB isnt even required, just power the module with 3.3V and plug the USB connector. The USB chip is philips ISP1671 developing and validating (eg passing USB OTG compliance testing) an HS OTG IP core is not less than 1 man year. So buying an IP core or using some other options is possible better choice both isp150x or usb3300 can be used for the OTG IP core, but it really isnt so reasonable to be implemented in the FPGA also from the resource utilization, etc so if you need HS use ISP1671 for FS speed I would use Atmel AT90USB1287 but there are other choices also available AnttiArticle: 97587
<fpga_toys@yahoo.com> wrote in message news:1140727198.395726.97600@u72g2000cwu.googlegroups.com... >> > and low level hardware design is soon to be long gone for all the >> > same reasons of labor cost vs. hardware cost. >> Where price, performance and power consumption don't matter a higher >> level language might become more prevalent. > > The power argument is moot, as the difference between power for a good > C coder and a good asm coder, is probably less than a fraction of a > percent. I was talking about the FPGA domain here, not SW. >> I also wonder if price/performance/power consumption will become much >> less important in the future, as it has with software. These days >> you can assume application software will be run on a 'standard' >> sufficiently powerful PC. It won't be the case that at the start of >> every hardware project that you can assume you have a multi million >> gate FPGA (or whatever) at your disposal. > > Today, the price difference between low end FPGA boards and million > gate boards is getting pretty small, with megagate FPGAs in high > volume. Five, or even two years ago, was pretty different. Not every design has the need for million gate device functionality, Altera and Xilinx's low cost families seem to be selling in big numbers. Sometimes it's important to push the performance of these lower cost devices to keep costs down. Getting the same functionality into a smaller device can also be important if power consumtion is critical (my original point). How many power supplies do you need for your big devices? > The Google description for this group is: Field Programmable Gate Array > based computing systems, under Computer Architecture FPGA. And, after > a few years, I think we are finally getting there .... FPGA based > coputing instead of CPU based computing. This newsgroup and FPGAs were around long before some numpty at Google decided what their description should be. I don't think we should be taking this as a guiding pointer for the future. > The days of FPGA's being only for hardware design are slipping away. > While this group has been dominated by hardware designers using FPGA's > for hardware designs, I suspect that we will see more and more > engineers of all kinds here doing computing on FPGA's, at all levels. That's probably true, and I expect to be using other tools as well as VHDL in 5 years. However as John posted above, there's alot more to implementing an FPGA design than the description used for the logic and I think we'll still be using HDLs to get the most out of them for a long time to come (to a bigger extent than with C/asm). Nial.Article: 97588
Allan Herriman a =E9crit: > A *very rough* estimate would be to look at the size of a 10Base-2 > Ethernet Phy + MAC. Sure, the implementation will be totally > different, but the basic functions and speed are equivalent. Sounds good... :o) > You may need a few k bytes of buffer ram, but this may be shared with > your system ram if you're short of chip area. I'm in the preliminary phase of the project (feasability study, actually). I get some inspiration from SMSC's COM20020 datasheet. This chip has 2Kbytes of RAM. > IIRC, Arcnet drives a rather large signal (some V p-p) into a 93 ohm > cable. You will probably need a heavy duty driver just to get the > current. Still following SMSC's datasheet... Their evaluation board uses an HYC9088 as physical interface so I guess I'll use it too. Thanks a lot NicolasArticle: 97589
If we are going to do anything as a development board it won't be anything smaller than the XC3S500E. We are looking at cheap simple small modules for hobby use with smaller parts on but a few more boards to deliver before those appear. With 2 new development boards launching at DATE and planning an aggressive rollout of products for Q2 we have been somewhat busy. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Antti" <Antti.Lukats@xilant.com> wrote in message news:1140771268.319428.228280@z34g2000cwc.googlegroups.com... > well 3 companies are known to be shipping s3e based boards for some > time already, Xilinx seems to be simply delaying what is very strange > as it really hard to belive that other companies are getting Xilinx > silicon earlier than Xilinx himself!! > > shipping are > s3-100e based board from Avnet > http://www.cesys.com/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53 > http://www.zefant.de/de/products/index.php > > there are possible even more boards already shipping > > Antti >Article: 97590
Hi I am working on 10 Gb Ethernet project. I am going to use a NIOS II in a Stratix II or a Stratix GX. I don't know yet. I have seen 2 development boards for this high bandwith. Normally, the interface SPI (System Packet Interface) is used between the fpga and a NPU. I don't use a NPU but a NIOS II in the fpga! So I think I can choose a development board whose within the SPI is not supported. Are you agree with that?Article: 97591
Antti, thanks for your quick reply. Right now im investigating all possibilities. The hydraXC seems indeed a very interesting solution. But are you sure it hasnt the isp1761 on board in stead of the isp1671. Cause i cant find any infromation of the isp1671. And what do you know about integrate the PHY into the FPGA? Is it even possible? Cause we maybe want to make an asic of the usb interface. If it isnt possible and just use an external PHY, there are many possibilities. Because all the phys i have seen are using an ulpi or utmi interface. And thats what i prefer. MartinArticle: 97592
Martin Bosma <martinbosma@gmail.com> wrote: > Antti, thanks for your quick reply. > Right now im investigating all possibilities. The hydraXC seems indeed > a very interesting solution. But are you sure it hasnt the isp1761 on > board in stead of the isp1671. Cause i cant find any infromation of the > isp1671. > And what do you know about integrate the PHY into the FPGA? Is it even > possible? Cause we maybe want to make an asic of the usb interface. If > it isnt possible and just use an external PHY, there are many > possibilities. Because all the phys i have seen are using an ulpi or > utmi interface. And thats what i prefer. The page http://wiki.openchip.org/index.php/HydraXC:FAQ#What_other_components_are_on-board.3F had it wrong. I have now corrected it -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 97593
sorry sure 1761, my typo FPGA is not OK for USB PHY ULPI phys are nice (small package, etc) but the overall effort to get your OTG HS IP core validates is enormous anttiArticle: 97594
thanks Uwe, it should have been my responsibility to fix :) well I am really busy making more reference design and firmware for the hydraxc modules, tested working are u-boot (microblaze), including file load from sd-card sd-card support in uclinux microwindows (uclinux, direct hardware access) some ppc demos also, ppc-linux support in progress for the ISP1761 there are some device mode demos mass storage device, etc, for host mode now also a minimal standalone application that configures the internal hub and request some descriptors from connected device, etc.. AnttiArticle: 97595
Hi I am trying to design a PHY-MAC interface on a Virtex-2 Pro FPGA. The MAC will be running on PPC 405, and the the PHY algorithms would be implemented on FPGA. I was wondering what would be the best way for desiging the interface between the two. Can we designate some sort of shared memory that can be accessed by both?? I am very new to this, so any help would be deeply appreciated. Thanks AmitArticle: 97596
I have xilinx 95108 I am clocking by 555 timer and testing for some small project. the 95108 is getting heated up when I connect 555 output to an IO pin(1 number). Then i dont understand what to do about it, this is a problem because it rendered my previous chip non programable when I was doing same thing? circuit is (Dip)555 ---> 95108 (plcc 84)-----> cro I have hand soldered everything on a general purpose board any body had similar problem? regardsArticle: 97597
1 PHY *has* to be external to the FPGA before doing anything else, get some FPGA board with ethernet PHY on it, and get some EDK design with networking working, after that its easier for you to understand what you need shared memory sure can be used, but... its the best to use existing IP cores AnttiArticle: 97598
Hi
I 'm also trying to use a master ip on the PLB bus and I also use the
IPIF interface from the "Create Peripheral" wizard in EDK's XPS.
Like you I have some troubels with writhing and reading (I want to
write and read to/from a BRAM on the PLB-Bus)
You say that the slave attachment is also used for the master
trasaction. When I look at the timing diagram on pg 116 of the
plb_ipif.pdf
(http://www.xilinx.com/bvdocs/ipcenter/data_sheet/plb_ipif.pdf) it say
that when you read you will get a Bus2IP_WrReq is this correct, because
you want to read and not write. Is this correct?
I have made a small FSM to test a single read and write (at the bottom
of the message is my VHDL-code)
I have a state (PrepareWr_State and PrepareRd_State) to make sure all
the addresses are correct
I have a state (ReqWr_State and ReqRd_State) for the request =>
IP2Bus_MstWrReq and IP2Bus_MstRdReq
I have a state (AckWr_State and AckRd_State) for the ack that the IPIF
can read/write from/to my ip => IP2Bus_WrAck and IP2Bus_RdAck
I have a state (OkWr_State and OkRd_State) so I know everything went
well
But there must be something wrong because it doesn't work, when I want
to write something, my FSM stays in the ReqWr_State, and when I want to
read something it also doesn't do what it should do (or atleast what I
think it should do)
Can you help me please?
Mich
-- TRANSITION_STATE_LOGIC
STATE_TRANSITION_LOGIC: process (ACTUAL_STATE, pushR, pushL, pushU,
pushD, Bus2IP_MstLastAck, Bus2IP_WrReq, Bus2IP_RdReq)
variable counter_Rd : integer range 0 to 15;
variable counter_Wr : integer range 0 to 15;
begin
case ACTUAL_STATE is
when idle =>
if (pushR = '0') then -- pushR is active low
NEXT_STATE <= PrepareWr_State;
counter_Wr := 10;
elsif (pushL = '0') then -- pushL is actief laag
NEXT_STATE <= PrepareRd_State;
counter_Rd := 10;
else
NEXT_STATE <= idle;
end if;
when PrepareWr_State =>
if (counter_Wr = 0) then
NEXT_STATE <= ReqWr_State;
else
NEXT_STATE <= PrepareWr_State;
counter_Wr := counter_Wr - 1;
end if;
when ReqWr_State =>
if (Bus2IP_MstLastAck = '1') then
NEXT_STATE <= AckWr_State;
else
NEXT_STATE <= ReqWr_State;
end if;
when AckWr_State =>
if (Bus2IP_MstLastAck = '1') then
NEXT_STATE <= OkWr_State;
else
NEXT_STATE <= AckWr_State;
end if;
when OkWr_State => -- Writing is ok
if (pushU = '0') then -- PusU is active Low
NEXT_STATE <= idle;
else
NEXT_STATE <= OkWr_State;
end if;
when PrepareRd_State =>
if (counter_Rd = 0) then
NEXT_STATE <= ReqRd_State;
else
NEXT_STATE <= PrepareRd_State;
counter_Rd := counter_Rd - 1;
end if;
when ReqRd_State =>
if (Bus2IP_WrReq = '1') then
NEXT_STATE <= AckRd_State;
else
NEXT_STATE <= ReqRd_State;
end if;
when AckRd_State =>
if (Bus2IP_MstLastAck = '1') then
NEXT_STATE <= OkRd_State;
else
NEXT_STATE <= AckRd_State;
end if;
when OkRd_State => -- Reading is ok
if (pushD = '0') then -- pushD is actief laag
NEXT_STATE <= idle;
else
NEXT_STATE <= OkRd_State;
end if;
when others => NEXT_STATE <= idle;
end case;
end process STATE_TRANSITION_LOGIC;
-- TRANSITION_STATE_LOGIC
-- OUTPUT_LOGIC
OUTPUT_LOGIC: process (ACTUAL_STATE)
begin
case ACTUAL_STATE is
when idle =>
led <= "1110";
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when PrepareWr_State =>
led <= "0001";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when ReqWr_State =>
led <= "0010";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '1';
when AckWr_State =>
led <= "0011";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '1';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '1';
when OkWr_State =>
led <= "0100";
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when PrepareRd_State =>
led <= "1000";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when ReqRd_State =>
led <= "1001";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '1';
IP2Bus_MstWrReq <= '0';
when AckRd_State =>
led <= "1010";
IP2Bus_Data(0 to 3) <= D_out;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '1';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '1';
IP2Bus_MstWrReq <= '0';
when OkRd_State =>
if (D_out = Bus2IP_Data(0 to 3)) then
led <= "1011";
else
led <= "1100";
end if;
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "11111111";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
when others =>
led <= "1111";
IP2Bus_Data(0 to 3) <= schakelaar;
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= '0';
IP2Bus_Addr <= C_Memory_Addr;
IP2Bus_MstBE <= "00000000";
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
end case;
end process OUTPUT_LOGIC;
-- OUTPUT_LOGIC
Article: 97599On a sunny day (23 Feb 2006 19:27:04 -0800) it happened "Peter Alfke" <alfke@sbcglobal.net> wrote in <1140751624.632774.85380@u72g2000cwu.googlegroups.com>: > >If you absolutely want to make life tough for yourself, what is so >special about 1975-vintage circuits? Just nostalgia, and those lovely >yellow books? > >Peter Alfke, Xilinx Applications Yes Peter, way to go, use the best of teh old and new technology: http://www.neoseeker.com/Articles/Hardware/Reviews/aopenax4btube/
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z