Messages from 103800

Article: 103800
Subject: Re: How do I use the DDS core in a verilog flow?
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 12 Jun 2006 10:30:40 +0100
Links: << >> << T >> << A >>

xilinx_user wrote:
> I am new to using Xilinx cores. My intention is to use the DDS core,
> for which I was able to generate a number of files using coregen. It
> appears that only the "padded" EDIF can be run through the backend
> stages. My question - as naive as it is - is what do you instantiate in
> a higher level verilog module in order to implement the design?
> 
take a look at core_name.veo (core_name.vho for vhdl) vit a text editor, 
these files have instantiation template for your core (all the 
param/generics and ports)

(replace core_name with your actual core name)
have fun,
Aurash

Article: 103801
Subject: Re: Xilinx timing viloations
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 12 Jun 2006 10:36:06 +0100
Links: << >> << T >> << A >>

Prav,
The approach is very dependent of the root cause.
you have to investigate where your time budget is spent, logic or routing
if is on logic try to reduce the number of logic levels, pipeline, 
re-balance registers, etc.
if is on routing try to floor plan, use area constraints, different 
switches in map/par etc.

Aurash

prav wrote:
> Hi all,
> 
> I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set
> up viloations).
> What are the steps to be taken to meet the frequency other than doing a
> pipeline in RTL.
> I am using Xilinx FPGA's.
> 
> regards
>

Article: 103802
Subject: Re: Good free or paid merge software that edits two similar files?
From: charles.elias@wpafb.af.mil
Date: 12 Jun 2006 02:49:33 -0700
Links: << >> << T >> << A >>


Weng Tianxiang wrote:
> Hi,
> Recently I am asked to update several my projects. A lot of works has
> to be made, comparing old code and new code and replace old one with
> new one.
>
> I found that WinMerge is of great value in this respect. I would like
> to thank those people who developed the free software to let me use it
> and dramatically to increase my job efficiency and reliability.
>
> Thank you, WinMerge software designer.
>
> I wonder if there is better merge software better than WinMerge, free
> or paid?
>
> If you know, please let me know.
>
> Weng

I use Multi-Edit (not free) for editing and comparing text files.  It
is excellent for both purposes.

Charles

Article: 103803
Subject: Re: how to readback a frame
From: Vivian Bessler <vivian.bessler.nospam@sandbyte.com>
Date: Mon, 12 Jun 2006 11:44:21 +0100
Links: << >> << T >> << A >>

Hi Nicky,
Xtclsh is a tcl shell included with ISE.  The ChipScope user manual 
describes how to use it for JTAG operations.

Vivian

--
Sandbyte

Article: 103804
Subject: xc3sprog -- any updates?
From: "Eric" <jonas@mwl.mit.edu>
Date: 12 Jun 2006 04:28:48 -0700
Links: << >> << T >> << A >>

I was about to start hacking on xc3sprog after e-mailing the author and
not hearing back, but I was curious if anyone else has done the same.
I'm interested in adding programmatic support for the spartan-3
USER1/USER2 instructions, as well as getting it to program my
coolrunner-II CPLD and Virtex-4 LX. Before I reinvent the wheel, has
anyone else done this? 

   ...Eric

Article: 103805
Subject: Re: ICAP Virtex4 32 bits
From: Meres Five <meres5@alpha.tmit.bme.hu>
Date: Mon, 12 Jun 2006 14:24:38 +0200
Links: << >> << T >> << A >>

Hi,

> 
> I have implemented a small ICAP controller hanging on the "B" side of a 
> DPRAM.
> The ICAP is configured as 32 bits wide, but it does not work....
> 

I have successfully readback the IDCODE.
It was a RAMB16 issue...
It was in READ_FIRST mode, and that refired my state-machine,
instead of dispatch/complete.

I have put it in WRITE_FIRST - and success!

Best regards

Article: 103806
Subject: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
From: "Andy" <jonesandy@comcast.net>
Date: 12 Jun 2006 05:56:07 -0700
Links: << >> << T >> << A >>

I can think of several reasons Altera's own customers would want to do
this, and that should mean that Altera should want to too.

For enterprises that have standardized on vhdl/verilog design
methodology, yet have legacy AHDL code for which they don't want to
throw away and completely start over. Granted, the resulting code is
not always the best/most readable, but at least it works, and can be
simulated right along side revised vhdl code to determine sameness.

For use with better synthesis engines (i.e. Synplicity), even for
Altera targets.

For co-simulation at the rtl level with other vhdl/verilog simulators.

"AHDL works fine, and is supported" on Altera tools only. 3rd party
simulation, synthesis and formal analysis tools are not supported, and
won't be because AHDL is not a standard for anyone but Altera.

Andy

Jim Granville wrote:
> Andy wrote:
> > I find it interesting that Xilinx webpack has tools to convert AHDL to
> > VHDL, but Altera does not!  Of course, the copyright notice included in
> > the generated code restricts its use to Xilinx products.
>
>   Given Subroto's reply, why would Altera need to do this ?
> AHDL works fine, and is supported.
>
>   Xilinx, on the other hand, have to oil the pathways for
> Altera users, so they have to offer something...
> 
> -jg

Article: 103807
Subject: Re: xc3sprog -- any updates?
From: "Sandro" <sdroamt@netscape.net>
Date: 12 Jun 2006 06:00:45 -0700
Links: << >> << T >> << A >>

Eric wrote:
> I was about to start hacking on xc3sprog after e-mailing the author and
> not hearing back, but I was curious if anyone else has done the same.
> I'm interested in adding programmatic support for the spartan-3
> USER1/USER2 instructions, as well as getting it to program my
> coolrunner-II CPLD and Virtex-4 LX. Before I reinvent the wheel, has
> anyone else done this?
>

Eric,
I started using xc3sprog some weks ago (tired to upgrade the windrvr6
each
time I upgrade or recompile the kernel ;-) )
I made a very minor change in the detectchain.cpp in order to print the
device position of each device found in the chain.
I wrote also a script to help chosing the device to program
graphically.
Nothing about USER1/USER2... but when I've a little bit of time I would
like
hacking on xc3sprog too!

If You are interested I can send You the changes I made to
detectchain.cpp and the
script I wrote.

Have a nice day
Sandro

Article: 103808
Subject: Re: xc3sprog -- any updates?
From: "Eric" <jonas@mwl.mit.edu>
Date: 12 Jun 2006 07:16:21 -0700
Links: << >> << T >> << A >>

> Eric,
> I started using xc3sprog some weks ago (tired to upgrade the windrvr6
> each
> time I upgrade or recompile the kernel ;-) )
> I made a very minor change in the detectchain.cpp in order to print the
> device position of each device found in the chain.
> I wrote also a script to help chosing the device to program
> graphically.
> Nothing about USER1/USER2... but when I've a little bit of time I would
> like
> hacking on xc3sprog too!
>
> If You are interested I can send You the changes I made to
> detectchain.cpp and the
> script I wrote.
>
> Have a nice day
> Sandro

That sounds great!

After a few hours of work this morning I've already got it programming
my 4VLX25, and I just managed to get USER1 working.

This is really a testament to the original code; it is well-thought-out
and easy to understand.

Article: 103809
Subject: Re: How do I use the DDS core in a verilog flow?
From: "xilinx_user" <barrinst@ix.netcom.com>
Date: 12 Jun 2006 07:36:37 -0700
Links: << >> << T >> << A >>


Aurelian Lazarut wrote:
> xilinx_user wrote:
> > I am new to using Xilinx cores. My intention is to use the DDS core,
> > for which I was able to generate a number of files using coregen. It
> > appears that only the "padded" EDIF can be run through the backend
> > stages. My question - as naive as it is - is what do you instantiate in
> > a higher level verilog module in order to implement the design?
> >
> take a look at core_name.veo (core_name.vho for vhdl) vit a text editor,
> these files have instantiation template for your core (all the
> param/generics and ports)
>
> (replace core_name with your actual core name)
> have fun,
> Aurash

I tried that. The problem is that when you instantiate a verilog module
it will implicitly refer to a ".V" file, which is the simulation model.
It appears that only the EDIF file can be used for
synthesis/place&route.

What am I misinterpreting?

Article: 103810
Subject: Re: from VHDL to FPGA
From: "Eric Crabill" <eric.crabill@xilinx.com>
Date: Mon, 12 Jun 2006 09:10:47 -0700
Links: << >> << T >> << A >>

Hello,

You might look for a copy of "Synthesis and Optimization of Digital
Circuits" by Mr. Giovanni De Micheli. I would advise previewing this text at
a library before you consider buying it, though. I found it a bit abstract
for my own taste.

Eric

"elesser" <elesser@gmail.com> wrote in message
news:1150096033.903404.265200@f14g2000cwb.googlegroups.com...

> Any particular book that focuses on this subject that you liked?

Article: 103811
Subject: RocketIO AC coupling
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 12 Jun 2006 16:48:44 GMT
Links: << >> << T >> << A >>

Does anyone know whether the type of capacitor is important or not when AC 
coupling RIO signals to/from a VII-Pro please? I've heard that certain 
dielectrics are better than others but is it really that important?

TIA,

Roger.

Article: 103812
Subject: Re: Xilinx timing viloations
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 12 Jun 2006 16:52:56 GMT
Links: << >> << T >> << A >>

If you try to perform something too "complex" in your 8 ns, you have to 
change the complexity.  Often the problem is that logic has a larger number 
of logic levels than the application requires.  Find the critical path, 
figure out if you need 12 levels of logic - if there's another way to 
produce the same result in fewer logic levels, do it.  Often the FPGA you 
target has advanced silicon features that can speed up the implementation if 
you know it's there and can code to use it.  Pipelining is often the best 
approach, registering parts of the slow path in the previos cycle.

I can't make a baby in 4.5 months.  Is there a way to meet my deadline 
without using two women?


"prav" <praveen.kantharajapura@gmail.com> wrote in message 
news:1150089636.764110.11680@c74g2000cwc.googlegroups.com...
> Hi all,
>
> I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set
> up viloations).
> What are the steps to be taken to meet the frequency other than doing a
> pipeline in RTL.
> I am using Xilinx FPGA's.
>
> regards

Article: 103813
Subject: Re: Problem with DCM simulation models
From: Michael_R_Hicks-NR@raytheon.com
Date: Mon, 12 Jun 2006 17:03:39 GMT
Links: << >> << T >> << A >>

This is a multipart message in MIME format.
--=_alternative 005E3E9C8525718B_=
Content-Type: text/plain; charset="US-ASCII"

Try setting your simulation resolution to ps vice ns.
--=_alternative 005E3E9C8525718B_=
Content-Type: text/html; charset="US-ASCII"


<br><font size=2 face="sans-serif">Try setting your simulation resolution
to ps vice ns.</font>
--=_alternative 005E3E9C8525718B_=--

Article: 103814
Subject: Re: from VHDL to FPGA
From: "elesser" <elesser@gmail.com>
Date: 12 Jun 2006 10:08:31 -0700
Links: << >> << T >> << A >>

thanks a lot, everyone!!

Article: 103815
Subject: Re: How do I use the DDS core in a verilog flow?
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 12 Jun 2006 18:19:55 +0100
Links: << >> << T >> << A >>

just rename, or move these *.v files (behavioral models) from your way, 
and make sure the edifs are into the working directory, and should work.
Aurash

xilinx_user wrote:

>Aurelian Lazarut wrote:
>  
>
>>xilinx_user wrote:
>>    
>>
>>>I am new to using Xilinx cores. My intention is to use the DDS core,
>>>for which I was able to generate a number of files using coregen. It
>>>appears that only the "padded" EDIF can be run through the backend
>>>stages. My question - as naive as it is - is what do you instantiate in
>>>a higher level verilog module in order to implement the design?
>>>
>>>      
>>>
>>take a look at core_name.veo (core_name.vho for vhdl) vit a text editor,
>>these files have instantiation template for your core (all the
>>param/generics and ports)
>>
>>(replace core_name with your actual core name)
>>have fun,
>>Aurash
>>    
>>
>
>I tried that. The problem is that when you instantiate a verilog module
>it will implicitly refer to a ".V" file, which is the simulation model.
>It appears that only the EDIF file can be used for
>synthesis/place&route.
>
>What am I misinterpreting?
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324

Article: 103816
Subject: Re: Xilinx timing viloations
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 12 Jun 2006 18:24:04 +0100
Links: << >> << T >> << A >>

John_H wrote:

>If you try to perform something too "complex" in your 8 ns, you have to 
>change the complexity.  Often the problem is that logic has a larger number 
>of logic levels than the application requires.  Find the critical path, 
>figure out if you need 12 levels of logic - if there's another way to 
>produce the same result in fewer logic levels, do it.  Often the FPGA you 
>target has advanced silicon features that can speed up the implementation if 
>you know it's there and can code to use it.  Pipelining is often the best 
>approach, registering parts of the slow path in the previos cycle.
>
>I can't make a baby in 4.5 months.  Is there a way to meet my deadline 
>without using two women?
>  
>
of course it is, just make a baby with each, and we can find a marketing 
guy to say that you have 2 childrens in 9 months equals to 4.5 months on 
average / baby
Aurash

>
>"prav" <praveen.kantharajapura@gmail.com> wrote in message 
>news:1150089636.764110.11680@c74g2000cwc.googlegroups.com...
>  
>
>>Hi all,
>>
>>I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set
>>up viloations).
>>What are the steps to be taken to meet the frequency other than doing a
>>pipeline in RTL.
>>I am using Xilinx FPGA's.
>>
>>regards 
>>    
>>
>
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324

Article: 103817
Subject: Re: Xilinx ISE S/W Install kernel version "mismatch"
From: Rich Grise <richgrise@example.net>
Date: Mon, 12 Jun 2006 18:13:14 GMT
Links: << >> << T >> << A >>

On Sun, 11 Jun 2006 12:58:19 +0200, Felix Bertram wrote:

> Rich,
> 
> I am not really sure, why you are trying to install Xilinx on Slackware. 
> As you describe, you have a plain vanilla system, so probably  the 
> reason for using Slackware is, that you just did not have access to RedHat?
> 

No, my reason for using Slackware is, I can do a plain vanilla install,
hand-picking what I want and how I want it configured, and it will do
everything I want done, with the possible exception of Xilinx ISE until
I find a workaround. ;-) Meanwhile, I can still boot W2K and use ISE there.

I've tried Red Hat, and didn't like the M$-ish attitude of the install
script - it never even gave me an option to partition my drives or
anything, and Slackware was my first Linux ever, back in the mid-1990's,
when you had to download about 30 floppy disks. ;-) At the time, I picked
it from the vast smorgasboard of distros because I liked the name the best. :-)

Cheers!
Rich

Article: 103818
Subject: How to get lowest price for a ModelSim license?
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 12 Jun 2006 11:43:31 -0700
Links: << >> << T >> << A >>

Hi,
We want to buy a ModelSim license.

1. Buy Xilinx-ModelSim version license from Xilinx website shop for
$1150 with dongle and 1 year expiration limit;

2. Buy ModelSim PE version from one of agents we contact: $3K for
perpatual license.

Both versions will work and make no differences to our applications.

Does anyone knows a better way to buy a ModelSim license with lowest
price except the above two options? For a start-up, we prefer lowest
price, of course.

Thank you.

Weng

Article: 103819
Subject: Re: Xilinx ISE S/W Install kernel version "mismatch"
From: mghembru@harshrealm.uwaterloo.ca (MH)
Date: Mon, 12 Jun 2006 18:46:57 +0000 (UTC)
Links: << >> << T >> << A >>

In article <pan.2006.06.13.02.12.53.237366@example.net>,
Rich Grise  <richgrise@example.net> wrote:
>On Sun, 11 Jun 2006 12:58:19 +0200, Felix Bertram wrote:
>
>> Rich,
>> 
>> I am not really sure, why you are trying to install Xilinx on Slackware. 
>> As you describe, you have a plain vanilla system, so probably  the 
>> reason for using Slackware is, that you just did not have access to RedHat?
>> 
>
>No, my reason for using Slackware is, I can do a plain vanilla install,
>hand-picking what I want and how I want it configured, and it will do
>everything I want done, with the possible exception of Xilinx ISE until
>I find a workaround. ;-) Meanwhile, I can still boot W2K and use ISE there.
>
>I've tried Red Hat, and didn't like the M$-ish attitude of the install
>script - it never even gave me an option to partition my drives or
>anything, and Slackware was my first Linux ever, back in the mid-1990's,
>when you had to download about 30 floppy disks. ;-) At the time, I picked
>it from the vast smorgasboard of distros because I liked the name the best. :-)

Red Hat not giving you a chance to partition your drives? Have they slipped
that much? Back when I was doing more sysadmin work, I thought RH 7.x/8.x
was quite good, including all those options, letting you pick what you want
to install, etc..

Mind you, I've kept running Slackware at home, mainly because centos and
such weren't available last time I installed, and Fedora/Yarrow had lots of
"unstable" warnings.

MH

Article: 103820
Subject: Re: How to get lowest price for a ModelSim license?
From: "oneweek" <sunnyz@pacbell.net>
Date: 12 Jun 2006 12:08:27 -0700
Links: << >> << T >> << A >>

you can try lattice semi for a fraction of cost, only restriction is
you have to use their FPGA, but not bad at all.

Weng Tianxiang wrote:
> Hi,
> We want to buy a ModelSim license.
>
> 1. Buy Xilinx-ModelSim version license from Xilinx website shop for
> $1150 with dongle and 1 year expiration limit;
>
> 2. Buy ModelSim PE version from one of agents we contact: $3K for
> perpatual license.
>
> Both versions will work and make no differences to our applications.
>
> Does anyone knows a better way to buy a ModelSim license with lowest
> price except the above two options? For a start-up, we prefer lowest
> price, of course.
> 
> Thank you.
> 
> Weng

Article: 103821
Subject: Re: How to get lowest price for a ModelSim license?
From: Andy <ajg112@ohm.york.ac.uk>
Date: Mon, 12 Jun 2006 20:26:04 +0100
Links: << >> << T >> << A >>

Weng Tianxiang wrote:
> Hi,
> We want to buy a ModelSim license.
> 
> 1. Buy Xilinx-ModelSim version license from Xilinx website shop for
> $1150 with dongle and 1 year expiration limit;
> 
> 2. Buy ModelSim PE version from one of agents we contact: $3K for
> perpatual license.
> 
> Both versions will work and make no differences to our applications.
> 
> Does anyone knows a better way to buy a ModelSim license with lowest
> price except the above two options? For a start-up, we prefer lowest
> price, of course.
> 
> Thank you.
> 
> Weng
>

Hi Weng,
I guess from 'start-up' you are talking commercial use. If, however, you
are an academic user, you might want to talk to europractice.

http://www.msc.rl.ac.uk/europractice/

Andy

Article: 103822
Subject: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 13 Jun 2006 08:00:02 +1200
Links: << >> << T >> << A >>

Andy wrote:
> I can think of several reasons Altera's own customers would want to do
> this, and that should mean that Altera should want to too.
> 
> For enterprises that have standardized on vhdl/verilog design
> methodology, yet have legacy AHDL code for which they don't want to
> throw away and completely start over. 

  I've assumed Altera allows mixed-source projects : so you do not have
to re-code the AHDL much at all.
Someone in Altera can correct that, if I am wrong ?

  Of course, new projects should always have a language review, to choose
the best tools to get the job done.

-jg

Article: 103823
Subject: Re: How to get lowest price for a ModelSim license?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 12 Jun 2006 13:06:36 -0700
Links: << >> << T >> << A >>

Weng Tianxiang wrote:

> 1. Buy Xilinx-ModelSim version license from Xilinx website shop for
> $1150 with dongle and 1 year expiration limit;

Quartus FIXEDPC $2k license covers windows modelsim
for vhdl or verilog.
One year limit only applies to updates -- tools keep working.
 From distributors only.

> 2. Buy ModelSim PE version from one of agents we contact: $3K for
> perpatual license.

Quartus FLOATLNX $3k license covers linux modelsim
for vhdl or verilog.
One year limit only applies to updates -- tools keep working.
 From distributors only.

   -- Mike Treseler

Article: 103824
Subject: Re: from VHDL to FPGA
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 12 Jun 2006 13:28:29 -0700
Links: << >> << T >> << A >>

With ise or quartus you can learn about synthesis
by running code examples to the RTL or Technology viewers.

          -- Mike Treseler

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