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xilinx_user skrev: > Aurelian Lazarut wrote: > > xilinx_user wrote: > > > I am new to using Xilinx cores. My intention is to use the DDS core, > > > for which I was able to generate a number of files using coregen. It > > > appears that only the "padded" EDIF can be run through the backend > > > stages. My question - as naive as it is - is what do you instantiate in > > > a higher level verilog module in order to implement the design? > > > > > take a look at core_name.veo (core_name.vho for vhdl) vit a text editor, > > these files have instantiation template for your core (all the > > param/generics and ports) > > > > (replace core_name with your actual core name) > > have fun, > > Aurash > > I tried that. The problem is that when you instantiate a verilog module > it will implicitly refer to a ".V" file, which is the simulation model. > It appears that only the EDIF file can be used for > synthesis/place&route. > > What am I misinterpreting? if I use coregen to generate a, for example, a memory block called "ram2kx8" I get from coregen: ram2kx8.v: that is the wrapper you need to include in you synthesis and simulation. ram2kx8.veo: that is a file with an example of how to instatiate the module (cut-n-paste from this file as needed) ram2kx8.edn: the edif file need to be in a place where the place and route toold can find it -LasseArticle: 103826
Hi all! I made a clocking module for Virtex4FX12 that accepts 66MHz from DCM0 (FX output at 6/9 ratio from 100MHz). Output is giving frequencies ranging from 35 to 66 MHz in 2MHz increments by changing Multiplier value (while D is fixed at 32) using DCM_ADV's Dynamic Reconfiguration (DRP). The output drives CMOS imaging chip MT9V403. The structure of this module is very simple and works perfectly in simulation and on oscilloscope, but I am not satisfied with the performance in real usage. When I change the clock settings the imaging chips fails to respond. The only setting that works perfectly is 66MHz (M=D=32). I also added BUFGCE at the output to enable clock only when DCM lock and syncronised to full clock pulse. That doesn't help either. Does anyone has the idea what can be wrong? Thanks in advance GuruArticle: 103827
Looking for a qualified patent attorney/agent specialized in programmable logic technology to file FPGA architecture and software algorithm related patents. Worked with a patent agent advertized in IEEE magazine but this guy don't get it. I'm in Bay area but the attorney/agent doesn't have to be in Bay area. Any recommendations? Thanks in advance, HTArticle: 103828
Hi Jerome, Sylvan, Looking at your architecture requirements, I would say that your need is to design an endpoint solution. Here is a link that would perhaps help you see where an endpoint solution sits in the model PCI Express system architecture. http://www/products/ip/images/pci_express_fig1_typ_app.pdf Going a little bit further, Altera devices (and I think Xilinx is the same) are capable of doing both root complex as well as end point applications. Altera offers a complete portfolio of solutions for PCI Express applications, some highlights as it pertains to Stratix II GX are given below: End point IP Core (x1, x4, x8) with proven interoperability at the PCI SIG (e.g. x8 IP core: http://www/products/ip/iup/pci-express/m-alt-pcie8.html) FPGA (Stratix II GX) with embedded transceivers that are shipping today Stratix II GX based PCI Express development kit orderable today (http://www/products/devkits/altera/kit-pciexpress_s2gx.html) Besides Stratix II GX, Altera supports PCI Express on Cyclone II, Stratix II as well as Stratix GX. Here is a link that would provide you with an overall idea of Altera PCI Express solutions: http://www.altera.com/technology/high_speed/protocols/pci_exp/pro-pci_exp.html Please feel free to contact me if you have any questions (amalhotr@altera.com) Regards, Aashish Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > > Looking to use some Xilinx V4FX or Altera Stratix GXparts for designing > > several endpoints using PCI Express for the 1st time. I dont have the > > PCI-Express spec yet but am wondering whether I need a root complex? > > > > My understanding is that root complex differs from endpoint in that it > > is used > > for interfacing to main CPU memory. > > However if I only want to communicate between various FPGA endpoints > > (using a switch) do I really need a root complex IP bridge? Seems like > > all IP cores > > are endpoints only? > > > > Any Xilinx or Altera PCI Express IP core recommendations based on > > experience? > > I would guess it's more or less like PCI and you need someone to > enumerate the busses and assign address. > > > SylvainArticle: 103829
HT, Sure. Email me at xilinx. Austin HT Chang wrote: > Looking for a qualified patent attorney/agent specialized in programmable > logic technology to file FPGA architecture and software algorithm related > patents. > Worked with a patent agent advertized in IEEE magazine but this guy don't > get it. > I'm in Bay area but the attorney/agent doesn't have to be in Bay area. Any > recommendations? > Thanks in advance, > HT > >Article: 103830
I do not know what's wrong, but I would have divided 100 MHz by 25 in a simple 5-bit counter, and then multiplied the 4 MHz by M/2 in a DCM. Seems simpler to me. Note that in synthesis mode, the input frequency can be as low as 1 MHz, as long as the output frequency is above 25 MHz. Peter Alfke ================== Guru wrote: > Hi all! > > I made a clocking module for Virtex4FX12 that accepts 66MHz from DCM0 > (FX output at 6/9 ratio from 100MHz). Output is giving frequencies > ranging from 35 to 66 MHz in 2MHz increments by changing Multiplier > value (while D is fixed at 32) using DCM_ADV's Dynamic Reconfiguration > (DRP). The output drives CMOS imaging chip MT9V403. The structure of > this module is very simple and works perfectly in simulation and on > oscilloscope, but I am not satisfied with the performance in real > usage. When I change the clock settings the imaging chips fails to > respond. The only setting that works perfectly is 66MHz (M=D=32). I > also added BUFGCE at the output to enable clock only when DCM lock and > syncronised to full clock pulse. That doesn't help either. Does anyone > has the idea what can be wrong? > > Thanks in advance > > GuruArticle: 103831
Other choices are: divide 100 MHz by 5 in a counter, then multiply by N/10, or divide 100 MHz by10 in a counter, then multiply by N/5 Peter Alfke Peter Alfke wrote: > I do not know what's wrong, but I would have divided 100 MHz by 25 in a > simple 5-bit counter, and then multiplied the 4 MHz by M/2 in a DCM. > Seems simpler to me. > Note that in synthesis mode, the input frequency can be as low as 1 > MHz, as long as the output frequency is above 25 MHz. > Peter Alfke > ================== > Guru wrote: > > Hi all! > > > > I made a clocking module for Virtex4FX12 that accepts 66MHz from DCM0 > > (FX output at 6/9 ratio from 100MHz). Output is giving frequencies > > ranging from 35 to 66 MHz in 2MHz increments by changing Multiplier > > value (while D is fixed at 32) using DCM_ADV's Dynamic Reconfiguration > > (DRP). The output drives CMOS imaging chip MT9V403. The structure of > > this module is very simple and works perfectly in simulation and on > > oscilloscope, but I am not satisfied with the performance in real > > usage. When I change the clock settings the imaging chips fails to > > respond. The only setting that works perfectly is 66MHz (M=D=32). I > > also added BUFGCE at the output to enable clock only when DCM lock and > > syncronised to full clock pulse. That doesn't help either. Does anyone > > has the idea what can be wrong? > > > > Thanks in advance > > > > GuruArticle: 103832
John Smith wrote: > When I discover en error in one of your products, and there is no way what > so > ever tha I can get in touch with you, I gett pissed off ! You must have > some sort of customer service, anything else is just stupid.. http://www.xilinx.com Click on 'Support' Click on 'WebCase' (scroll down a bit to see it) Login and enter your complaint. If you're going to spit the dummy over the fact you have to use a web browser instead of an email client, well.. grow up. Also, as someone else said, if you don't supply any useful information it's impossible to help you. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 103833
oneweek wrote: > you can try lattice semi for a fraction of cost, only restriction is > you have to use their FPGA, but not bad at all. > ModelSim is included with shipments of Lattice's ispLEVER base software, which you can purchase (Windows part number: LS-HDL-BASE-PC-N) from the Lattice online store for $495 at http://www.latticesemi.com/store/software.cfm Regards, Bart Borosky, LatticeArticle: 103834
> HT Chang wrote: > >>Looking for a qualified patent attorney/agent specialized in programmable >>logic technology to file FPGA architecture and software algorithm related >>patents. >>Worked with a patent agent advertized in IEEE magazine but this guy don't >>get it. >>I'm in Bay area but the attorney/agent doesn't have to be in Bay area. Any >>recommendations? >>Thanks in advance, >>HT Austin Lesea wrote: > HT, > > Sure. Email me at xilinx. > > Austin Wot - no smiley ? :) -jgArticle: 103835
Maybe he moonlights? "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:448e05d3$1@clear.net.nz... >> HT Chang wrote: >> >>>Looking for a qualified patent attorney/agent specialized in programmable >>>logic technology to file FPGA architecture and software algorithm related >>>patents. >>>Worked with a patent agent advertized in IEEE magazine but this guy don't >>>get it. >>>I'm in Bay area but the attorney/agent doesn't have to be in Bay area. >>>Any recommendations? >>>Thanks in advance, >>>HT > Austin Lesea wrote: >> HT, >> >> Sure. Email me at xilinx. >> >> Austin > > Wot - no smiley ? :) > -jg >Article: 103836
Rob, Ha ha. No. Hardly. But I do work with consultants who do good work. Austin Rob wrote: > Maybe he moonlights?Article: 103837
Eric wrote: > I was about to start hacking on xc3sprog after e-mailing the author and > not hearing back, but I was curious if anyone else has done the same. > I'm interested in adding programmatic support for the spartan-3 > USER1/USER2 instructions, as well as getting it to program my > coolrunner-II CPLD and Virtex-4 LX. Before I reinvent the wheel, has > anyone else done this? I've modified it to run under FreeBSD (pretty trivial changes) but nothing more (since I'm only using Spartan 3's :) Perhaps you could put it up on Sourceforge or something similar? -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 103838
Hi, All! When adding my userlogic in component editor, i can't find the singal type "burstcount". Does Altera SOPC builder 5.1 support it?Article: 103839
Jim, you are correct. With Quartus you can mix AHDL, VHDL, Verilog and schematics (bdf's) in the same project. As was pointed out earlier, if you are doing a functional simulation prior to place and route, or a timing simulation after place and route you will be able to use a VHDL or Verilog simulator, even if the sources are of different types. Quartus writes out a VHDL or Verilog netlist for the project in both cases. The thing that you cannot do in the mixed language with AHDL case is behavioral simulation prior to place and route. - Subroto Datta Altera Corp. "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:448dc77d$1@clear.net.nz... > Andy wrote: >> I can think of several reasons Altera's own customers would want to do >> this, and that should mean that Altera should want to too. >> >> For enterprises that have standardized on vhdl/verilog design >> methodology, yet have legacy AHDL code for which they don't want to >> throw away and completely start over. > > I've assumed Altera allows mixed-source projects : so you do not have > to re-code the AHDL much at all. > Someone in Altera can correct that, if I am wrong ? > > Of course, new projects should always have a language review, to choose > the best tools to get the job done. > > -jg > >Article: 103840
Daniel O'Connor <darius@dons.net.au> wrote: > Eric wrote: > > I was about to start hacking on xc3sprog after e-mailing the author and > > not hearing back, but I was curious if anyone else has done the same. > > I'm interested in adding programmatic support for the spartan-3 > > USER1/USER2 instructions, as well as getting it to program my > > coolrunner-II CPLD and Virtex-4 LX. Before I reinvent the wheel, has > > anyone else done this? > I've modified it to run under FreeBSD (pretty trivial changes) but nothing > more (since I'm only using Spartan 3's :) > Perhaps you could put it up on Sourceforge or something similar? Yes, Sourceforge would be a good place. I have changes to recognise different adapters ( Xilinx parallel, Altera Byteblaster and the MPSSE machine of an FT2232 USB Adapter). -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 103841
bart wrote: > oneweek wrote: > > you can try lattice semi for a fraction of cost, only restriction is > > you have to use their FPGA, but not bad at all. > > > ModelSim is included with shipments of Lattice's ispLEVER base > software, which you can purchase (Windows part number: > LS-HDL-BASE-PC-N) from the Lattice online store for $495 at > http://www.latticesemi.com/store/software.cfm > > Regards, > Bart Borosky, Lattice if you use verilog I suggest you to try icarus verilog :http://www.icarus.com/eda/verilog. and the wave viewer you can use wave 1.0 : www.iss-us.com I think they are quite good. They are free and in my opinion they are veru good. FrancescoArticle: 103842
> Quartus FIXEDPC $2k license covers windows modelsim > for vhdl or verilog. > One year limit only applies to updates -- tools keep working. Are you sure about that Mike, I thought they changed the licencing model a while ago so Modelsim only works for 18 months now. Nial.Article: 103843
Hi everybody,
I just tried to minimize a simple statemachine with ISE8.1 and wondered
that there is no effect, while the machine itself is an ideal target for
state minimization. (It's a lecture example fur just that purpose)
I tried several synthesis properties with no effect.
Anyone knows how to do state minimizing with ISE, or what the reasons
are for not minimizing the given FSM? It works with Design Compiler!
Best regards
Eilert
-- example FSM source
-- analyzes a serial bitstream and
-- detects non-BCD values in 4-bit segments (tetrades)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY pseudotetradedetector IS
PORT (
X : IN STD_LOGIC;
Reset : IN STD_LOGIC;
CLK : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END pseudotetradedetector;
ARCHITECTURE ptd_2p OF pseudotetradedetector IS
TYPE state IS (S0, S1, S2, S3, S4, S5, S6, S7,
S8, S9, S10, S11, S12, S13, S14);
SIGNAL cs,ns : state;
BEGIN
PROCESS (Reset, CLK)
BEGIN
IF Reset = '1' THEN
cs <= S0;
ELSIF rising_edge(CLK) THEN
cs<= ns;
END IF;
END PROCESS;
process(cs,x)
BEGIN
CASE cs IS
WHEN S0 => IF (X = '0') THEN
Y <= '0';
ns<= S1;
ELSE
Y <= '0';
ns<= S2;
END IF;
WHEN S1 => IF (X = '0') THEN
Y <= '0';
ns<= S3;
ELSE
Y <= '0';
ns<= S4;
END IF;
WHEN S2 => IF (X = '0') THEN
Y <= '0';
ns<= S5;
ELSE
Y <= '0';
ns<= S6;
END IF;
WHEN S3 => IF (X = '0') THEN
Y <= '0';
ns<= S7;
ELSE
Y <= '0';
ns<= S8;
END IF;
WHEN S4 => IF (X = '0') THEN
Y <= '0';
ns<= S9;
ELSE
Y <= '0';
ns<= S10;
END IF;
WHEN S5 => IF (X = '0') THEN
Y <= '0';
ns<= S11;
ELSE
Y <= '0';
ns<= S12;
END IF;
WHEN S6 => IF (X = '0') THEN
Y <= '0';
ns<= S13;
ELSE
Y <= '0';
ns<= S14;
END IF;
WHEN S7 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '0';
END IF;
ns <= S0;
WHEN S8 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '1';
END IF;
ns <= S0;
WHEN S9 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '1';
END IF;
ns <= S0;
WHEN S10 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '1';
END IF;
ns <= S0;
WHEN S11 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '0';
END IF;
ns <= S0;
WHEN S12 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '1';
END IF;
ns <= S0;
WHEN S13 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '1';
END IF;
ns <= S0;
WHEN S14 => IF (X = '0') THEN
Y <= '0';
ELSE
Y <= '1';
END IF;
ns <= S0;
WHEN OTHERS => Y <= '0';
ns <= S0;
END CASE;
END PROCESS;
END ptd_2p;
Article: 103844Thanks Peter, I will try this route instead solving an unsolvable problem, which took me about a month without any progress. Cheers, GuruArticle: 103845
Hi austin, Generally what is the budget we give for Logic and Routing delays respectively? Regards, Prav Aurelian Lazarut wrote: > Prav, > The approach is very dependent of the root cause. > you have to investigate where your time budget is spent, logic or routing > if is on logic try to reduce the number of logic levels, pipeline, > re-balance registers, etc. > if is on routing try to floor plan, use area constraints, different > switches in map/par etc. > > Aurash > > prav wrote: > > Hi all, > > > > I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set > > up viloations). > > What are the steps to be taken to meet the frequency other than doing a > > pipeline in RTL. > > I am using Xilinx FPGA's. > > > > regards > >Article: 103846
prav wrote:
>Hi austin,
>
>Generally what is the budget we give for Logic and Routing delays
>respectively?
>
>
>
Prav,
the budget is your clock period minus setup and hold (assuming SDR)
Aurash
>Regards,
>Prav
>Aurelian Lazarut wrote:
>
>
>>Prav,
>>The approach is very dependent of the root cause.
>>you have to investigate where your time budget is spent, logic or routing
>>if is on logic try to reduce the number of logic levels, pipeline,
>>re-balance registers, etc.
>>if is on routing try to floor plan, use area constraints, different
>>switches in map/par etc.
>>
>>Aurash
>>
>>prav wrote:
>>
>>
>>>Hi all,
>>>
>>>I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set
>>>up viloations).
>>>What are the steps to be taken to meet the frequency other than doing a
>>>pipeline in RTL.
>>>I am using Xilinx FPGA's.
>>>
>>>regards
>>>
>>>
>>>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 103847> Yes, Sourceforge would be a good place. > I've created the sf project as xc3sprog -- I think with all these additions we've expanded the program a bit from what its original purpose was, but there seems to be no harm in keeping the name. Evidently SF will be contacting me in a day or two saying they've set up the project, at which point I'll upload the code and we can start accepting patches. Does anyone else want admin bits on the site? ...EricArticle: 103848
The general rule for Xilinx devices (others may be similar) is 50% routing, 50% logic. If you're 70% routing, chances are the place & route can give better results. If you have 43% routing, there's a strong chance you won't get better results, at least easily. prav wrote: > Hi austin, > > Generally what is the budget we give for Logic and Routing delays > respectively? > > Regards, > Prav > Aurelian Lazarut wrote:Article: 103849
Most projects I've been on that used legacy code still had to modify the code somewhat to suit the new use. Modifying legacy code in AHDL is not a good solution for us, since the reviewers are not AHDL literate (not that its that hard to understand), and it cannot be simulated on 3rd party simulators, except at the gate level, which is painfully slow. I don't see where Altera would lose customers if they had the capability to convert AHDL to VHDL/verilog. They could put the same type of copyright restrictions in the code that Xilinx does if they wish. Andy Jim Granville wrote: > Andy wrote: > > I can think of several reasons Altera's own customers would want to do > > this, and that should mean that Altera should want to too. > > > > For enterprises that have standardized on vhdl/verilog design > > methodology, yet have legacy AHDL code for which they don't want to > > throw away and completely start over. > > I've assumed Altera allows mixed-source projects : so you do not have > to re-code the AHDL much at all. > Someone in Altera can correct that, if I am wrong ? > > Of course, new projects should always have a language review, to choose > the best tools to get the job done. > > -jg
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z