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I will be using Vertex 4 (LX60) in my project this chip has two pins TDN_0 and TDP_0 which are supposed to be connected to temperature sensing diode. Can I leave them unconnected? If not what sort of diode should it be? Thank you. Vassili SavinovArticle: 104051
"Vassili Savinov" <vassili.savinov@sharp.co.uk> wrote in message news:ee9c73e.-1@webx.sUN8CHnE... >I will be using Vertex 4 (LX60) in my project this chip has two pins TDN_0 >and TDP_0 which are supposed to be connected to temperature sensing diode. >Can I leave them unconnected? If not what sort of diode should it be? > > Thank you. Vassili Savinov First, read the Xilinx literature. You'll see that those two pins ARE the sensing diode. They indicate what the FPGA junction temperature is. BobArticle: 104052
Static Timing Analysis. It's nearly impossible to prove that a design will work with simulation. Static Timing Analysis is a simulation-less proof mechanism. The tool uses clock periods and setup and hold times and propagation delays of the hardware to prove it a design will meet a specified timing. A digital design flow should go basically like this: 1=2E Specify and make list of features. 2=2E Implement RTL. 3=2E Write functional simulations to test features exhaustively. 4=2E Test features. 5=2E Write design constraints. 6=2E Synthesize. 7=2E Run Static Timing. 8=2E Do timing fixes if necessary, go back to step 4. 9=2E Tape out or do whatever you need to do with your complete design. The point is you should never need to run timing sims. That said, I've never worked on a chip that didn't need them. All I can say is that you almost can't guarantee a circuit to be working through timing gate sims. -Arlen GaLaKtIkUs=99 wrote: > Mike Treseler wrote: > > GaLaKtIkUs=99 wrote: > > > Rewrite the whole libraries, which model Xilinx primitives for all > > > Xilinx FPGA/CPLD families and all speed grades? > > > > No. > > Leave the primitives to synthesis. > > Leave the timing to STA. >=20 > STA? >=20 > >=20 > > -- Mike TreselerArticle: 104053
Eric Smith schrieb: > "Bluespace Technologies" <bluespace@rogers.com> writes: > > I'm trying to use the sample pictiva VHDL code from Avnet to drive a mini > > OLED (OSRAM Pictiva 128x64 pixel) on their test board, to get anything > > presented (numerical data) on the screen. Has anyone got this device to > > work, using sample code or other? > > I haven't tried yet. I am somewhat pissed off that the datasheet on the > controller chip in the module is apparently nearly impossible to obtain, and > the data sheet on the module doesn't give the details of the interface other > than electrical parameters. datasheet for the controller IC http://www.mikrocontroller.net/attachment.php/347504/Treiber_IC-SSD0323_OLED_128x64_GELB.pdf its all on the net :) AnttiArticle: 104054
Vassili, The diode pins are subject to ESD damage if they do not get connected to anything. So we recommend grounding them if not used. That way if at some point in the future, you wanted to use them, it is unlikely they would be bad. The diode is just a lateral pnp transistor emitter base junction, and is designed to be used with the two current switched sensors sold for Penitums by National, Micrel, and others. We try to make the ideality factor, and series resistance the same as a Pentium 3, but we are only close to, not at, the values. This results in a 1 or 2 degree C offset and error over temperature. The Rs and I factors are in the datasheet, and can be used with some temp sensor ICs where these two factors can be programmed in. Austin http://www.national.com/pf/LM/LM63.html http://www.edn.com/article/CA307863.html Vassili Savinov wrote: > I will be using Vertex 4 (LX60) in my project this chip has two pins TDN_0 and TDP_0 which are supposed to be connected to temperature sensing diode. Can I leave them unconnected? If not what sort of diode should it be? > > Thank you. Vassili SavinovArticle: 104055
sjulhes wrote: > Thank you for your answers. > > But the fact is that in our electronic department we design > development kit boards for main ARM processors used with Win CE ( > AT91, NADIA, XSCALE, Samsung 2SC2412 and others .. ) and the > associated BSP in our software departement. > > The idea, here in the FPGA department, is to use the power of the > Xilinx's System On Chip capabilities, to offer a custom system like > the ones designed for the WIN CE platforms. The optimal way would be > to have a synthetizable ARM7/9 core to link it to a SOC in the FPGA. > > Second way would be to find an ARM core with no peripherals in a > external chips and connect it to the FPGA. > > For now I didn't find anything like this. > Why not check out the WebNet module from www.iotech.dk Combines an AT91RM9200 and a Spartan - 3 FPGA. Have some more info on ARM9 + FPGA boards but that cannot be distributed here just yet. > Stéphane. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 104056
"Peter Alfke" <peter@xilinx.com> wrote in message news:1150482515.162859.122140@y41g2000cwy.googlegroups.com... > Check whether there really is any difference between LVTTL and LVCMOS. > LVTTL inherited a Vohmin specification of 2.4 V from a 40-year old T.I. > specification. Today this has no connection to reality, since in CMOS > the output pulls to the rail, irrespective of any specification. Since > it exceeds the spec, everybody is happy to comply with LVTTL... > The difference between LVTTL and LVCMOS is really just a numbers game > and has nothing to do with physical reality. > Peter Alfke You're quite right. The original CMOS (4xxx) and TTL (74xxx) chips had different outputs in terms of voltage, drain and source current. These differences don't seem to apply to Xilinx FPGA's, and that is a little bit confusing.Article: 104057
"Daniel O'Connor" <darius@dons.net.au> wrote in message news:1150154713_9586@pnews.internode.on.net... > John Smith wrote: > > When I discover en error in one of your products, and there is no way what > > so > > ever tha I can get in touch with you, I gett pissed off ! You must have > > some sort of customer service, anything else is just stupid.. > > http://www.xilinx.com > Click on 'Support' > Click on 'WebCase' (scroll down a bit to see it) > Login and enter your complaint. > > If you're going to spit the dummy over the fact you have to use a web > browser instead of an email client, well.. grow up. > > Also, as someone else said, if you don't supply any useful information it's > impossible to help you. I don't think you quite understand the issue. I have tried to join Xilinx support, but I got an email stating that I could not do that. And when I was pissed off by that, all I got in reply from an apparently Xilinx employee at this newsgroup was that I had to spend real money to get support from Xilinx. Well, I spent $600 . That's real money to me. Xilinx is way out of line in terms of customer service. And arrogant messages on news don't shape up their apperance either.Article: 104058
I stand corrected: it's a PIC rather than an AVR but this doesn't change much. For the "disk data" to serial application there is no need for external SRAM: at 230K serial rate you can dump the bytes faster than they come assuming the "double density" floppy format. pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > Alex Freed <alexf@mirrow.com> wrote: > > >>I remember seeing someone already did it, but with a microcontroller >>rather than an FPGA. Google for "semi-virtual disk". It is using an >>Atmel AVR uC to simulate a floppy. Works for both FM and MFM formats. > > > http://www.thesvd.com/ > > Seems to be a PIC 16C65b @ 20MHz + 256kByte sram in essence. > > Schematic+PCB: > http://www.thesvd.com/SVD/Downloads/SVD-Instructions.pdf >Article: 104059
If people like the LVTTL standard, we don't want to disappoint them. Its Vohmin spec of 2.4 V is derived from the original 5-V Vcc bipolar totem-pole outputs which usually have two diode driops below Vcc. And at 4.5 V and -55 degrees that can, worst-case, result in a 2.4 V output High voltage. Dictated T.I. fourty years ago. Today we don't use 5 V, and we don't use bipolar circuitry anymore, but this old number just hangs around and confuses designers who might hardly know what TTL really stands for. Except for the special cases of LVDs and CML, each CMOS output today has a bunch of n-channel transistors that pull to GRND and a bunch of p-channel transistors that pull to Vcc. The standards then differ in the number of transistors in the bunch being activated. (And the "c" in Vcc means "collector" , another bipolar anachronism. Even a young industry like ours carries a lot of historical baggage...) Peter Alfke John Smith wrote: > > > You're quite right. The original CMOS (4xxx) and TTL (74xxx) chips had > different outputs in terms of voltage, drain and source current. These > differences don't seem to apply to Xilinx FPGA's, and that is a little bit > confusing.Article: 104060
John, you just misunderstood what Austin wrote, before this thread derailed, He wrote: "Spending Real money for a product makes you a customer (not a student)". That means: "Because you have spent real money, you are a customer, not a student, and Xilinx will treat you as a real customer". Austin meant to be positive and re-assuring. John, I suppose we are both using a language here that is not our native one, therefore we must be careful not to draw hot-tempered wrong conclusions. Your interpretation of Austin's single phrase was 180 degrees out of phase with its intended meaning. Get on your boat and enjoy the Norwegian summer ! Peter Alfke ==================== John Smith wrote: > > I don't think you quite understand the issue. I have tried to join Xilinx > support, but I got an email stating that I could not do that. And when I was > pissed off by that, all I got in reply from an apparently Xilinx employee at > this newsgroup was that I had to spend real money to get support from > Xilinx. Well, I spent $600 . That's real money to me. > Xilinx is way out of line in terms of customer service. And arrogant > messages on news don't shape up their apperance either.Article: 104061
Austin Lesea wrote: > I still have no idea why this matters whatsoever, > It makes a big difference for the convenience of use for multiple engineers or multiple computers, or for those making only a few boards with large devices. The cost of the full software license is little compared to an order of a hundred large FPGA devices - but the cost of several licenses (other engineers trying it out, or doing work on a home computer or laptop while travelling) compared to a small evaluation board is quite significant. Free tools means a freedom from having to keep track of what licensing you have here and there, and freedom from having to buy (or borrow - distributors can easily "lend" out evaluation licenses) the right licenses for the right people and the right computer. This convenience can often be more significant than the cost of the software. > Sorry, > > Austin > > Tommy Thorn wrote: > >> mk wrote: >> >>> Austin, >>> I think you misunderstand. The post was about "largest part WITH free >>> tool support". According to the op, now A seems to be winning this >>> contest and he wanted to see if X would up the ante. You're right, I >>> don't think anyone is asking for LX200 to be supported by free tools >>> but something larger than S3E 1600. How about it? >> >> >> Thanks, that's exactly what I was asking. I see now that I was unclear >> and I unfortunately didn't realize that Austin had misunderstood. All I >> was suggesting was for some of the Virtex 5 parts (larger than 70k LUT4 >> equiv.) to have free tool support (3S5000 would only be a narrow win >> over). >> >> It's not just a urination contest, it has real implications. >> >> Updating the score board (LUT4 / total memory): >> >> Altera: 68k / 1.2Mb (EP2C70) >> Lattice: 48k / 0.5Mb (ECP2-50) >> Xilinx: 33k / 0.9Mb (3S1600E) Highest memory to LUT ratio >> Actel: 25k / 0.1Mb (A3P1000) Adjust the 25k; this is LUT3 based >> Atmel: ? >> >> Tommy >>Article: 104062
Tommy Thorn wrote: > mk wrote: >> Austin, >> I think you misunderstand. The post was about "largest part WITH free >> tool support". According to the op, now A seems to be winning this >> contest and he wanted to see if X would up the ante. You're right, I >> don't think anyone is asking for LX200 to be supported by free tools >> but something larger than S3E 1600. How about it? > > Thanks, that's exactly what I was asking. I see now that I was unclear > and I unfortunately didn't realize that Austin had misunderstood. All I > was suggesting was for some of the Virtex 5 parts (larger than 70k LUT4 > equiv.) to have free tool support (3S5000 would only be a narrow win > over). > > It's not just a urination contest, it has real implications. > > Updating the score board (LUT4 / total memory): > > Altera: 68k / 1.2Mb (EP2C70) > Lattice: 48k / 0.5Mb (ECP2-50) > Xilinx: 33k / 0.9Mb (3S1600E) Highest memory to LUT ratio > Actel: 25k / 0.1Mb (A3P1000) Adjust the 25k; this is LUT3 based > Atmel: ? > > Tommy > Altera's free tools also support the smallest Stratix II - while it is not as big as the EP2C70, the EP2S15 (15k / 0.4 Mb) at least gives you the chance to try out your designs in a high-end device.Article: 104063
Dear All,
As a beginner of IC designer, I was confused with PAD connector,
why should we use
PAD for top's pin. For increasing its driving or what? what kind of
book/reference can I study for
making sense as a IC designer ? Thanks a lot.
kelvin
Article: 104064Mike Treseler wrote: > GaLaKtIkUs™ wrote: > >> I wanted to use Icarus but I was confronted to a big problem (as a user >> of Xilinx): in the simlation libraries there are specify blocs and >> Icarus verilog doesn't support them. > > Could you write your own code > and not use the libraries? Ugh! There is no need for that. As I said already on this thread, Icarus Verilog will (should) parse and ignore specify blocks and the end result is a perfectly good simulation. All you miss in this context is back-annotation support. Any other problems simulating with Xilinx models should be posted in the bug tracking database. I *will* fix such bugs, because I do Xilinx work with Icarus Verilog regularly. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 104065
Falk Brunner schrieb: > vans schrieb: >> What is the best way to convert a differential DVI signal to single >> ended for use in an FPGA? (My FPGA does not support differential I/O) >> >> I was thinking high speed op amp in unity gain, but unsure of this as >> I'm not an analog circuit buff. > > > First, there are dedicaded differential to single ended converter ICs. > Second, they wont work at thoses DVI speeds (370 Mbit/s??). They can: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3606 Note that your signal loading probably is lower than the worst case spec in the datasheet, so you can reliably overclock. I do not know much about DVI. But if it has a DC-balanced encoding you could also AC couple to a single ended input with sufficiently low voltage swing. (e.g. GTL) You only need a capacitor and a resistor per pin. Of course you lose the noise immunity of LVDS in the process. Kolja SulimmaArticle: 104066
Peter Alfke schrieb: > (And the "c" in Vcc means "collector" , which one? ;-) KoljaArticle: 104067
Both. The rule was (is): Vc describes the actual collector voltage, which usually is a variable. Vcc describes the source of that coltage, the power supply voltage. See also Vgg and Vdd,same reasoning. Peter Alfke, playing historian... Kolja Sulimma wrote: > Peter Alfke schrieb: > > (And the "c" in Vcc means "collector" , > which one? > ;-) > > KoljaArticle: 104068
Please excuse an uninformed question: HDTV has roughly 2 million pixels times 60 Hz = >120 million pixels per second Each pixel uses 24 bits. That's a traffic of roughly 3 gigabits per second. How do you handle this? how many bits and device pins in parallel ? Peter Alfke, getting lost in the 3-letter acronyms. ===========================================Article: 104069
On 18 Jun 2006 12:24:23 -0700, "Peter Alfke" <alfke@sbcglobal.net> wrote: >Please excuse an uninformed question: > >HDTV has roughly 2 million pixels times 60 Hz = >120 million pixels per >second >Each pixel uses 24 bits. That's a traffic of roughly 3 gigabits per >second. > >How do you handle this? how many bits and device pins in parallel ? SATA II does 3 Gb/s and PCIE II does 5 Gb/s so with either a single pair of wires should do the trick. Ain't the current low voltage differential signalling standards great ? PS the HDMI 1.2 supports 5 Gb/s over a single pair too and probably that's what you will get for HDTV support.Article: 104070
Peter Alfke schrieb: > Please excuse an uninformed question: > > HDTV has roughly 2 million pixels times 60 Hz = >120 million pixels per > second > Each pixel uses 24 bits. That's a traffic of roughly 3 gigabits per > second. > > How do you handle this? how many bits and device pins in parallel ? http://de.wikipedia.org/wiki/Digital_Visual_Interface http://de.wikipedia.org/wiki/Transition_Minimized_Differential_Signaling Regards FalkArticle: 104071
ghelbig@lycos.com wrote: > Odds are, this equipment is way too old to have a 3.5" floppy -or- an > IDE port. Most likely, it's a 5.25" inch drive, mayby FAT12 360K, > mayby not. > I suppose I should have mentioned that the drive in question is actually a 3.5" floppy. I'm not sure whether there's a spare IDE port however. It also runs some DOS variant.Article: 104072
Falk, I had checked that, but my question was: how much of the traffic is done in parallel? If it is all done serially, then 3 to 5 Gbps can only be done by dedicated "Multi-gigabit transceivers" and then only with encoding methods that guarantee transitions, like 8B/10B. One track per color would decrease the speed by a factor 3, and that would get us at the bleeding edge of LVDs interfaces on some FPGAs. The number of different FPGAs than can support this type of interface is limited, but the original poster remarked that his FPGA doesnot even support differential signaling. Something does not hang together here... Peter ======= Falk Brunner wrote: > Peter Alfke schrieb: > > Please excuse an uninformed question: > > > > HDTV has roughly 2 million pixels times 60 Hz = >120 million pixels per > > second > > Each pixel uses 24 bits. That's a traffic of roughly 3 gigabits per > > second. > > > > How do you handle this? how many bits and device pins in parallel ? > > http://de.wikipedia.org/wiki/Digital_Visual_Interface > http://de.wikipedia.org/wiki/Transition_Minimized_Differential_Signaling > > Regards > FalkArticle: 104073
In article <1150658663.022634.176120@r2g2000cwb.googlegroups.com>, Peter Alfke <alfke@sbcglobal.net> wrote: >Please excuse an uninformed question: > >HDTV has roughly 2 million pixels times 60 Hz = >120 million pixels per >second >Each pixel uses 24 bits. That's a traffic of roughly 3 gigabits per >second. > >How do you handle this? how many bits and device pins in parallel ? One pin-pair per colour channel, sending 8->10-encoded data at up to 1650Mbps. There's one shielding wire per pair of colour channels, and a differential clock also. I've no idea what the signalling protocols look like. Some kinds of HDTV set (as opposed to computer monitor) encrypt the data with a stream cipher, though that only has to run at the pixel rate rather than the bit rate. For the very high resolutions (2048x1536 and above), DVI goes to two pin-pairs per channel and so up to about 4Gbps. TomArticle: 104074
Peter Alfke schrieb: > Falk, I had checked that, but my question was: how much of the traffic > is done in parallel? That all I found so quick. > If it is all done serially, then 3 to 5 Gbps can only be done by > dedicated "Multi-gigabit transceivers" and then only with encoding > methods that guarantee transitions, like 8B/10B. > One track per color would decrease the speed by a factor 3, and that Looks like thats all. > would get us at the bleeding edge of LVDs interfaces on some FPGAs. > The number of different FPGAs than can support this type of interface > is limited, but the original poster remarked that his FPGA doesnot even > support differential signaling. > Something does not hang together here... Right. Regards Falk
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