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On Thu, 15 Jun 2006 20:53:04 -0700, Adam Megacz <megacz@cs.berkeley.edu> wrote: > >Here's how you would do this in an ASIC (see page 6, top left slide) > > http://www.cl.cam.ac.uk/Teaching/Lectures/compwoclocks/selftimed.4up.pdf > >The four transistors on the right basically measure the voltage >difference between the two NAND outputs, watching for them to be >separated by at least Vth. There's another version where you use >high-threshhold gates instead. > >Obviously you can't reproduce exactly this circuit in an FPGA. I'm >just posting this to show the thing I'm trying to imitate. > > - a > I think the following is a useful reference on Seitz arbiters: http://caltechcstr.library.caltech.edu/273/00/5212-TR-86.pdfArticle: 103976
hi all.. like there is library for opb, opb_ipif_v3_01_a... what and where is the library for lmb.. also with this if anyone has any idea about all lmb ports... then please reply... thanks in advance cheers SAVSArticle: 103977
Hi all, as many of you may know after all my posts, I'm working with a Spartan3 in the FT256 BGA package. Could anyone give me a link or something on documentation that may help me routing all those pins out in that kind of package with a 4-6 layer board. I'd like to get some examples or guidelines related to the most common approach adopted by experienced people. Thanks, MarcoArticle: 103978
"kia rui" <krbyxtrm@gmail.com> wrote in message news:1150312807.015662.272400@f6g2000cwb.googlegroups.com... > Is LVTTL or LVCMOS can be used for PCI Signaling? > BTW, I'm using Atera MAX-II EPM1270T144C5... > > - kai - > Depends on the - Physical size of the PCI bus - Number of loads - PCI bus speed (33 or 66 MHz) But in some situations LVTTL can be used with no problem. KJArticle: 103979
Hi Marco, http://groups.google.com/groups?q=PCBs+for+modern+FPGAs HTH, Cheers, Syms. "Marco" <marco@marylon.com> wrote in message news:1150451628.497499.313150@f6g2000cwb.googlegroups.com... > Hi all, > as many of you may know after all my posts, I'm working with a Spartan3 > in the FT256 BGA package. Could anyone give me a link or something on > documentation that may help me routing all those pins out in that kind > of package with a 4-6 layer board. I'd like to get some examples or > guidelines related to the most common approach adopted by experienced > people. > Thanks, > Marco > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103980
Marco wrote: > Hi all, > as many of you may know after all my posts, I'm working with a Spartan3 > in the FT256 BGA package. Could anyone give me a link or something on > documentation that may help me routing all those pins out in that kind > of package with a 4-6 layer board. I'd like to get some examples or > guidelines related to the most common approach adopted by experienced > people. > Thanks, > Marco I have been doing it last 6 years or so on 1.27 mm pitched BGAs on two signal layers (top and bottom), planes as necessary (actually 6 in all cases so far), 3 lines between BGA pads, pitched 10 mils (say, 5 mils trace and 5 mils gap, these may vary to 4-6 or 6-4). Pad to gap is 5 or even 4 mil, drilling is 0.3mm or 0.2mm (I leave this choice to the PCB house). I drill each BGA pad so I can have access to all signals since my borads are typically expected to begin to work and sell from revision 1; I have posted some info before on how to avoid problems with the drilled BGA pads. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 103981
Marco,
try this
http://www.xilinx.com/bvdocs/appnotes/xapp157.pdf
Aurash
Marco wrote:
>Hi all,
>as many of you may know after all my posts, I'm working with a Spartan3
>in the FT256 BGA package. Could anyone give me a link or something on
>documentation that may help me routing all those pins out in that kind
>of package with a 4-6 layer board. I'd like to get some examples or
>guidelines related to the most common approach adopted by experienced
>people.
>Thanks,
>Marco
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 103982>I am not sure if anyone is still reading this, but I've tested >the ADC with worrying results. When I apply a sine wave to the input >of the ADC with no SCLK or CS signal from FPGA, I can clearly >see the sinewave on an oscilloscope. When I then use the FPGA >to drive the CS and SCLK pins, the pure sine wave input to the >ADC is no longer visible on the scope. What I see instead is what >appears to be a bouncing noisy signal with sharp peaks and troughs. >Similarly the ADC output consists of sharp periodic spikes. My SLCK >and CS signals don't look very clean on the scope. How can I improve >the quality of these if I need to drive the ADC from the FPGA? What >else should I consider to resolve this problem? What does your signal looks like if you remove the probe. And put the adc inside a shielded box..? Other than that: * Trace lengths equally long? * Trace impedance * Termination resistors * Analog/Digital seperation for power and groundplane * Shielding (possible even a shielding barrier between analog & digital) * Radiated energy? wire=antenna.. * Enough power, ripple issues * Faulty componentArticle: 103983
Hello, I am doing some Excel timing analysis of asynchronous interface. I am finding difficult in formulating the formula for HOLD time margin. Write Transaction: Setup margin (flash) = Control strobe time (Max) - Input setup requirement of the receiver (Flash) + control trace delay- data trace delay what about Hold margin? Read Transaction: Setup margin (processor) = Control strobe time (Max) - Input setup requirement of the receiver (processor) + control trace delay- data trace delay what about Hold margin? I am tabulating for different value of Control and Data trace. Any help will be great. Thanks and regards PraveenArticle: 103984
Brian Davis wrote: > johnp wrote: > > Does anyone know if similar clocking is available on the V2Pro parts? > Yes. > > > Any pointers to documentation? > > Other than XAPP609, I know of: > - the phantom XAPP769 for S3 local clocks > - manual inspection in FPGA Editor > - the perl script in Answer Record 17697 : > How do you determine I/O locations for Local Clock Routing > according to XAPP609? For "Data Capture and Transfer" applications mentioned in tha app notes, you may want to take a look at ADEPT (http://home.comcast.net/~jimwu88/tools/adept/). The tool displays graphically which pins can be used for local clocks and which pins can be driven by a local clock pins. HTH, JimArticle: 103985
>I have been doing it last 6 years or so on 1.27 mm pitched BGAs >on two signal layers (top and bottom), planes as necessary (actually >6 in all cases so far), 3 lines between BGA pads, pitched 10 mils >(say, 5 mils trace and 5 mils gap, these may vary to 4-6 or 6-4). >Pad to gap is 5 or even 4 mil, drilling is 0.3mm or 0.2mm (I leave >this choice to the PCB house). I drill each BGA pad so I can have >access to all signals since my borads are typically expected >to begin to work and sell from revision 1; I have posted some >info before on how to avoid problems with the drilled BGA pads. I saw you'r doing radioactive measurement equipment. How do you handle the fpga sensitivity to radiation ..?Article: 103986
Antti wrote: > > But what I found VERY VERY interesting is the fact that CoreConsole > uses SPIRIT XML standard for the IP parametrization and interconnect > description. > Apologies for my ignorance on this, but why is this significant? Ed McGettigan -- Xilinx Inc.Article: 103987
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > >I have been doing it last 6 years or so on 1.27 mm pitched BGAs > >on two signal layers (top and bottom), planes as necessary (actually > >6 in all cases so far), 3 lines between BGA pads, pitched 10 mils > >(say, 5 mils trace and 5 mils gap, these may vary to 4-6 or 6-4). > >Pad to gap is 5 or even 4 mil, drilling is 0.3mm or 0.2mm (I leave > >this choice to the PCB house). I drill each BGA pad so I can have > >access to all signals since my borads are typically expected > >to begin to work and sell from revision 1; I have posted some > >info before on how to avoid problems with the drilled BGA pads. > > I saw you'r doing radioactive measurement equipment. How do you handle the > fpga sensitivity to radiation ..? I don't. For two reasons - one, because the measuring equipment does not experience any radiation of concern. Often the levels measured are below the natural background, and the detector is placed in a lead shield with 10+ cm walls... There are also high count rate applications, but it is the detector which sees the counts, not the analyzer (several meters cable). Second, I only use CPLDs, not FPGAs, in my equipment.... :-) :-). (I use Coolrunners). Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 103988
pd, Spartan 3 latest atmospheric neutron readout is 6.3 FIT/Mb. It is still decreasing. The LANSCE cross sections were less than half V2. S3 is not recommended for heavy ion applications (space) as there is no mil version with epi wafer. CERN uses our parts to instrument their beams. Many labs use our parts. Unless they are actually near the beam, there is no radiation issue. If they are near the beam, total dode, and upsets, can be determined, and then mitigated by design. I leave you with the following: Xilinx FPGAs today allow the engineer to design to, and meet, any arbritrary MTB or FIT rate through the use of various techniques. Doing this some other way is extremely painful, and can not be verified until you are completely finished (when it is too late). For example, when you think you have a robust design, we have a tool which can go and change individual bits, one by one, or at random. With beam time at more thanb $400 an hour, it is a lot cheaper to verify resiliance to upsets on your bench where you can find it, and then fix it. Austin pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >>I have been doing it last 6 years or so on 1.27 mm pitched BGAs >>on two signal layers (top and bottom), planes as necessary (actually >>6 in all cases so far), 3 lines between BGA pads, pitched 10 mils >>(say, 5 mils trace and 5 mils gap, these may vary to 4-6 or 6-4). >>Pad to gap is 5 or even 4 mil, drilling is 0.3mm or 0.2mm (I leave >>this choice to the PCB house). I drill each BGA pad so I can have >>access to all signals since my borads are typically expected >>to begin to work and sell from revision 1; I have posted some >>info before on how to avoid problems with the drilled BGA pads. > > > I saw you'r doing radioactive measurement equipment. How do you handle the > fpga sensitivity to radiation ..? >Article: 103989
Have you checked the power supplies and ground to the ADC? This
sounds like a weird problem, so look at something odd in the
design. I doubt that the CS and SCLK signals could cause the
ADC to act like this unless there is something screwed up in how
the ADC is hooked up.
Also...
- your are using good grounding on the scope probe, right?
- if you're using a digital scope, you're sampling at a high enough
frequency to avoid aliasing? I've seen truly odd waveforms from
digital scopes if they're used improperly.
Good luck!
John Providenza
m_oylulan@hotmail.com wrote:
> I am not sure if anyone is still reading this, but I've tested
> the ADC with worrying results. When I apply a sine wave to the input
> of the ADC with no SCLK or CS signal from FPGA, I can clearly
> see the sinewave on an oscilloscope. When I then use the FPGA
> to drive the CS and SCLK pins, the pure sine wave input to the
> ADC is no longer visible on the scope. What I see instead is what
> appears to be a bouncing noisy signal with sharp peaks and troughs.
> Similarly the ADC output consists of sharp periodic spikes. My SLCK
> and CS signals don't look very clean on the scope. How can I improve
> the quality of these if I need to drive the ADC from the FPGA? What
> else should I consider to resolve this problem?
>
> Thanks,
>
> Mees
Article: 103990
Hi all,
I am doing a DDR SDRAM design which is obtained using the MIG tool.
The target device is V4LX60. But in that i observed a problem that the
controller is using differntial clocking. And IBUFGDP is used to buffer
the clcok. The problem is controller needs two differential clcok
signals. But the demo board support only one. Tried to assign the same
clock to different IBUFGDP units but in the par state it showed an
error. Is it possible to assign a differntial clcok signals to two
different buffers.
Second question is what is the risk involved in changing the RAM
controlller code to work with single ended clock. I am planning to use
160 MHz for RAM operation.
regards
Sumesh V S
Article: 103991Joseph Samson wrote: > Here is the recipe that always works for me: > I use the ISE GUI. When I have a CoreGen model instantiated in my > Verilog, ISE leaves a place for the .xco file. In your example, your > core is called sine_new, so there will be a sine_new.xco. Add that > source to your project. > > Among other files, CoreGen will generate sine_new.edn and sine_new.v . > You should place these files in same directory as your *.ise file (the > ISE project file). In general, you can't go wrong if you put every file > that CoreGen creates into the directory that has your *.ise file. > > --- > Joe Samson > Pixel Velocity Thanks for your posting. Unfortunately I did not check back in time. I experimented quite a but and discovered the same thing. I have alot of experience with Verilog/Xilinx, but have not used cores before. Also, I have not used the Xilinx tools for about 2 years and am getting re-used to the WEBPACK GUI. I have another question. I am now trying to simulate the core using the ISE simulator in Webpack 8.1 I am running into the problem that the output is always 0 no what frequency I set as the 'quiescent' frequency for this core. I know I am doing something wrong. Do you have any general observations along the lines of your reply to me? Any help with be appreciated. Best Regards, ArtArticle: 103992
>does not experience any radiation of concern. Often the levels >measured are below the natural background, and the detector Like measureing food activity I guess (or similar tasks). (So you know when you die :) >is placed in a lead shield with 10+ cm walls... There are also No RoHS here then :) >high count rate applications, but it is the detector which >sees the counts, not the analyzer (several meters cable). >Second, I only use CPLDs, not FPGAs, in my equipment.... :-) :-). >(I use Coolrunners). Yeah that pretty much solve it I guess. :-) Wonder if actel fpga that uses eeprom cells for config would be at the same radiation level as cpld..Article: 103993
I'm currently working with an old imaging device whose only output is a
floppy drive which only allows transferring 6 images at a time (due to
floppy disk size constraint). I had the idea of implementing an FDC
(floppy drive controller) on an fpga then connecting the drive cable to
the fpga and using the fpga to stream the images through a serial port
thus bypassing the disk size constraint. Can anybody comment on the
feasibility of this project and perhaps point me to some existing VHDL
code? Otherwise, does anyone have any other feasible ideas?
Thanks.
Article: 103994> > uses SPIRIT XML standard for the IP parametrization and interconnect > > Apologies for my ignorance on this, but why is this significant? SPIRIT promises to enable a plug-and-play environment for IP integration that is tool, language and platform agnostic. This allows developers to import internal or third-party SPIRIT compliant IP into various tools or flows to quickly integrate IP and build an SoC. As the SPIRIT ecosystem continues to grow more and more tool vendors and IP providers are supporting SPIRIT. SPIRIT is essentially just a way to store SoC meta-data such that files, components, component generators, memory-maps, interfaces, interconnect and abstraction levels are defined in a standard human and machine readable way (that's eXtensible). SPIRIT provides a standard way to interface between different tools, abstraction levels, companies, code generators, and teams (i.e. design, verification, validation, and documentation). Regards, Jeremy --- PDTi [ http://www.productive-eda.com ] SpectaReg -- Spec-down code and doc generation for register mapsArticle: 103995
fslearner <junkaccount616@gmail.com> wrote: >I'm currently working with an old imaging device whose only output is a >floppy drive which only allows transferring 6 images at a time (due to >floppy disk size constraint). I had the idea of implementing an FDC >(floppy drive controller) on an fpga then connecting the drive cable to >the fpga and using the fpga to stream the images through a serial port >thus bypassing the disk size constraint. Can anybody comment on the >feasibility of this project and perhaps point me to some existing VHDL >code? Otherwise, does anyone have any other feasible ideas? Implementing an fdc controller in fpga should be a piece of cake. The signal is 1 Mbps at tops asfaik. It's proberbly MFM encoded signal, otherwise it's likely GCR or FM. 1.44M/1.2M discs are 500 kbps. 720k/360k = 250 kbps. The signal consists of a pulse for every magnetic flux asfair. If you use an oscillator to count the number of clocks between these pulses. You can derive data from there. On a higher level you have to pay attention so that your host only read disc data when it has been completed, and fat is consistent. Should you erase or in other way alter "floppy" your scanner device better be aware of this. Through the signal 'discchange' wire or simply instruct it on console. Your fpga can also imitate two floppys btw, by useing the select signals. A quick approach is to add one those usb-fpga kits. And tie floppy i/o to it. Don't forgett that floppy idc36 is 5V.. ;)Article: 103996
fslearner schrieb: > I'm currently working with an old imaging device whose only output is a > floppy drive which only allows transferring 6 images at a time (due to > floppy disk size constraint). I had the idea of implementing an FDC > (floppy drive controller) on an fpga then connecting the drive cable to > the fpga and using the fpga to stream the images through a serial port > thus bypassing the disk size constraint. Can anybody comment on the > feasibility of this project and perhaps point me to some existing VHDL > code? Otherwise, does anyone have any other feasible ideas? > > Thanks. should be doable. there is one guy who has floppy disk host interface done by 100% software with some small microcontroller. So with FPGA you defenetly can do it. but I bet you need todo it all from scratch. AnttiArticle: 103997
Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com> writes: > If I may ask, what's your application for this ? Asynchronous circuits. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 103998
Brian - Thanks for the pointer to the Answer Record, unfortunately, the script dies on my machine with the following error: FATAL_ERROR:StaticFileParsers:StaticAcdRead.c:614:1.48 - ACD file .acd does not exists Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com Any ideas? Thanks! John Providenza Brian Davis wrote: > johnp wrote: > > Does anyone know if similar clocking is available on the V2Pro parts? > Yes. > > > Any pointers to documentation? > > Other than XAPP609, I know of: > - the phantom XAPP769 for S3 local clocks > - manual inspection in FPGA Editor > - the perl script in Answer Record 17697 : > How do you determine I/O locations for Local Clock Routing > according to XAPP609? > > Also, that DIFF_OUT buffer example code I posted a couple > months ago had some local clocking notes in the comments. > > The various flavor DRAM app notes may have a few more tidbits > of information, since the local clocks are used for DQS-like signals. > > BrianArticle: 103999
mk<kal*@dspia.*comdelete> writes:
>>Here's how you would do this in an ASIC (see page 6, top left slide)
>>
>> http://www.cl.cam.ac.uk/Teaching/Lectures/compwoclocks/selftimed.4up.pdf
>
> I think the following is a useful reference on Seitz arbiters:
> http://caltechcstr.library.caltech.edu/273/00/5212-TR-86.pdf
Thanks for posting this!
I should note that this link shows how to use the primitive
arbiter-core ("interlock") from the first paper to build a complete
arbiter (handshaking, request/grant, etc). The interlock is the box
with the funny angle-symbol in figure 3 of the second paper.
Seitz' original paper on building the full arbiter had an error, but I
am not aware of any problems with his interlock element.
The following paper claims to prove the correctness of the interlock
circuit (see figure 5 for a transistor diagram) under a pretty minimal
set of assumptions:
http://ewic.bcs.org/conferences/1996/circuits/papers/paper10.pdf
Where correctness means "Because an arbiter cannot be guaranteed to
respond correctly in any bounded amount of time, we verify liveness in
an almost surely sense -- with probability 1, the arbiter eventually
grants some pending request."
Stuff like this turns out to be a pretty big deal, since "interlocks
work properly" is one of the very few "timing" assumptions you have to
make in delay-insensitive circuits (the other being that certain
fanouts are asymmetric and that you know which side has more delay).
- a
--
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