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Hi, We have here real good skills in Windows CE software development in our software departement and I was wondering if there was any solution to get an ARM7 or ARM9 core running in a Xilinx FPGA ? Any feedbacks ? Thanks. Stéphane.Article: 103926
Hello, Thank you Duane for the pointers. I did get the first design to work on Aurora (eg. counter design). I am going to try sending the actual data. However, I have some doubts again: 1. I need to send a data pattern at a very high rate. The Aurora links transmit data at 3.125 GBits/sec ( multiplication of Bref_clk with a factor of 20 inside the DCM). I was wondering if I could access that clock and use it clock my data generator module. 2. Moreover, has anyone accessed the data sent through the Aurora links on a high speed oscilloscope. I am trying to send modulated GPS signals and hence this query. 3. I have downloaded the Aurora module and I am using it to implement the networking among a series of FPGAs. Is Aurora proprietary?? Can it be used by the industry for implementation on their products??( I want to know if it's restricted to academia use.) Thanks, Vivek Duane Clark wrote: > Vivek Menon wrote: > > Hello Duane, > > thanks for the reply. What I meant was that the constraints for clocks > > can be used for the ISE file. However I get errors while trying to > > define : > > > > INST GT_FIBRE_CHAN_INST/mgt_io/mgt_io_1 AREA_GROUP="BERT_0_GRP"; > > AREA_GROUP "BERT_0_GRP" RANGE=SLICE_X0Y0:SLICE_X33Y59; > > #---------------------------------------------------------------- > > # MGT Placement: > > #---------------------------------------------------------------- > > > > #Top MGTs > > INST GT_FIBRE_CHAN_INST LOC = GT_X1Y1; ## MGT6 > > > > Any information on this? > > When you sign up with Xilinx for the Aurora core, you will receive a > license to use in Coregen to generate a core. When you generate the > core, along with the design files, a constraints file will be generated > that has all those constraints. You will copy those constraints into > your ucf file. The core comes with docs explaining how to use it. I'll > admit that the first time you use coregen to generate an Aurora core, it > can be tricky trying to figure out what to enter, so you can ask here if > you have questions about that part.Article: 103927
Hello, Can anyone suggest a development or evaluation board with Virtex-4 Fpga having rocket IO capability? Thanks, VivekArticle: 103928
Vivek Menon wrote: > Hello, > Can anyone suggest a development or evaluation board with Virtex-4 Fpga > having rocket IO capability? > Thanks, > Vivek > What RocketIO functionality or connectivity are you looking for? Ed McGettigan -- Xilinx Inc.Article: 103929
Hi Dave, Maybe you can look at FTDICHIP website they have boards with USB connections to FPGA's http://www.ftdichip.com/Products/EvaluationKits/FPGA.htm Kind Regards, http://www.vhdl.eu "Dave Farrance" <DaveFarrance@OMiTTHiSyahooANDTHiS.co.uk> wrote in message news:c8ci82t7ns08cbn70qq5ipe5mtg8i4vua6@4ax.com... > "John Adair" wrote: > >>Have a look at this module >>http://www.enterpoint.co.uk/moelbryn/modules/usb_ps2.html in conjunction >>with our Raggedstone1 product. Basically the module is a voltage >>limiter(bus >>switch) on the USB lines leaving the logic to be implemented in the FPGA. > > Thanks to everybody that helped me in this thread. I've decided to buy > the above product. > > -- > Dave FarranceArticle: 103930
Hi, Maybe you can consider to go to the FPGA's of ACTEL they have a free ARM core for in there Mixed Signal FPGA: http://www.actel.com/products/arminfusion/ Kind regards, http://www.vhdl.eu "sjulhes" <t@aol.fr> wrote in message news:449152f8$0$29801$626a54ce@news.free.fr... > Hi, > > We have here real good skills in Windows CE software development in our > software departement and I was wondering if there was any solution to get > an ARM7 or ARM9 core running in a Xilinx FPGA ? > > Any feedbacks ? > > Thanks. > > Stéphane. >Article: 103931
Hi, Iam looking to use Virtex-4 Rocket IO capability so as to use the Aurora core and probably intercae the FPGA board to similar such boards using coaxial cables or any available interface. Thanks, Vivek Ed McGettigan wrote: > Vivek Menon wrote: > > Hello, > > Can anyone suggest a development or evaluation board with Virtex-4 Fpga > > having rocket IO capability? > > Thanks, > > Vivek > > > > What RocketIO functionality or connectivity are you looking for? > > Ed McGettigan > -- > Xilinx Inc.Article: 103932
If you migrate older designs into Quartus you may get some internal errors and the program may crash. I had dug into this some time ago to find the root cause of the crash and spoke with Altera who confirmed the problem. I just installed the most current version of Quartus and the problem is still there. So, if you run into this, look in the .QSF file and see if the following line is included: set_global_assignment -name TDO_DUMP_FILE AUTO If there is, remove it and try to build. I am not sure what versions of the Altera tools added this command, but starting with Quartus 5, it will crash the program. Hope this saves someone some time ......Article: 103933
Vivek Menon wrote: > Hello, > > Thank you Duane for the pointers. I did get the first design to work on > Aurora (eg. counter design). I am going to try sending the actual data. > > However, I have some doubts again: > 1. I need to send a data pattern at a very high rate. The Aurora links > transmit data at 3.125 GBits/sec ( multiplication of Bref_clk with a > factor of 20 inside the DCM). > I was wondering if I could access that clock and use it clock my data > generator module. In the Aurora core user guide, there is a chapter on "The Clock Interface and Clocking". Notice that there are clocks generated called USER_CLK*. You can use those clocks with any extra logic you want. At least in the user guide ug061.pdf, Figure 7-2 shows this connection. > 2. Moreover, has anyone accessed the data sent through the Aurora links > on a high speed oscilloscope. I am trying to send modulated GPS signals > and hence this query. If you have a scope capable of handling these signals, sure. People use eye diagrams on a scope to determine how much margin a link has. Also, it was my understanding that Xilinx used to have centers scattered around, at least in the US, where a company could bring in a board and check out RocketIO interfaces on their equipment. I assume they still provide that service, though I never used it myself. For myself, I tested the links by generating a known pattern on one side of the link, and had hardware detect the pattern on the other side and count bit errors. You should have no bit errors on a good link. Test your detection code by including the ability to inject an occasional deliberate error. > 3. I have downloaded the Aurora module and I am using it to implement > the networking among a series of FPGAs. Is Aurora proprietary?? Can it > be used by the industry for implementation on their products??( I want > to know if it's restricted to academia use.) It is not restricted to academia, but other than that I can't give legal advice ;) The core came with a license agreement, and despite the legalese, you should be able to figure out what is allowed.Article: 103934
>>In the Aurora core user guide, there is a chapter on "The Clock Interface and >>Clocking". Notice that there are clocks generated called USER_CLK*. You can use >>those clocks with any extra logic you want. At least in the user guide ug061.pdf, >>Figure 7-2 shows this connection. I did look at this figure but I guess I should have framed my question differently. Is the user_clk multiplied by 20 inside the DCM present inside the MGT. When I try to use a DCM to multiply it, the maximum I can shoot for is to 250 MHz. So how can I use the user_clk as it is still 156 MHz and are there any other ways to access the multiplied clk signal?? ANy pointers?? VivekArticle: 103935
I'm trying to use the sample pictiva VHDL code from Avnet to drive a mini OLED (OSRAM Pictiva 128x64 pixel) on their test board, to get anything presented (numerical data) on the screen. Has anyone got this device to work, using sample code or other? Is there an alternative way to get numerical data presented to a screen? Assuming I can get VHDL drivers for it. -AndrewArticle: 103936
Vhdl.eu wrote: > Hi, > > Maybe you can consider to go to the FPGA's of ACTEL they have a free ARM > core for in there Mixed Signal FPGA: > http://www.actel.com/products/arminfusion/ > > Kind regards, > http://www.vhdl.eu > If they are working on WindowsCE development, the Actel FPGA is not a good choice because WindowsCE need a Memory Management Unit. The ARM7 core in Actel FPGA does not provide this feature. Stéphane, Does the ARM9 has to be in the FPGA? If it doesn't have to be, you can use an ARM9 Core Tile board http://www.arm.com/products/DevTools/Versatile/CT926EJ-S.html connect to a emulation baseboard http://www.arm.com/products/DevTools/EB.html For additional logic blocks you can add extra FPGA by Logic Tile http://www.arm.com/products/DevTools/LogicTiles.html Joseph This e-mail message is intended for the addressee(s) only and may contain information that is the property of, and/or subject to a confidentiality agreement between the intended recipient(s), their organisation and/or the ARM Group of Companies. If you are not an intended recipient of this e-mail message, you should not read, copy, forward or otherwise distribute or further disclose the information in it; misuse of the contents of this e-mail message may violate various laws in your state, country or jurisdiction. If you have received this e-mail message in error, please contact the originator of this e-mail message via e-mail and delete all copies of this message from your computer or network, thank you.Article: 103937
mk wrote: > You're right, I > don't think anyone is asking for LX200 to be supported by free tools > but something larger than S3E 1600. How about it? Actually, you got that wrong, as people have, including myself. Admittedly all that I've asked for is that place, route, and bitgen be free ... Xilinx can try to make a buck or too on XST and core sales if it wants, but as I and other posters have said, we are pretty sure that costs Xilinx a lot of money in lost chip sales, and completely trashes the market for larger FPGA boards (losing more chip sales).Article: 103938
Vivek Menon wrote: > Hi, > Iam looking to use Virtex-4 Rocket IO capability so as to use the > Aurora core and probably intercae the FPGA board to similar such boards > using coaxial cables or any available interface. > I don't believe that there are any partner boards in production that do this at this time. Xilinx will be releasing two boards in July (ML405 and ML421) that will have this capability. The ML421 is similar to our ML32x series of boards with all of the RocketIO MGTs brought out to SMA connectors. The ML405 is similar to the ML40x series, but includes RocketIO MGTs brought to SMAs, SATA connectors and a SFP cage. All of these can be used for board-to-board communication with Aurora or other protocols. If you need more details your local Xilinx FAE can help you out. Ed McGettigan -- Xilinx Inc.Article: 103939
"Bluespace Technologies" <bluespace@rogers.com> schrieb im Newsbeitrag news:z8ednRZo4eugEgzZnZ2dnUVZ_tGdnZ2d@giganews.com... > I'm trying to use the sample pictiva VHDL code from Avnet to drive a mini > OLED (OSRAM Pictiva 128x64 pixel) on their test board, to get anything > presented (numerical data) on the screen. Has anyone got this device to > work, using sample code or other? > > Is there an alternative way to get numerical data presented to a screen? > Assuming I can get VHDL drivers for it. > > -Andrew the original demos including the star wars movie work on the OLED, and as there CD has all source I assume its rather simple to use the OLED? Or what problems are you having? AnttiArticle: 103940
"Vhdl.eu" <info@mobile-it.be> schrieb im Newsbeitrag news:44917270$0$10467$ba620e4c@news.skynet.be... > Hi, > > Maybe you can consider to go to the FPGA's of ACTEL they have a free ARM > core for in there Mixed Signal FPGA: > http://www.actel.com/products/arminfusion/ > > Kind regards, > http://www.vhdl.eu what Actel says "FREE" means 120USD per FPGA for ARM license fee in small qty. the do not want any small customers at all :( AnttiArticle: 103941
Xilinx has an appnote (XAPP609) describing local clocking for a Virtex2 part. The appnote describes bringing a clock for a source synchronous design into a local clock region using specific IOBs that have special local clock driving connections. Does anyone know if similar clocking is available on the V2Pro parts? Any pointers to documentation? Thanks! John ProvidenzaArticle: 103942
"Antti Lukats" <antti@openchip.org> wrote in message news:e6s84l$nq2$1@online.de... > "Bluespace Technologies" <bluespace@rogers.com> schrieb im Newsbeitrag > news:z8ednRZo4eugEgzZnZ2dnUVZ_tGdnZ2d@giganews.com... >> I'm trying to use the sample pictiva VHDL code from Avnet to drive a mini >> OLED (OSRAM Pictiva 128x64 pixel) on their test board, to get anything >> presented (numerical data) on the screen. Has anyone got this device to >> work, using sample code or other? >> >> Is there an alternative way to get numerical data presented to a screen? >> Assuming I can get VHDL drivers for it. >> >> -Andrew > the original demos including the star wars movie work on the OLED, and as > there CD has all source I assume its rather simple to use the OLED? Or > what problems are you having? > > Antti > Thanks, Where can I get those demos? Are they available online somewhere? The source code I got from the Avnet website and board CD didn't really help get me going. -AndrewArticle: 103943
Antti Lukats wrote: > "Vhdl.eu" <info@mobile-it.be> schrieb im Newsbeitrag > news:44917270$0$10467$ba620e4c@news.skynet.be... >> Hi, >> >> Maybe you can consider to go to the FPGA's of ACTEL they have a free ARM >> core for in there Mixed Signal FPGA: >> http://www.actel.com/products/arminfusion/ >> >> Kind regards, >> http://www.vhdl.eu > > what Actel says "FREE" means 120USD per FPGA for ARM license fee in small > qty. > the do not want any small customers at all :( I've always wondered how much value was in the Actel ARM the whole announcement and strategy has seemed strange to me. I just took a look at the CoreMP7 product brief (http://www.actel.com/documents/CoreMP7_PB.pdf) and on page 5 there is a list of the max MHz and the number of Tiles that the soft core takes up. Max Freq : 22.714 - 29.699 (Depends on device and if debug is supported) Tiles : 6,104 - 8,587 (Depends on device and if debug is supported) Utilization: 26.0% - 99.3% (Depends on device and if debug is supported) This seems to be well below the performance level of a Xilinx MicroBlaze or Altera NIOS-II soft core and extremely below the level of a a Xilinx PowerPC hard core with a much higher area cost. I know that there is niche out there for ARM7 prototypers, but with the performance and area cost does this even come close to a general market need? Ed McGettigan -- Xilinx Inc.Article: 103944
Francesco wrote: > bart wrote: > > oneweek wrote: > > > you can try lattice semi for a fraction of cost, only restriction is > > > you have to use their FPGA, but not bad at all. > > > > > ModelSim is included with shipments of Lattice's ispLEVER base > > software, which you can purchase (Windows part number: > > LS-HDL-BASE-PC-N) from the Lattice online store for $495 at > > http://www.latticesemi.com/store/software.cfm > > > > Regards, > > Bart Borosky, Lattice > > if you use verilog I suggest you to try icarus verilog > :http://www.icarus.com/eda/verilog. I wanted to use Icarus but I was confronted to a big problem (as a user of Xilinx): in the simlation libraries there are specify blocs and Icarus verilog doesn't support them and there are no shoft term plans to support them. Great was my deception (as open source enthusiast) but now I'm obliged to use a commercial simulator. > and the wave viewer you can use wave 1.0 : www.iss-us.com > I think they are quite good. I used gtk-wave for that. > They are free and in my opinion they are veru good. > > FrancescoArticle: 103945
Ed McGettigan wrote: > I've always wondered how much value was in the Actel ARM the whole > announcement > and strategy has seemed strange to me. I just took a look at the CoreMP7 > product brief (http://www.actel.com/documents/CoreMP7_PB.pdf) and on page 5 > there is a list of the max MHz and the number of Tiles that the soft core > takes up. > > Max Freq : 22.714 - 29.699 (Depends on device and if debug is > supported) > Tiles : 6,104 - 8,587 (Depends on device and if debug is > supported) > Utilization: 26.0% - 99.3% (Depends on device and if debug is > supported) > > This seems to be well below the performance level of a Xilinx MicroBlaze or > Altera NIOS-II soft core and extremely below the level of a a Xilinx > PowerPC > hard core with a much higher area cost. > > I know that there is niche out there for ARM7 prototypers, but with the > performance and area cost does this even come close to a general market > need? Yes, it looks more like a 'marketing tick box', than a compelling engineering argument. You can buy 70MHz ARM uC, with FLASH Code storage, for under $2, and these have quite high performance SSP interfaces - so a system that needs a FPGA ( and not a huge code base) could slave one of these, and save a lot of $$. Larger ARM uC are also available, and normally for about the same price as the FLASH + SDRAM needed to support a FPGA core would be, but with all the high memory bandwidth stuff on one chip - giving large savings in PCB area/layers/EMC. -jgArticle: 103946
"GaLaKtIkUs" <taileb.mehdi@gmail.com> writes: > I wanted to use Icarus but I was confronted to a big problem (as a user > of Xilinx): in the simlation libraries there are specify blocs and > Icarus verilog doesn't support them and there are no shoft term plans > to support them. There was a bug in the unisim libraries at one point which make ghdl (rightfully) choke: an element of an enum had the same name as a variable or a type IIRC. Maybe that is your problem? Cheers, ColinArticle: 103947
Hi Paul, Tanks for your help. I'm sorry for the late replay. I wanted to try what you suggested before answering, but din't had much time. The example programs ware very useful, and I manage to solve my problem. What I have misunderstood is that you can not configure a GPIO module as input and output simultaneously, unless you use the GPIO_IO pins. tanks again, Jos=E9 MarianoArticle: 103948
Vivek Menon wrote: >>> In the Aurora core user guide, there is a chapter on "The Clock Interface and >>Clocking". Notice that there are clocks generated called USER_CLK*. You can use >>those clocks with any extra logic you want. At least in the user guide ug061.pdf, >>Figure 7-2 shows this connection. > > I did look at this figure but I guess I should have framed my question > differently. Is the user_clk multiplied by 20 inside the DCM present > inside the MGT. When I try to use a DCM to multiply it, the maximum I > can shoot for is to 250 MHz. So how can I use the user_clk as it is > still 156 MHz and are there any other ways to access the multiplied clk > signal?? The x20 multiplier is indeed already inside the MGT, and is produced off the "dedicated" REFCLK/BREFCLK. That is why they are so picky about how you provide that clock. You don't need to provide x20 clock, and you don't have any access to it. It wouldn't do you any good; even Xilinx FPGAs won't run at 3.1GHz yet.Article: 103949
Colin Marquardt wrote: > "GaLaKtIkUs" <taileb.mehdi@gmail.com> writes: > > > I wanted to use Icarus but I was confronted to a big problem (as a user > > of Xilinx): in the simlation libraries there are specify blocs and > > Icarus verilog doesn't support them and there are no shoft term plans > > to support them. > > There was a bug in the unisim libraries at one point which make ghdl > (rightfully) choke: an element of an enum had the same name as a > variable or a type IIRC. Maybe that is your problem? > > Cheers, > Colin I'm talking about icarus verilog ... not about ghdl!!! Cheers
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