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> <snip> > For OPB, I ever tried to connect to Microblaze to one OPB bus but it > didn't work. After I disabled one Microblaze it works. Could you > suggest what's wrong with my design. Thanks for your help. > > Sunwei > > For You might want to try using the newest tools, and enable dynamic priority on the OPB (C_DYNAM_PRIORITY). /SivaArticle: 105851
jimwalsh142@hotmail.com wrote:
> I'm trying to develop a programmable pulse generator, essentially a
> single pulse of variable width repeated at a given rate.
I would recommend a synchronous design
using clock enabled counters.
The RTL example "clk enabled counters" here:
http://home.comcast.net/~mike_treseler/
is not a pulse generator, but
it does demonstrate square waves of
three frequencies.
-- Mike Treseler
Article: 105852<jimwalsh142@hotmail.com> wrote in message news:1154471886.472858.324360@s13g2000cwa.googlegroups.com... > Hi All, > > I'm trying to develop a programmable pulse generator, essentially a > single pulse of variable width repeated at a given rate. I posted a > similar question a few weeks ago on sci.elec.design and someone > suggested that this would make a nice CPLD project. As I'm keen to > learn about programmable logic devices I decided to buy a development > kit (Altera 7000 series) and try implementing the pulse generator. > > My ideal specification would be pulse widths from 10ns to 10us > incremented in 10ns steps at repetition rates between 1 to 10 kHz. The > evaluation board has a 25MHz clock so I'm limited to 40ns increments > but that's ok for now. > > I've been playing around with various counters etc but am struggling > to create anything useful, would be great if someone more experienced > could give me a few hints!? > > Thanks, > > Jim W If you want to do it yourself, are you doing schematic, Verilog, or VHDL? For the guts you just want a counter that runs from one to your period-1 (after which it rolls back to 0) and a comparator for the number of cycles for your output pulse high. The registered comparator output give you a nice, clean, programmed pulse. If you had a 100 MHz source, 10 us would require a count to at least 999 or 10 bits. This 10-bit counter also needs two 10-bit values, one for the period and one for the high width. The 10-bit comparator should implement nicely in the CPLD. The two 10-bit values need to be written into the CPLD in some form. If your load signal is asynchronous, be aware that changing the setting may present an unexpected glitch or runt pulse. Let us know if you need to avoid a single bad pulse when changing settings. Also, do you have more than 32 Macrocells to work with and want more bells and whistles?Article: 105853
Greetings, I want to parameterize a module in a way that makes some inputs used or not used. If I have the input defined but don't use it in the module instantiation, I end up with a synthesis warning about tying an unused input to 0. If I use a generate, I'll be trying to add a generate item of the form "input clk," where the comma looks like it won't be a legal generate item. Anyone have a clean way to remove the input from the module definition list without a `define? I can imagine specifying a Verilog-1995 style I/O list where only the names are listed initially then outside the module port definition use an if/else to define my value as input or output; if I don't use the output, I get no warning and if I hook something up to the signal I want unused I should have a synthesis warning for too many drivers. But I'd like to keep my Verilog-2001 style of I/O definitions embedded in the portdefs. - John_HArticle: 105854
jimwalsh142@hotmail.com wrote: > Hi All, > > I'm trying to develop a programmable pulse generator, essentially a > single pulse of variable width repeated at a given rate. I posted a > similar question a few weeks ago on sci.elec.design and someone > suggested that this would make a nice CPLD project. As I'm keen to > learn about programmable logic devices I decided to buy a development > kit (Altera 7000 series) and try implementing the pulse generator. > > My ideal specification would be pulse widths from 10ns to 10us > incremented in 10ns steps at repetition rates between 1 to 10 kHz. The > evaluation board has a 25MHz clock so I'm limited to 40ns increments > but that's ok for now. > > I've been playing around with various counters etc but am struggling > to create anything useful, would be great if someone more experienced > could give me a few hints!? Where are you struggling ? For a single pulse, you need a saturating, Reloadable counter - one that loads, counts, then stops when it hits some limit - Commonly 0000. 10us from 40ns is appx 8 bit counter. ( 10-12 bits if you load with BCD thumbwheels) For linear frequecy rep-rate, that's not quite as simple as normal /N is a 1/X curve. Choices are a small ROM ( OK for a few Freqs), or a Rate Multiplier or DDS frequency scheme. With a Rate Multiplier, run it from max Clk, and post-scale to the < 10KHz re-trigger frequency you want, to reduce jitter. Do you mean 1KHz to 10Khz, or 1Hz to 10Khz ? - former is one decade of Prog Fo, doable in 4 bits of RateMult, latter is 4 decades, so needs appx 14 bits binary, or 20 bits if you load with BCD thumbwheels. 10Khz to 25Mhz of postscale is ~11 bits binary. Another pulse-generator approach, is to define the ON and OFF times, then you have just one timing chain, which is a reloadable counter, from two alternating set-values. That's simple logic, but more set-point wires, or you could choose to compile-in the settings, and use the ISP cable to set. [ Smaller CPLD and less wires ] -jgArticle: 105855
Hi Eric, I have difficulty understanding your slide p. 35. It relates to calculation of latency in ns: 2 - 9; - 1 | | | 6; 5 3; ',' is a register. Number is number of delays. First pipeline delay should be 2+9; The 2nd pipeline delay should be 5+3. Total delay should be 19. But your slide says it is 22 ns. Page 37 is totally wrong using pipeline registers. Because they are not synchronous at all. There is a short cut from the entry to the end point. Thank you. Weng Eric Crabill wrote: > Hello, > > There was a similar thread in this newsgroup. If you are looking to solve a > specific problem and have performance targets, you should share those -- it > will help people give you more focused answers. > > You do not need PowerPCs or BlockRAMs to sort integers. Sure, you can write > a sequential sort algorithm and run it on a processor, but if you are > interested in performance, I think that approach may be one of the last > things you would want to do. If you are interested in two examlpes of a > hardware sort, take a look at: > > http://www.engr.sjsu.edu/crabill/module05.pdf > > There is a bubble sort and an odd-even transposition sort. The examples > sort a set of five, 16-bit values. They could certainly be extended to > handle fewer/more and/or wider/narrower inputs. One example is pipelined, > the pipeline depth can certainly be changed. In fact, you can turn it into > a combinational sorter if you want. > > If anyone expands the examlpes to sort 1 million 64-bit integers, please let > me know what your synthesis tool thinks about it. > > Certainly, I am not advertising the examples as "the best" and I am no > "expert" in sorting. Or anything. But they might be a place for you to > start. I only knew the bubble sort, but used Google to search for "parallel > sorting algorithms" because I figured there would be one which I could > implement in hardware. The odd-even transposition sort is indeed quite > easy. > > Eric > > > we have a Virtex4 FPGA and are looking for availlable hardware sorting > > algorithms. I couldnt find anything @opencores.org however I guess that > > it has been worked on this subject. > > > > The Virtex4 supports 2 PowerPCs and lots of Block RAMs so everything > > seems to be there. Are there any projects and what speeds could be > > estimated for sorting 64 bit integers?Article: 105856
Austin Lesea wrote: > Jim, > > Been down that road (making any software source public). Nope. Dead > end. I have more useful things to attend to right now. > > There are already many vendors that support JTAG, and the BSDL files are > their for them (or you). Feel free to buy and use their software > instead of ours. I am sure it can be made better than ours, and provide > more features than ours does. > > I would not want to appear to be competing with these vendors, nor > making their business any less profitable. > > Austin Thanks, Sounds like that may be viable for programming (and is what the OP is now doing), but what about the Logic analyzer/probe tools, don't they use JTAG pathways ? Or do they also work fine, with anyones JTAG system ? -jgArticle: 105857
John_H wrote: > A perhaps better approach is to use a loadable down-counter that is one bit wider than your maximum count. That way, the terminal count is just the MSB of the counter, and it can be used to disable the count as well. This eliminates the comparator. A DDS can be used to get a programmable rate that is not an integer multiple of the clock frequency and that has a linear relationship between the program value and the output frequency. The DDS is basically just an accumulator to which a fixed increment is added on each clock cycle. The square-wave output is taken from the MSB of the accumulator. (It will have jitter of up to a clock cycle depending on the increment value).Article: 105858
Siva Velusamy wrote: > > <snip> > > For OPB, I ever tried to connect to Microblaze to one OPB bus but it > > didn't work. After I disabled one Microblaze it works. Could you > > suggest what's wrong with my design. Thanks for your help. > > > > Sunwei > > > > For > > > You might want to try using the newest tools, and enable dynamic > priority on the OPB (C_DYNAM_PRIORITY). > > /Siva I see. Thanks Siva.Article: 105859
I used [31:0] to pass on the integer to my task, but it won't compare with
"count"
which is of integer type.
How can I solve this?
task mytask:
input [31:0] my_int;
integer count;
blah
if (my_int == count) begin
do_something
end
end
endtask
Article: 105860"Mr. Ken" <Mr. Ken@asdf> wrote in message news:44d04454$1@news.starhub.net.sg... > I used [31:0] to pass on the integer to my task, but it won't compare with > "count" > which is of integer type. > > How can I solve this? > > > > task mytask: > input [31:0] my_int; > integer count; > > blah > if (my_int == count) begin > do_something > end > > end > endtask > > Got it input integer my_int;Article: 105861
Hi,
I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga.
And i am using the controller generated by the MIG1.5 tool. When i run
this controller in the real hardware i am getting zeros in the result
bus(read_data_fifo_out)... Dont know where i am wrong.
I am monitored all my controller signals using the chipscope
and they are all working fine for me. But the ddr is not giving
anything back...
Can u guys please tell me what is the minimum frequency at
which i can operate the ddr controller.
regards
subin
Article: 105862jvdh wrote: > This might be slightly OT for an FPGA group, but maybe someone has run > into a similar problem before: > > I'd like to connect my FPGA, via JTAG, to my PC, 100m away. Due to a > hazardous environment, putting the PC any closer isn't feasible > > I'm using a Xilinx parallel cable III, which I extended with RS485 > drivers to get to required distance, before converting back to TTL to > drive the original cable. What about a USB programming cable and some USB <-> CAT5 extender modules? I am not sure if they go up to 100m though, might only do 50m. Another possibility would be to use a (potentially) 'sacrificial' PC to talk JTAG from CableServer and control it from your workstation over ethernet. (As I read further into the thread.. maybe one in a farking big lead box :) > Does someone perhaps know whether impact will get upset with the delay? > Is there away around it? (As far as I can see, my cable doesn't > respond to the speed setting in Impact) AFAIK the Parallel III is locked at 200kHz. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 105863
Jim Granville <no.spam@designtools.co.nz> wrote: > 'All' FPGA software could have issues, but yes, there IS a strong case > for placing this level of software on sourceforge. There is already a XC3SPROG project on sourceforge, but with no code yet. End of June Eric(?) told that he had not had time yet to put something into the project he put on sourceforeg. Hopefully things change. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 105864
Dear Mr. Ken, I recommend you search for this on Google :- vhdl math tricks Mr. Jim has written a very enlightening article. Yours &c, Mr. Syms. p.s. You may also like to know that the usenet group comp.lang.vhdl is useful for the kind of question you posed.Article: 105865
> Fax application cannot be counted as full Huffman encoding. The reason > is the statistics for characters are not dynamically collected. Also for JPEG, etc. in most cases the predefined default Huffman-tables are used (Althought the file-format would support custom tables). I think the term "Huffman" is also widely used for such "static" applications. Regards, Thomas P.S.: I am wondering what the reason for your question is? www.entner-electronics.comArticle: 105866
Jim Granville wrote: > jimwalsh142@hotmail.com wrote: > > Hi All, > > > > I'm trying to develop a programmable pulse generator, essentially a > > single pulse of variable width repeated at a given rate. I posted a > > similar question a few weeks ago on sci.elec.design and someone > > suggested that this would make a nice CPLD project. As I'm keen to > > learn about programmable logic devices I decided to buy a development > > kit (Altera 7000 series) and try implementing the pulse generator. > > > > My ideal specification would be pulse widths from 10ns to 10us > > incremented in 10ns steps at repetition rates between 1 to 10 kHz. The > > evaluation board has a 25MHz clock so I'm limited to 40ns increments > > but that's ok for now. > > > > I've been playing around with various counters etc but am struggling > > to create anything useful, would be great if someone more experienced > > could give me a few hints!? > > Where are you struggling ? > > For a single pulse, you need a saturating, Reloadable counter - one that > loads, counts, then stops when it hits some limit - Commonly 0000. > 10us from 40ns is appx 8 bit counter. ( 10-12 bits if you load with BCD > thumbwheels) > > For linear frequecy rep-rate, that's not quite as simple as normal /N > is a 1/X curve. > Choices are a small ROM ( OK for a few Freqs), or a Rate Multiplier or > DDS frequency scheme. > With a Rate Multiplier, run it from max Clk, and post-scale to the < > 10KHz re-trigger frequency you want, to reduce jitter. > > Do you mean 1KHz to 10Khz, or 1Hz to 10Khz ? - former is one decade of > Prog Fo, doable in 4 bits of RateMult, latter is 4 decades, so needs > appx 14 bits binary, or 20 bits if you load with BCD thumbwheels. > 10Khz to 25Mhz of postscale is ~11 bits binary. > > Another pulse-generator approach, is to define the ON and OFF times, > then you have just one timing chain, which is a reloadable counter, from > two alternating set-values. > > That's simple logic, but more set-point wires, or you could choose to > compile-in the settings, and use the ISP cable to set. [ Smaller CPLD > and less wires ] > > -jg Thanks for all the useful replies! I think I need to clarify my setup... I have a small microcontroller that generates a PWM signal and I was planning to use this as the repetition rate. Also attached to the uC is an LCD and keypad to enable the user to enter the pulse width and rep rate. I'm ok with that and it works well. At the minute I'm using a Altera Max epm7128slc84-10 which has 128 macrocells. I'm really new to all this so I have been using the schematic design entry tool. So far I have managed to use two 74160 decade programmable counters to divide my clock, the counters are controlled by the microprocessor. This approach fails because the duty cycle of the divided clock isn't 50% and I still don't know how to get a single pulse from the train of pulses? By the way, my first approach was to use a Pic & DDS I put the idea on hold as I can't make PCB's and the DDS is surface mount! Also I'm learning much more doing this via CPLD as I've never used anything like it before. Thanks for the help, Jim W.Article: 105867
On 2 Aug 2006 10:00:19 +0200, "Symon" <symon_brewer@hotmail.com>
wrote:
>Dear Mr. Ken,
>I recommend you search for this on Google :- vhdl math tricks
>Mr. Jim has written a very enlightening article.
>Yours &c, Mr. Syms.
>p.s. You may also like to know that the usenet group comp.lang.vhdl is
>useful for the kind of question you posed.
tee hee, all you'll get there is chuckles - the OP's problem was
a Verilog, not VHDL, problem; he was effectively trying to
compare a reg[31:0] with an integer, and (I guess) being
badly confused because Verilog does unsigned comparison
if any unsigned operand appears in the expression - and
all reg[] variables are unsigned unless you explicitly set
them to be signed. In VHDL you don't normally have this
kind of problem (unless you use goofy packages like
std_logic_unsigned); things either do what you expect
them to do, or give rise to a compiler error.
Try this in Verilog:
reg [7:0] Byte;
...
Byte = -3; // legal, gives binary 11111101
if (Byte < 0)
$display("Negative"); // nope, Byte is unsigned!
else
$display("Positive"); // this is what you get, Byte==253
The solution of passing an integer argument to the task is
fine as long as you are happy for it to be an unspecified
bit width (at least 32 bits, possibly more). If your tools
support Verilog-2001 then it's also possible to pass
a "reg signed [31:0]" into the task, and then you keep
control over the bit width whilst still preserving signed
arithmetic.
Caveat scriptor :-)
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 105868Użytkownik subint napisał: > Hi, > I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. > And i am using the controller generated by the MIG1.5 tool. When i run > this controller in the real hardware i am getting zeros in the result > bus(read_data_fifo_out)... Dont know where i am wrong. > I am monitored all my controller signals using the chipscope > and they are all working fine for me. But the ddr is not giving > anything back... > Can u guys please tell me what is the minimum frequency at > which i can operate the ddr controller. > regards > subin > Proper frequency range for your memory is from 77MHz to 166MHz. AdamArticle: 105869
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:8mr0d2hsehqehufng8k80eb5qm4f926tjt@4ax.com... > On 2 Aug 2006 10:00:19 +0200, "Symon" <symon_brewer@hotmail.com> > wrote: > >>p.s. You may also like to know that the usenet group comp.lang.vhdl is >>useful for the kind of question you posed. > > tee hee, all you'll get there is chuckles - the OP's problem was > a Verilog, not VHDL, problem; > Caveat scriptor :-) > Whoops, you're of course quite correct. (Must not post before 1st coffee of the day!) I just assumed it had to be VHDL because Verilog blithely parses whatever you feed it! Thanks for correcting that Jonathan, Syms.Article: 105870
jimwalsh142@hotmail.com wrote: <snip> > Thanks for all the useful replies! > > I think I need to clarify my setup... I have a small microcontroller > that generates a PWM signal and I was planning to use this as the > repetition rate. Also attached to the uC is an LCD and keypad to enable > the user to enter the pulse width and rep rate. I'm ok with that and > it works well. OK, so this is a uC augmented by CPLD, which is a good combination. > > At the minute I'm using a Altera Max epm7128slc84-10 which has 128 > macrocells. I'm really new to all this so I have been using the > schematic design entry tool. So far I have managed to use two 74160 > decade programmable counters to divide my clock, the counters are > controlled by the microprocessor. This approach fails because the duty > cycle of the divided clock isn't 50% and I still don't know how to > get a single pulse from the train of pulses? You need to make a 'digital monostable' - start the counter on an edge from the uC PWM, and then stop, and hold until the next trigger edge, after NNN clock cycles. Taking your 74160, you need a JK FF, driving the 160.ClockEnable Setup an edge detector ( one clock pulse wide ) from the PWM, and The JK FF is set on this, the same one-clock pulse does the SyncLoad of the 160s. Then the terminal count from the 160, clears the JK FF, which holds everything paused, until the next Edge. The JK ff gives a variable width wide pulse. Use a common clock for the PLD and uC, to avoid clock race conditions. > > By the way, my first approach was to use a Pic & DDS I put the idea on > hold as I can't make PCB's and the DDS is surface mount! Also I'm > learning much more doing this via CPLD as I've never used anything > like it before. > > Thanks for the help, > > Jim W. >Article: 105871
Ray Andraka wrote: > John_H wrote: > A DDS can be used to get a programmable rate that is not an integer > multiple of the clock frequency and that has a linear relationship > between the program value and the output frequency. The DDS is > basically just an accumulator to which a fixed increment is added on > each clock cycle. The square-wave output is taken from the MSB of the > accumulator. (It will have jitter of up to a clock cycle depending on > the increment value). I prefer Bresenhams algorithm for frequency generation. The N-bit accumulator has a frequency error of up to 1/2^N. Bresenhams algorithm is exact for the question "generate N pulses in M clock cycles". I also has minimum jitter (up to half a clock cycle). The hardware implementation is simple and small. Kolja SulimmaArticle: 105872
Hello, I'd like to know if it's possible (and if yes how ?) to initialize BRAM content not directly in the sources, nor in the final .bit file but in the ngc (netlist). The situation is this : I have an IP core that contains several BRAM, some for EDK some for other stuff. Some of them need to be initialized to some values. When I do it "for me", I can do it in the final BRAM file, but when delivering the core, I'd lilke to provide a single ngc file that has all that is required already in it. So, anyone know how to do that ;) ? Thanks & regards, SylvainArticle: 105873
On 2006-08-02, Sylvain Munaut <SomeOne@SomeDomain.com> <246tnt@gmail.com> wrote: > Hello, > > I'd like to know if it's possible (and if yes how ?) to initialize BRAM > content not directly in the sources, > nor in the final .bit file but in the ngc (netlist). > > The situation is this : I have an IP core that contains several BRAM, > some for EDK some for other stuff. Some of them need to be initialized > to some values. When I do it "for me", I can do it in the final BRAM > file, but when delivering the core, I'd lilke to provide a single ngc > file that has all that is required already in it. > > > So, anyone know how to do that ;) ? I haven't tried any of this myself, I have only used the data2mem tool to update the final bitstream or generate suitable defparams for use in the source code. Anyway, you might be able to use the xdl tool to convert the ngc file to an xdl file (which will contain a text description of the ngc file), change the values of the relevant block rams and then use the xdl tool to convert it back. A safer option could be to specify that your customers would have to specify a -bd option to bitgen. (Although I haven't tried this myself either.) /AndreasArticle: 105874
G=F3rski Adam wrote: > Uzytkownik subint napisal: > > Hi, > > I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. > > And i am using the controller generated by the MIG1.5 tool. When i run > > this controller in the real hardware i am getting zeros in the result > > bus(read_data_fifo_out)... Dont know where i am wrong. > > I am monitored all my controller signals using the chipscope > > and they are all working fine for me. But the ddr is not giving > > anything back... > > Can u guys please tell me what is the minimum frequency at > > which i can operate the ddr controller. > > regards > > subin > > > > Proper frequency range for your memory is from 77MHz to 166MHz. > > Adam The Spec minimum for DDR is 83.33MHz (See the JEDEC data sheet: http://download.micron.com/pdf/misc/JEDEC79R2.pdf ) Cheers PeteS
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