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Dear Jens, Through reading some topic in this forum, I see that there are still some bugs on this ISE 8.1i. My friend also try run an example with ISE 8.1i. But when he run the floorplanner when design an example on the Spartan2e, he could not find the clock pin. He still not install the Partial Flow yet. Is it the main reason? We still can not find the service pack 1 for ISE 8.1i. Thanks alot! Thang NguyenArticle: 110351
Hi Davy, The AVM cookbook from Mentor describes these terms, you can download a free copy from: http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm Hans www.ht-lab.com "Davy" <zhushenli@gmail.com> wrote in message news:1160799509.696951.204680@b28g2000cwb.googlegroups.com... > Hi all, > > IMHO, there is something compare the golden output and DUT output in > testbench (I call it Checker). But in verification book, there is both > Scoreboard and Checker. Are they similar? > > Please recommend some reading on it.Thanks! > > Best regards, > Davy >Article: 110352
Brad Smallridge schrieb:
> Seems like they are there. I can see them in the
> editor. They route through several hierarchies
> to a series of these:
>
> iobuf00 : IOBUF
> port map (
> O => O( 0),
> IO => IO( 0),
> I => I( 0),
> T => T( 0) );
>
> which are there but the OLOGIC is showing a latched O
> and a thru T.
>
> Brad
see below
XLXI_7
maps into T flop of ologic 100%
antti
XLXI_6 : OFDT_MXILINX_t4
port map (C=>XLXN_13,
D=>XLXN_25,
T=>XLXN_15,
O=>XLXN_16);
XLXI_7 : FD
port map (C=>XLXN_13,
D=>XLXN_24,
Q=>XLXN_15);
XLXI_10 : IFD_MXILINX_t4
port map (C=>XLXN_13,
D=>XLXN_26,
Q=>XLXN_24);
XLXI_11 : IFD_MXILINX_t4
port map (C=>XLXN_13,
D=>XLXN_27,
Q=>XLXN_25);
Article: 110353Hi Thang, try this links for 8.1.01, they worked for me: http://www.xilinx.com/direct/swhelp/ise8/81i_sp1/8_1_01i_sol.zip http://www.xilinx.com/direct/swhelp/ise8/81i_sp1/8_1_01i_lin.zip http://www.xilinx.com/direct/swhelp/ise8/81i_sp1/8_1_01i_lin64.zip http://www.xilinx.com/direct/swhelp/ise8/81i_sp1/8_1_01i_win.zip Choose the one you need for your operating system. Never use a version of ISE without any service pack installed. I don't know about floorplanner issues regarding Spartan 2E, since i'm not using that part. Have you tried to specify the clock pin in the UCF file manually? Regards, Jens Thang Nguyen schrieb: > Dear Jens, > > Through reading some topic in this forum, I see that there are still some bugs on this ISE 8.1i. My friend also try run an example with ISE 8.1i. But when he run the floorplanner when design an example on the Spartan2e, he could not find the clock pin. He still not install the Partial Flow yet. Is it the main reason? We still can not find the service pack 1 for ISE 8.1i. > > Thanks alot! > > Thang NguyenArticle: 110354
Hi,
i would like to know which is the best if i want a FPGA ( with
150k virtex4 equavalent LUTs) and low cost.
thanks in advance
subin
Article: 110355
subint wrote:
> Hi,
> i would like to know which is the best if i want a FPGA ( with
> 150k virtex4 equavalent LUTs) and low cost.
> thanks in advance
> subin
>
You want a FPGA with 150.000 LUTs ? 75000 Slices ... and at low cost ?
I must have mis-understood ...
But there is not that much manufacturer of FPGA ... If you currently
have a model that fits your needs :
- Lookup it's size in terms of LUTs/FF couple.
- Check what "special resources" you're using like hard multipliers,
DSP48, DCM, ...
- Now check the Xilinx, Altera, Lattice, (Actel ?) websites for devices
with about the same or superior LUTs/FF count and check if it has the
other special resources you need. Think also that some of there
resources could be implemented by logic ...
Also check out
http://www.fpga-faq.org/compare/build_form.cgi
Sylvain
Article: 110356
Hi,
Yes i mean 150k LUTs.. i checked all these websites but only
xilinx is projecting the LUT counts. Altera projecting there features
with ALM and they saying it's is almost equvalent to 2 slice
etc.Lattice semiconductors clamming they are better and FAST.
I am totally confused.
By saying low cost i just mean the comparision(if there are more
than one source with these features).
when i synthesized my project it's taking almost 80% of the
virtex4(Lx200) ( it have 180kLUTs) . i think lx200 cost about $7000. i
am looking for a alterative if available....
regards
subin
Sylvain Munaut wrote:
> subint wrote:
> > Hi,
> > i would like to know which is the best if i want a FPGA ( with
> > 150k virtex4 equavalent LUTs) and low cost.
> > thanks in advance
> > subin
> >
>
> You want a FPGA with 150.000 LUTs ? 75000 Slices ... and at low cost ?
> I must have mis-understood ...
>
> But there is not that much manufacturer of FPGA ... If you currently
> have a model that fits your needs :
> - Lookup it's size in terms of LUTs/FF couple.
> - Check what "special resources" you're using like hard multipliers,
> DSP48, DCM, ...
> - Now check the Xilinx, Altera, Lattice, (Actel ?) websites for devices
> with about the same or superior LUTs/FF count and check if it has the
> other special resources you need. Think also that some of there
> resources could be implemented by logic ...
>
> Also check out
>
> http://www.fpga-faq.org/compare/build_form.cgi
>
>
>
>
> Sylvain
Article: 110357HI all how can one use an edif netlist of a design to add components to it either in schematic or vhdl and verilog? is it possible to do it in webpack? if yes then how? i have tried a lot and i can use command line tools to add ucf file and generate bit file from this edif netlist but i am unable to find a way to add further design components to it in schematic or vhdl design entry.Article: 110358
Hi, what quantities do you need? What kind of design is it? Without knowing any details, I think you should try to get the LUT count down. I can imagine that a design that REALLY fills one of those large devices must have a quite long development time. So I suppose if you can already compile the design before you know which device you are targeting, I think there is a lot of potential there. Thomas "subint" <subin.82@gmail.com> schrieb im Newsbeitrag news:1160821923.691563.325170@m7g2000cwm.googlegroups.com... > Hi, > Yes i mean 150k LUTs.. i checked all these websites but only > xilinx is projecting the LUT counts. Altera projecting there features > with ALM and they saying it's is almost equvalent to 2 slice > etc.Lattice semiconductors clamming they are better and FAST. > I am totally confused. > By saying low cost i just mean the comparision(if there are more > than one source with these features). > when i synthesized my project it's taking almost 80% of the > virtex4(Lx200) ( it have 180kLUTs) . i think lx200 cost about $7000. i > am looking for a alterative if available.... > regards > subin > > Sylvain Munaut wrote: >> subint wrote: >> > Hi, >> > i would like to know which is the best if i want a FPGA ( with >> > 150k virtex4 equavalent LUTs) and low cost. >> > thanks in advance >> > subin >> > >> >> You want a FPGA with 150.000 LUTs ? 75000 Slices ... and at low cost ? >> I must have mis-understood ... >> >> But there is not that much manufacturer of FPGA ... If you currently >> have a model that fits your needs : >> - Lookup it's size in terms of LUTs/FF couple. >> - Check what "special resources" you're using like hard multipliers, >> DSP48, DCM, ... >> - Now check the Xilinx, Altera, Lattice, (Actel ?) websites for devices >> with about the same or superior LUTs/FF count and check if it has the >> other special resources you need. Think also that some of there >> resources could be implemented by logic ... >> >> Also check out >> >> http://www.fpga-faq.org/compare/build_form.cgi >> >> >> >> >> Sylvain >Article: 110359
On 13 Oct 2006 02:13:55 -0700, "Tim Verstraete" <tim.verstraete@barco.com> wrote: >Hey, > >I have 2 LVDS clock signals and both are terminated with the DIFF_TERM >attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them >... now i want both buffers to stay in my design and not optimized >away. Is there a constraint that i can place on that buffer? i guess >that it should be a UCF constraint since when i look into the RTL >viewer of planahead and ISE i still see the buffer. Look into "keep" attributes. See the Constraints Guide for details. (Sometimes "keep" attributes don't work though. On registers, they are overridden by "equivalent_register_removal" and result in an obscure error message instead. I haven't tried them on clock buffers) - BrianArticle: 110360
On Fri, 13 Oct 2006 15:21:41 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >The following code: > > output_process:process(clk) > begin > if( clk'event and clk='1') then > mem_a <= mem_a_fabric; > mem_q <= mem_q_fabric; > mem_t <= mem_t_fabric; > end if; > end process; >is correctly placing registers at pads for d and q but not T. >Seems like the XST is simplifying this down to one >flop and routing the resulting signal through the T >buffers. > >How do I register T at the OLOGIC? If you have equivalent_register_removal ON in XST it will do this, and override any "keep" attributes you place on the _t signal, giving obscure warning messages that aren't documented anywhere in the Answers Record. You can locally apply an "equivalent_register_removal = FALSE" attribute to the tristate signal, to prevent the simplification. This worked here for the same problem. - BrianArticle: 110361
Hi, The following is the VHDL example on page 699, Libraries Guide, ISE 8.1i. I have two questions in this example. 1. This example is not for XST (In ISE, I can use the end port map and include Library UNISIM; use UNISIM.vcomponents.all; as provided in VHDL template). Just for VHDL grammar, I am curious about INIT is defined a 8 bit bit_vector, then it declares attribute INIT : string; attribute INIT of LUT3_instance_name : label is "8"; I cannot understand the necessary of the attribute sentences. 2. The following is wrong? I guess the values can be 0,1,2,...63. -- values can be 0, 1, 2, 3, 4, 5, 6, 7, 8 At least it is different from the LUT1 and LUT2 examples, one of them should be wrong. Thank you very much. ---------------------------- VHDL Instantiation Template for LUT3 -- Component Declaration for LUT3 should be placed -- after architecture statement but before begin keyword component LUT3 -- synthesis translate_off generic ( INIT : bit_vector := X"8"); -- synthesis translate_on port (O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT3 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT3_instance_name : label is "8"; -- values can be 0, 1, 2, 3, 4, 5, 6, 7, 8 -- Component Instantiation for LUT3 should be placed -- in architecture after the begin keyword -- LUT3_INSTANCE_NAME : LUT3 -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2);Article: 110362
Ayon kay Brad Smallridge: > Might be some trouble if this is an SDRAM with a control register. > What are you up to? > > > "yy" <yy7d6@yahoo.com.ph> wrote in message > news:1160763728.800770.182020@m7g2000cwm.googlegroups.com... > > Hi, > > Is it ok not to connect at least one DDR Address signal to a ddr > > controller? If so, should i connect it to GND or VCCIO? Thanks. > > Hi Brad, My design is out of IO pins, BTW i use an FPGA ddr controller core..Article: 110363
Hi Daniel, Daniel Leu wrote: > > Routing depends on your design structure. Even with high device > utilization, Designer usually is successful. If routing fails or you > can't get timing closure, you can try place&route with the "Multiple > Passes" option. I will try it, thanks. Does it have any drawback? > > Certainly. You can export the netlist together with the SDF to perform > gate-level simulation with effective cell and routing delays. > I thought that this is what the back-annotate does, am I wrong? I usually do the back-annotate and then do the post-layout simulation with Model-Sim (unfortunately by the mean of Libero IDE, that I personally hate, but still didn't have time to make rid of it). What do you mean by "gate-level simulation"? > > Daniel Leu > Inicore, Inc. > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110364
You are not going to get a device of this size as a low cost device unless you wait several years and several generations of low cost device. Even the very biggest low cost Spartan-3s and equivalents are not THAT low cost. The lowest cost option is several mid family parts to cover the size e.g. XC3S1500. John Adair Enterpoint Ltd. subint wrote: > Hi, > i would like to know which is the best if i want a FPGA ( with > 150k virtex4 equavalent LUTs) and low cost. > thanks in advance > subinArticle: 110365
Avion wrote: > HI all > how can one use an edif netlist of a design to add components to it > either in schematic or vhdl and verilog? is it possible to do it in > webpack? if yes then how? i have tried a lot and i can use command line > tools to add ucf file and generate bit file from this edif netlist but > i am unable to find a way to add further design components to it in > schematic or vhdl design entry. > I can tell you how using VHDL. Please don't use schematics ;) You will have a top level file in VHDL. Add a component declaration with the signal inputs/outputs of the edif file, and then instantiate it on your code and connect it up. Create your project as a normal VHDL project that will be synthesized by XST. In the "Sources" window of ISE, the blocks that are using the edif files will show up as question marks. This is fine; XST will treat them as "black boxes". If you like to keep the edif files in a separate location, then on the "Translate" process, right click, select properties, and point the "Macro Search Path" to the location of your edif files. Now just run the build. During the Translate phase, it should automatically find your edif files and include them in your project.Article: 110366
yy wrote: > Ayon kay Brad Smallridge: >> Might be some trouble if this is an SDRAM with a control register. >> What are you up to? >> >> >> "yy" <yy7d6@yahoo.com.ph> wrote in message >> news:1160763728.800770.182020@m7g2000cwm.googlegroups.com... >>> Hi, >>> Is it ok not to connect at least one DDR Address signal to a ddr >>> controller? If so, should i connect it to GND or VCCIO? Thanks. >>> > > Hi Brad, > My design is out of IO pins, BTW i use an FPGA ddr controller core.. > The main thing you need to be careful of is the initialization phase of the DDR (assuming you need initialization). This requires that you be able to access certain specific addresses.Article: 110367
yy wrote: > Ayon kay Brad Smallridge: > >>Might be some trouble if this is an SDRAM with a control register. >>What are you up to? >> >> >>"yy" <yy7d6@yahoo.com.ph> wrote in message >>news:1160763728.800770.182020@m7g2000cwm.googlegroups.com... >> >>>Hi, >>>Is it ok not to connect at least one DDR Address signal to a ddr >>>controller? If so, should i connect it to GND or VCCIO? Thanks. >>> > > > Hi Brad, > My design is out of IO pins, BTW i use an FPGA ddr controller core.. > This is such an odd question. The obvious answer is look at the datasheet on the ddr. ddr needs to be configured. This is done by putting a special address on the address lines. Which address bits need to be changing? Which can be tied to 0 or 1, or another address bit? Every address bit you remove will knock out at least 50% of the storage capacity of the ram, and these accumulate. Lose enough bits and the bits start knocking out 75% of the remainder. You've also got 2 bank bits -- you can tie them together. Or tie them to 0, at the expense of losing 50% or 75% of capacity. So you're out of io pins, but the design isn't finalized. Get a more io-centric part. This is like a jockey who's worried about being too heavy, so he's wondering if he cuts off a hand will he be able to handle the horse? There just isn't enough information in your question to go on. Failing that, you've got to do the studying and figure it out for yourself. I would think it's certainly possible to cut out pins to the DDR, but at what cost? You've got to figure that out. A better approach to reducing pins, ddr related, might be to let data pins float, or perhaps get an 8 bit part instead of a 16 bit one. By adding one address bit you can half the number of data pins without losing memory. Probably you can tie unused data pins to a pullup or pulldown. -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 110368
Manny, Reconfiguring takes no more power (and less than when things are running). Yes, the pass gate transistors, and the memory cells are all mid-oxide, to save power from leakage. Austin Manny wrote: > Yet another issue is how much reconfiguration power budget compares to > static power i.e. is it really worth it to reconfigure (partially or > fully) as frequent as diserable and still maintain improvements over > static power. Does Virtex-4 support tripple oxide technology for > routing transistors? Actually I'm planning one using this frequently > via having an ARM7 softcore (running on fusion) dispatching > functionalities dynamically. In principle it sounds interesting but I > don't knwo whether it is worth it or not and power reconfiguration > budget might grow exponentially with the frequency of reconfiguration. > > Thanks a lot guys, it's really been rather insightful comments. > > Cheers, > -Manny >Article: 110369
Hi Jens, I use Window. It looks like there is only the Add directory, which includes ISEExamples, and Replace directory, which includes docs. I can not update to the sp1 with these two directories. :( Thang NguyenArticle: 110370
That may be, but configuration takes a significant amount of time and energy to complete. This needs to be considered in any model that powers the parts down to conserve energy. The duration of the power down needs to be long enough to pay for the reconfiguration. Even some of the Flash based devices have this concern since they use internal Flash as a backup to an SRAM FPGA. Aren't the Coolrunner II parts like that as well? Although I am sure the CR II parts have a very low configuration energy. Austin Lesea wrote: > Antti, > > We are still characterizing the parts and process, so we don't want to > put anything in the data sheet for V5 until we are done. > > But, there is no surge, or big Iccint that is required for V5... > > Austin > > > > Antti wrote: > > Austin Lesea schrieb: > > > >> Manny, > >> > >> Just one comment: > >> > >> There has been no "in rush" or "bonus" current needed since Virtex II > >> (V2, V2P, V4, V5 have no "inrush" for Vccint, the datasheet specifies > >> the minimum Iccint required to power on and configure). > >> > >> What you describe was common for Virtex E, and older families. However, > >> we decided that was unacceptable, so we fixed it (a long time ago, now). > >> > >> Austin > >> > > Austin, > > > > please check Xilinx publication EN049(v 1.3) page 2 > > for Virtex-5 power requirements during configuration > > > > Antti > >Article: 110371
thanks for the help. let me try n i hope it will work. but isn't it much easier in schematics to connect signals? is there anyway in schematics as well? one way may be to create a schematic of the wrapper file u just suggested and then use it. am i right? Duane Clark wrote: > Avion wrote: > > HI all > > how can one use an edif netlist of a design to add components to it > > either in schematic or vhdl and verilog? is it possible to do it in > > webpack? if yes then how? i have tried a lot and i can use command line > > tools to add ucf file and generate bit file from this edif netlist but > > i am unable to find a way to add further design components to it in > > schematic or vhdl design entry. > > > > I can tell you how using VHDL. Please don't use schematics ;) > > You will have a top level file in VHDL. Add a component declaration with > the signal inputs/outputs of the edif file, and then instantiate it on > your code and connect it up. > > Create your project as a normal VHDL project that will be synthesized by > XST. In the "Sources" window of ISE, the blocks that are using the edif > files will show up as question marks. This is fine; XST will treat them > as "black boxes". If you like to keep the edif files in a separate > location, then on the "Translate" process, right click, select > properties, and point the "Macro Search Path" to the location of your > edif files. > > Now just run the build. During the Translate phase, it should > automatically find your edif files and include them in your project.Article: 110372
Funny, I think I understood what you were asking by your second post here. I don't know why Xilinx does not understand. They seem to want to answer the wrong question and then when you tell them they answered the wrong question they seem to think *you* are the one that misunderstands. I have seen this more than once and with more than one person at Xilinx. I don't know if it is a corporate culture thing to not be willing to reexamine their thinking or if it is just the individual people, but I have seen this on numerous occasions. Perhaps if you asked in an extremely detailed way that left no room for misunderstanding? Specify the pin number of the signal you are using to keep them from thinking you are using SSTL on the JTAG pins. Ask specifically what the threshold level will be on that pin during boundary scan after you have loaded the configuration. *Do not mention any other information that you may think will be helpful if it is not required!!!* Any stray info can result in misinterpretation. I have seen many times that the mention of a piece of information that should help to clarify your thinking actually results in alarm bells going off on the other side and the discussion goes way off course. Good luck! colin wrote: > Jim > > Unfortunately we haven't purchased the jtag debugger option where you > can manually tri-state and read the state of pins so injecting my own > levels is not easy. However your quite right, it is fast coming to this > and I am going to end up with adding a couple of 0R resistors so that I > can remove them and drive the net myself. > > Colin > > Jim Granville wrote: > > colin wrote: > > > > > Jim > > > > > > I'm using a coolrunner II (which I said in my first email). > > > I think they are the only CPLDs that support SSTL but if anyone knows > > > of another familly then I'd love to take a look. > > > > > > I'm fairly certain that the IO config isn't removed during boundary > > > scan because I can read the functional state of pins using JTAG and so > > > can chipscope for FPGAs. > > > > Failing a definitive reply from Xilinx, you could always just test it ? > > IP threshold is a fairly easy thing to check, especially if you have > > all the read-pathway working. > > > > -jgArticle: 110373
Ayon kay David Ashley: > yy wrote: > > Ayon kay Brad Smallridge: > > > >>Might be some trouble if this is an SDRAM with a control register. > >>What are you up to? > >> > >> > >>"yy" <yy7d6@yahoo.com.ph> wrote in message > >>news:1160763728.800770.182020@m7g2000cwm.googlegroups.com... > >> > >>>Hi, > >>>Is it ok not to connect at least one DDR Address signal to a ddr > >>>controller? If so, should i connect it to GND or VCCIO? Thanks. > >>> > > > > > > Hi Brad, > > My design is out of IO pins, BTW i use an FPGA ddr controller core.. > > > > This is such an odd question. The obvious answer is look at > the datasheet on the ddr. ddr needs to be configured. This > is done by putting a special address on the address lines. > Which address bits need to be changing? Which can be > tied to 0 or 1, or another address bit? Every address bit you > remove will knock out at least 50% of the storage capacity of > the ram, and these accumulate. Lose enough bits and the > bits start knocking out 75% of the remainder. You've also > got 2 bank bits -- you can tie them together. Or tie them > to 0, at the expense of losing 50% or 75% of capacity. > > So you're out of io pins, but the design isn't finalized. Get a > more io-centric part. This is like a jockey who's worried > about being too heavy, so he's wondering if he cuts off a > hand will he be able to handle the horse? > > There just isn't enough information in your question to go on. > Failing that, you've got to do the studying and figure it out > for yourself. I would think it's certainly possible to cut out > pins to the DDR, but at what cost? You've got to figure that > out. > > A better approach to reducing pins, ddr related, might be > to let data pins float, or perhaps get an 8 bit part instead of > a 16 bit one. By adding one address bit you can half the > number of data pins without losing memory. Probably you > can tie unused data pins to a pullup or pulldown. > > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architecture I guess you're right...Article: 110374
If you think of the EDK as a way to create a bussed architecture, you can do this within the EDK by using a custom peripheral. Use the EDK to instantiate: PLB PLB_DDR IP Core Connect the PLB to to the PLB_DDR IP core. Then use the Create Peripheral Wizard to generate templates for a custom peripheral. Create your custom logic, and setup your peripheral to DMA the data to the memory. Import the peripheral into the EDK, and hope it works. However, if the only reason you want the PLB is for the DDR controller, and you really want speed, why not use the Memory Interface Generator? If you want to share data with a processor, it may be easier to use block rams.
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