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> In order for the CLOCK signal to go high, ALE must > be low, in your logic, since (not ALE) is AND'd with > WRITE# and READ#. So that implies inside your > 'if' the ALE='1' can never be true. > > Perhaps changing your logic to falling_edge(CLOCK) > might fix it within your approach. Or invert the CLOCK > signal from what it is now. Hi David, The clock is right, I need to load the address at the falling edge of ALE. If you consider ALE falling edge generated the rising clock edge, ALE must be low at this point. So, ok, it should be "if (ALE = '0') then". But I'm not sure if the time taken by logic (inverting and anding ALE), and buffering this signal/clock will offer the sufficient setup time for the test. I mean, will it always work? Can I change the speed grade or the family of the FPGA ? Do I need to use some type of time constraint? Luiz CarlosArticle: 110051
I know about the bscan blocks in the xilinx virtex devices (bscan_virtex4 for instance). With these blocks you can make your own interface by use of the boundary scan usercode instruction. Does something like this exists for altera devices? TIA, FrankArticle: 110052
jacko wrote: > Hi > > Now at version indi16.3.0 fixed logical error and made improvements in > cycle timing. slightly larger, but the older versions will not work due > to the logical error pin held at ground. approx 370 logical elements. > removed interupt facility cos this can be done with 2 indi cores and > correct wait /busfree chaining. > > have to work out how to promote clock, 40 pin external bus changes to > test16 top level. compiling for larger chip 1270 series to be able to > get IO devices on. > > should work at 60MHz which is 12MIPS. the forth i'm developing will > support device polling, and i have just written the arithmetic words. > > cheers > > http://indi.joox.net or http://indi.hpsdr.com or > http://indi.microfpga.com When you say 12 MIPS are you saying it takes 5 clock cycles to complete an instruction? That seems excessive. My CPU design is about 50% larger than yours, but it completes an instruction per clock cycle and can run at 77 to 100 MHz in current economy FPGAs. Why do you need so many clock cycles?Article: 110053
antonio bergnoli schrieb: > does anybody uses partitions in Xilinx tools by command line? It seem > they are available only in project navigator or in tcl environment. I > ask if it is possible to use them in a UNIX command line like bash. We would need a feature like this and a collegue of mine tried it out. He soon found a list of bugs that made "using partitions" in ISE 8.2 somewhat impossible ... I wonder if there are any real world projects with large FPGAs where this is working properly? have a look at: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23454 http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23456 http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=23459 http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=23453 the solution: "This is scheduled to be fixed in the next major release of the design tools." bye, MichaelArticle: 110054
Hi Goran, I did not understood your answer.. Do you mean that I need to create a system which contains two microblaze instances and afterwards export it to the ISE ? What if I want to have these two microblazes in two different systems and afterwards export them to ISE separately (my top.vhd will contain two system (microblaze) instances ? Can I do it ? Can I use two BMM files in that case ? Thanks in advance, Mordehay. G=F6ran Bilski wrote: > Just add the 2nd MicroBlaze in the XPS tool. > > G=F6ran Bilski > > <me_2003@walla.co.il> wrote in message > news:1160296753.788965.57640@m73g2000cwd.googlegroups.com... > > Hi all, > > I have a microblaze processor that I've built using the EDK and > > afterwards simulated and it seems to work fine. Now I need to make two > > instances of this Microblaze system in my design. > > Can I use the same module and instantiate it twice or I maybe I need to > > make a copy of the system and name it differently. If I instance the > > same module twice I figured out that it will be problematic to fill the > > BRAM with code data. > > Can anyone help ? > > Thanks, Mordehay. > >Article: 110055
Hi, I am trying to create a project within the nios software ide (which is based on eclipse). I want to have my project and source files on a different location as the .ptf file is. Is this possible? If I have my workspace at location A and create a new project I have to tell where the .ptf file is which describes my nios system. Let's say this file is at location B. The project wizard is creating the application and library directories in location B (while the workspace is at location A). Who knows the solution for this problem (or is it not possible)? FrankArticle: 110056
colin wrote: > All > > I am wondering what the record is for having the longest Xilinx webcase > open . > > All I asked was whether I can do boundary scan in a Coolrunner II using > sstl logic levels, over three weeks ago. > > Ten days ago they answered half my question but either bsdlanno has a > serious bug or their answer was wrong. > > I am left with polling xilinx every couple of days. > > Colin > trust me, "Open" is better than "closed" with the notation of something like "will be addressed in next major release". Once they get a CR assigned, they go into a black hole.Article: 110057
Colin, Are you trying to interface to the JTAG port using SSTL drivers and receivers? If so, then this is an interfacing question (and one that can be answered in 60 seconds with a simulator), and really has nothing to do with boundary scan at all. If you post the part family (eg Spartan 3E), and the SSTL interface class and supply voltages, I can run the simulation, and see if it works. AustinArticle: 110058
Hello, I'm currently looking at the virtex-4 configuration details and have a question about FDRI writes in the virtex4. My reference point is the virtex-2 configuration. In the virtex-2 configuration, FDRI writes always include a pad frame (except in the MFWR write case, but that's not what i'm looking at). Virtex-4 documentation makes no hint at such a frame. Indeed, uncompressed bitstreams show that the exact number of frames are written to the FDRI -- no pad frame there. However, compressed bitstreams do not show such behaviour: FDRI writes of isolated configured portions of the design seem to show pad frames being written (the last frame's FAR value has already been programmed earlier). I'm left guessing that either the bitstream programs some frames twice (unlikely), or there's some machine state condition that i'm missing, which indicates whether or not pad frames are needed during FDRI writes on the virtex-4. Can someone enlighten me on this? Kind regards, Jean-BaptisteArticle: 110059
rickman wrote: > jacko wrote: > > Hi > > > > Now at version indi16.3.0 fixed logical error and made improvements in > > cycle timing. slightly larger, but the older versions will not work due > > to the logical error pin held at ground. approx 370 logical elements. > > removed interupt facility cos this can be done with 2 indi cores and > > correct wait /busfree chaining. > > > > have to work out how to promote clock, 40 pin external bus changes to > > test16 top level. compiling for larger chip 1270 series to be able to > > get IO devices on. top level now 41 pin bus. > > should work at 60MHz which is 12MIPS. the forth i'm developing will > > support device polling, and i have just written the arithmetic words. > > > > cheers > > http-offline://indi.joox.net (no longer in use!!) Try http://indi.hpsdr.com or http://indi.microfpga.com > When you say 12 MIPS are you saying it takes 5 clock cycles to complete > an instruction? That seems excessive. My CPU design is about 50% > larger than yours, but it completes an instruction per clock cycle and > can run at 77 to 100 MHz in current economy FPGAs. Why do you need so > many clock cycles? all instructions are load -> alu -> store (using the 1 memory bus) this would make a two cycle minimum. for 2 memory accesses. each memory access takes 2 cycles, this is due to 1 cycle data out or in settling time before 1 cycle latching time. this allows cheap external memory use, internal use could reduce mem io to 1 cycle, but not designed in yet. so total = 4 clock cycles so far. then 2 instructions come in one word so 2 cycles for fetch but only 1 equiv cycle per instruction. so grand total of 5 cycles per instruction. is that clearer? the two cycle memory access also makes for an easier WAIT pin which halts the processor after the current memory access. memory access wait state insertion would have to occur via clock division. I think it may work, got rid of many logic errors by simplyfying some logic and changing the external bus, moved to 5 cycle per instruction throughput in design while maintaining low complexity. This required the removal of RAS, CAS addressing easy direct support, but SRAM is best at 128KB maximum memory size ( except when using CS[1] to isolate stack memory from program and data memory. (( CS[0] selects program=0 or data=1 memory.but no dictionary extension can occur if CS[0] is used like this. )) cheers. p.s. when you must simply fit in 330 LEs then this is whats needed.Article: 110060
oen_br schrieb: >>Clock signal for what? The BRAM inside the FPGA? NO WAY! > > > Yes, for the BRAM too. Why not? > The ALE, READ# and WRITE# signals will never overlap! You better learn about synchronous design. And glitching of clocks. > I don't know what 'XO' means, but I think you mean a crystal (it Yes. > reminded me Galactica Colonel Tigh :-) ). > Anyway the tranfer rate is 60MHz (mega transfers per second), so, to > sample ALE, etc, I will need a very high frequency clock signal (200MHz > maybe?). Even if it is possible, it will spend a lot of power! > Did I misunderstand you? > > There is no external SRAM, just the internal BRAM used as a mail box! > Two processors, each one using one BRAM port. Ahhhh, the FPGA is used to connect two processors, right? Hmm, in this xase why do you want to use a FPGA? There are dedicaded dual port memories, ready to use. www.idt.com Regards FalkArticle: 110061
oen_br wrote: >>In order for the CLOCK signal to go high, ALE must >>be low, in your logic, since (not ALE) is AND'd with >>WRITE# and READ#. So that implies inside your >>'if' the ALE='1' can never be true. >> >>Perhaps changing your logic to falling_edge(CLOCK) >>might fix it within your approach. Or invert the CLOCK >>signal from what it is now. > > > Hi David, > > The clock is right, I need to load the address at the falling edge of > ALE. > If you consider ALE falling edge generated the rising clock edge, ALE > must be low at this point. > So, ok, it should be "if (ALE = '0') then". > But I'm not sure if the time taken by logic (inverting and anding ALE), > and buffering this signal/clock will offer the sufficient setup time > for the test. I mean, will it always work? Can I change the speed grade > or the family of the FPGA ? > Do I need to use some type of time constraint? > > Luiz Carlos > The whole point is you want to write the first data at the address specified, the next data at the next address... what if when you load the first address you do a "-1" calculation right then? So when the first data is to get loaded, it does its "+1" and you're at the real address you wanted. So you are loading the address right at the start of each cycle, plenty of setup + hold time in all cases. I just don't like your logic of testing ALE inside the clocked section -- when the clock itself depends on ALE. This is really questionable, get that out of the picture and things will get simpler. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 110062
I'm surprised none have mentioned it, but the Xilinx ML501 has finally been released officially, even though it's not available online yet. Press release: http://www.xilinx.com/prs_rls/2006/silicon_vir/06103ml501.htm Board info: http://www.xilinx.com/ml501 It looks to be a very compelling kit. Unfortunately for me, the XC5VLX50 isn't supported by the WebPACK and unlike with the original ML401 release, software is _not_ included so unless you can afford the full ISE package also, don't bother. TommyArticle: 110063
David Ashley wrote:
> oen_br wrote:
>
>>>In order for the CLOCK signal to go high, ALE must
>>>be low, in your logic, since (not ALE) is AND'd with
>>>WRITE# and READ#. So that implies inside your
>>>'if' the ALE='1' can never be true.
>>>
>>>Perhaps changing your logic to falling_edge(CLOCK)
>>>might fix it within your approach. Or invert the CLOCK
>>>signal from what it is now.
>>
>>
>>Hi David,
>>
>>The clock is right, I need to load the address at the falling edge of
>>ALE.
>>If you consider ALE falling edge generated the rising clock edge, ALE
>>must be low at this point.
>>So, ok, it should be "if (ALE = '0') then".
>>But I'm not sure if the time taken by logic (inverting and anding ALE),
>>and buffering this signal/clock will offer the sufficient setup time
>>for the test. I mean, will it always work? Can I change the speed grade
>>or the family of the FPGA ?
>>Do I need to use some type of time constraint?
>>
>>Luiz Carlos
>>
>
>
> The whole point is you want to write the first data at
> the address specified, the next data at the next address...
> what if when you load the first address you do a "-1"
> calculation right then? So when the first data is to
> get loaded, it does its "+1" and you're at the real
> address you wanted. So you are loading the address
> right at the start of each cycle, plenty of setup + hold
> time in all cases.
>
> I just don't like your logic of testing ALE inside the
> clocked section -- when the clock itself depends on
> ALE. This is really questionable, get that out of the
> picture and things will get simpler.
>
> -Dave
>
I've been looking at this more...it seems easy on the
face of it but it's somewhat complicated.
You want when ALE goes from high to low for the
address latch to get the initial address you want to
load. And when READ# or WRITE# go from low to
high, you want the address latch to get its current
value plus one. This implies 2 clocks...which is out
of my experience but I suspect isn't synthesizable.
Now, if you could have a set-reset latch in the
picture that would make everything easy. When
ALE is high, the SR goes to 1. When READ# or
WRITE# go low, the SR goes to 0. Your original
post had the LOAD_ADDR signal getting set
when there was a rising_edge of ALE, and
an async clear when READ# or WRITE# go
low, which is the 2 clock problem in the first
place. When would do it is an async set instead
of the clocked set. You don't need any clocking
on this.
I suppose you could describe the logic as 2
nand gates. I looked at xst.pdf and couldn't
find a simple set/reset flip flop.
Unisim has an entity FDCP which is:
D Flip-Flop with Asynchronous Clear and Preset
architecture FDCP_V of FDCP is
begin
VITALBehavior : process(C, CLR, PRE)
variable FIRST_TIME : boolean := true ;
begin
if (FIRST_TIME = true) then
Q <= TO_X01(INIT);
FIRST_TIME := false;
end if;
if (CLR = '1') then
Q <= '0';
elsif (PRE = '1') then
Q <= '1';
elsif (rising_edge(C)) then
Q <= D after 100 ps;
end if;
end process;
end FDCP_V;
So that would translate to
if ALE = '1' then
LOAD_ADDR <= '1';
else if READ# = '0' or WRITE# = '0' then
LOAD_ADDR <= '0';
end if;
However this is an implied latch...which is
probably ok in this instance because there is no
combinatorial feedback.
I'm in over my head. I wish one of the gurus would
offer some advice here. :)
-Dave
--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Article: 110064Henrik Pedersen wrote: > GaLaKtIkUs™ wrote: > >> Try to type in a shell: comxlib --s mti_se -arch all -l all -lib all -w >> -smartmodel_setup >> If it doesn't compile tell me the exact error message. >> Be sure that the modelsim's binary files are accessible (update you >> PATH environment variable) >> >> On Oct 8, 11:08 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >>> GaLaKtIkUs™ wrote: >>>> Hi, >>>> After you got the libraries compiled using the compxlib tool (included >>>> in ISE), you shouldn't get any trouble. >>>> Please precise the exact problem you encountred >>>> On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >>>>> Hey there >>>>> I have a lot of trouble finding directions/guides/manuals on how to >>>>> get subject working. >>>>> Anyone able to point me in the right direction ? >>>>> HenrikI'm a step further from that. >>> What libs should i compile. >>> >>> Let me resume for a moment. >>> Downloaded WebPack 8,2,03i and installed it. >>> Done a few recomended jumps and it works. >>> >>> When i click "Simulate Behavorial" i get a error saying: >>> Model technologies vsim cannot be found be Project navigator. .... >>> >>> Where do i start ? >>> >>> Henrik > > > Tried above solution with the folowing result: > > ./compxlib --s mti_se -arch all -l all -lib all -w -smartmodel_setup > ./compxlib: error while loading shared libraries: libPersonalityModule.so: > cannot open shared object file: No such file or directory > > The module in question is located in the same directory. > What would be a logical next step to try ? . /path/to/ise/settings.sh (the dot and the following space are important !) SylvainArticle: 110065
oen_br wrote:
> ____
> ALE ___/ \__________________________________________________
CLK _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
> _______________ __ __ __ ______
> WRITE# \______/ \______/ \______/ \______/
> ________ ________ ________ ________ ________
> DTADD ____/ ADDR \/ DATA0 \/ DATA1 \/ DATA2 \/ DATA3 \______
> \________/\________/\________/\________/\________/
>
> But the clock is a delayed version ALE, READ# and WRITE#, so the
> setup/hold times will no be met!
No, you want the continuous clock that
generated ALE. In a synchronous system,
ALE is an input, not a clock.
-- Mike Treseler
Article: 110066jacko wrote: > all instructions are load -> alu -> store (using the 1 memory bus) > this would make a two cycle minimum. for 2 memory accesses. > each memory access takes 2 cycles, this is due to 1 cycle data out or > in settling time before 1 cycle latching time. this allows cheap > external memory use, internal use could reduce mem io to 1 cycle, but > not designed in yet. > so total = 4 clock cycles so far. > then 2 instructions come in one word so 2 cycles for fetch but only 1 > equiv cycle per instruction. > so grand total of 5 cycles per instruction. > > is that clearer? the two cycle memory access also makes for an easier > WAIT pin which halts the processor after the current memory access. > memory access wait state insertion would have to occur via clock > division. That is a big difference. My design only runs on internal FPGA memory. It is intended to be a chip controller, not a general purpose CPU. > I think it may work, got rid of many logic errors by simplyfying some > logic and changing the external bus, moved to 5 cycle per instruction > throughput in design while maintaining low complexity. This required > the removal of RAS, CAS addressing easy direct support, but SRAM is > best at 128KB maximum memory size ( except when using CS[1] to isolate > stack memory from program and data memory. (( CS[0] selects program=0 > or data=1 memory.but no dictionary extension can occur if CS[0] is used > like this. )) > > cheers. > > p.s. when you must simply fit in 330 LEs then this is whats needed. What is the application for this design?Article: 110067
> You better learn about synchronous design. And glitching of clocks. Falk, I'm aware of the danger of gererated clocks, but in this case I couldn't see any problem (at least until now). The signals are clean and have some nano-seconds between their activation. > Ahhhh, the FPGA is used to connect two processors, right? > Hmm, in this xase why do you want to use a FPGA? There are dedicaded > dual port memories, ready to use. Not really. The FPGA, besides other functions, connects 4 DSPs, a shared external SRAM and a PCI controller, everybody talking to everybody. I thought this kind of problem was very common (combinatorial clocks using it's source signals as clock enables)! Thanks, Luiz CarlosArticle: 110068
> No, you want the continuous clock that > generated ALE. In a synchronous system, > ALE is an input, not a clock. Mike, I don't have access to this clock. Luiz Carlos.Article: 110069
> I just don't like your logic of testing ALE inside the > clocked section -- when the clock itself depends on > ALE. This is really questionable, get that out of the > picture and things will get simpler. Hi Dave, Yes, that's the point. I also don't like it, but if possible and safe, it would be the easier way. Can it be made in a safe way? This is what I'm trying to learn! Luiz Carlos.Article: 110070
Austin Lesea wrote: > Note that due to the memory required, the LX330 can ONLY be complied on > a 64 bit Linux machine.... there are just too many logic cells, and too > much routing. 8 Gbytes is about what you need, and windoze can't handle > it (at all). That says a lot about the required computing past Virtex-5, as things scale up another factor of two or four. I assume the total cpu cycles required for P&R are scaling even faster, making both memory and total instruction counts both serious bottlenecks. I assume you are supporting both Itanium IA64 and AMD _x64 architectures? Desktop 64bit machines this size aren't exactly plentiful, server class machines are a bit more plentiful, but still frequently pretty expensive. I have two quad, and three dual Itanium Linux servers here in an MPI cluster, each with at least 8GB. Plus a large MPI/PVM cluster farm of Intel P3 and P4 machines, but I suspect that's pretty rare in this readership given the stiff costs of building HPC clusters. None of them are easy to work near, as the required airflow makes them very noisy individually, and aggregated into a server room. With 8GB data sets, many algorithms fail to scale since there isn't enough data locality to make effective use of either L2 or L3 caches which are at most in the 9MB range. Relatively random access to an 8GB data set generally brings the processor to a grinding halt on memory, with a net instruction rate about 1-2% of L1 cache performance. Generally applications which have out grown 32 bit cpu caches, require nearly a complete rewrite with new algorithms and new data structures to gain enough locality to get effective/good memory performance in a large address space 64 bit machine. Almost always a major restructuring based on some flavor of divide and conquer is required to bring the memory footprint back inside L2/L3 caches. Generally this requires re-writing most, or all of the C++ code back into normal C to get rid of the dynamic allocation, randomly allocated link lists, and other data structure changes necessary to manage memory foot print and cache performance. Redesign for SMP and Clusters becomes critical, as more CPU/Caches become available to concurrently process a larger active working set than a fast cpu/core with a large cache can handle alone. Once your people start considering divide and conquer attacks to split the operation up for SMP threads or MPI/PVM clusters, it's certainly worth taking a better look at the problem for partioning it to run on a N-WAY SMP 32bit machine AND clusters too. Most of the newer high end 32 bit Intel processors will also handle 8+ GB in a machine, but only 2GB per process under Linux. Using divide and conquer the application should easily function as a 4-8 process application with some modest restructuring. With multiple cores/cpus now typical in high end SMP 32 bit machines, this should be Xilinix's primary strategy for a target host environment. I'm suprised that Xilinx didn't realize this before now, and roll out a linux SMP/cluster version of it's tools before getting backed into the 64 bit corner. > > Regardless of the 'open source' debate, or any other postings, the FPGA > software is much, much larger, and more complex than anyone seems to > comprehend (one of the greatest barriers to entry for anyone thinking > about competition). As such, I am hopeful that some of the musing here > will get folks thinking, but realisitically, I am doubtful as the people > responsible are daily trying to make things faster, and better as part > of their job. > > Austin Sometime the "we've always done it that way, it's the only way" problem becomes severe, as limited resources prevent considering solutions requiring a major investment ... IE a major rewrite with new algorithms and internal architectures. Data set and algorithmic scaling into HPC class facilities isn't a typical skill set for average programmers. Maybe one in a few thousand programmers have experience at this level, and probably fewer with EDA experience. There are probably far more open source programmers with experience at this level, than there are Xilinx EDA programmers that are comfortable architecting HPC SMP/Cluster software solutions. Many of the same folks have interest in high end reconfigurable computing too ... which seriously needs tools capable of doing P&R in near real-time. And then, there is always the NIH problem ....Article: 110071
oen_br schrieb: > Not really. > The FPGA, besides other functions, connects 4 DSPs, a shared external > SRAM and a PCI controller, everybody talking to everybody. In this case, a SYNCHRONOUS bus is strongly suggested. AFAIK many DSPs output the bus clock along with all other signals. > I thought this kind of problem was very common (combinatorial clocks > using it's source signals as clock enables)! This is bad bad hack an shounld be avoided as much as possible. Maybe sometimes even more ;-) Regards FalkArticle: 110072
Sylvain Munaut wrote: > Henrik Pedersen wrote: >> GaLaKtIkUs? wrote: >> >>> Try to type in a shell: comxlib --s mti_se -arch all -l all -lib all -w >>> -smartmodel_setup >>> If it doesn't compile tell me the exact error message. >>> Be sure that the modelsim's binary files are accessible (update you >>> PATH environment variable) >>> >>> On Oct 8, 11:08 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >>>> GaLaKtIkUs? wrote: >>>>> Hi, >>>>> After you got the libraries compiled using the compxlib tool (included >>>>> in ISE), you shouldn't get any trouble. >>>>> Please precise the exact problem you encountred >>>>> On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >>>>>> Hey there >>>>>> I have a lot of trouble finding directions/guides/manuals on how to >>>>>> get subject working. >>>>>> Anyone able to point me in the right direction ? >>>>>> HenrikI'm a step further from that. >>>> What libs should i compile. >>>> >>>> Let me resume for a moment. >>>> Downloaded WebPack 8,2,03i and installed it. >>>> Done a few recomended jumps and it works. >>>> >>>> When i click "Simulate Behavorial" i get a error saying: >>>> Model technologies vsim cannot be found be Project navigator. .... >>>> >>>> Where do i start ? >>>> >>>> Henrik >> >> >> Tried above solution with the folowing result: >> >> ./compxlib --s mti_se -arch all -l all -lib all -w -smartmodel_setup >> ./compxlib: error while loading shared libraries: >> libPersonalityModule.so: cannot open shared object file: No such file or >> directory >> >> The module in question is located in the same directory. >> What would be a logical next step to try ? > > . /path/to/ise/settings.sh > > (the dot and the following space are important !) > > Sylvain Not sure on the exact syntax directory to execute the command. Could you be a little more specific, please ? HenrikArticle: 110073
> In this case, a SYNCHRONOUS bus is strongly suggested. AFAIK many DSPs > output the bus clock along with all other signals. Yes, but not the parallel port of ADSP-21363! > This is bad bad hack an shounld be avoided as much as possible. Maybe > sometimes even more ;-) I would like to have the DSP peripheral clock, but I have to work with what is available. Luiz Carlos.Article: 110074
oen_br wrote:
>> No, you want the continuous clock that
>> generated ALE. In a synchronous system,
>> ALE is an input, not a clock.
>
> Mike, I don't have access to this clock.
In that case, I would use a PLL or add an oscillator
to resynchronize everything to one clock.
-- Mike Treseler
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