Messages from 124950

Article: 124950
Subject: Graphical VHDL Viewer ?
From: "Stéphane Julhes" <sjulhes@adeneo.adetelgroup.com>
Date: Fri, 12 Oct 2007 10:32:00 +0200
Links: << >> << T >> << A >>

Hi all,

Does anyone know a free/simple software that would use vhdl files to produce 
a graphical view ?
The goal is to have a easier and faster read of the architecture of a vhdl 
file and its components.

Thanks.

Stéphane.

Article: 124951
Subject: Re: Graphical VHDL Viewer ?
From: csantos <cayetanosantos@gmail.com>
Date: Fri, 12 Oct 2007 09:30:11 -0000
Links: << >> << T >> << A >>

Hi St=E9phane,

    You can use ISE (or not!) from Xilinx, since release 8 you have
the possibility to show the schematic equivalent of your hdl, try
right mouse button over 'design tools' or similar, after synthesis
using XST, then you can browse into the blocks, and so on. I guess
that using symplify or other tools you have something equivalent.

good luck

csb

On 12 oct, 10:32, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

Article: 124952
Subject: Re: Graphical VHDL Viewer ?
From: "Stéphane Julhes" <sjulhes@adeneo.adetelgroup.com>
Date: Fri, 12 Oct 2007 12:44:48 +0200
Links: << >> << T >> << A >>

Hi,

Thanks for your answer.

I saw the RTL viewer but you have to synthesis your design.
My goal is to view a simple level of design without providing the source 
file of each sub component.
Which can be quite long for complexe designs.

Stéphane.

"csantos" <cayetanosantos@gmail.com> a écrit dans le message de news: 
1192181411.264969.300860@q5g2000prf.googlegroups.com...
Hi Stéphane,

    You can use ISE (or not!) from Xilinx, since release 8 you have
the possibility to show the schematic equivalent of your hdl, try
right mouse button over 'design tools' or similar, after synthesis
using XST, then you can browse into the blocks, and so on. I guess
that using symplify or other tools you have something equivalent.

good luck

csb

On 12 oct, 10:32, "Stéphane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to 
> produce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> Stéphane.

Article: 124953
Subject: Re: Cyclone II SSTL-2 on-chip resistors
From: Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com>
Date: Fri, 12 Oct 2007 04:10:58 -0700
Links: << >> << T >> << A >>

Ok, thanks for the info.

So I think I should use Class II for data lines (two 50 ohm
terminations connected to Vtt, at both ends), and Class I (one 50 ohm
termination connected to Vtt, at the receiver) for all the others ;
and use the on-chip 25 ohm series resistors at the FPGA, and the 25-
ohm series resistors included on my DDRAM module. No additional
termination is required for clock lines (except the FPGA's on chip
series resistor) as these differential signals already have a 120 ohm
resistor across them on the DDRAM module. Is that correct (given the
price of 4-layer prototype boards and the difficulty in reworking BGA
packages, I'd like to be absolutely certain) ?

Article: 124954
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Kees Bakker <spam@altium.nl>
Date: Fri, 12 Oct 2007 13:42:33 +0200
Links: << >> << T >> << A >>

H. Peter Anvin wrote:

> I just got an email from Altera, saying:
> 
> ear Altera Customer,
> 
> The new Quartus® II Web Edition Software version 7.2 is now available 
> for download.
> New features include:
> 
>       [...blah...]
>      * Get complete OS support for Linux in addition to 64-bit Windows
>        Vista
> 
> However, on the download page they still have:
> 
> For Solaris or Linux support, purchase an Altera software subscription.
> 
> Anyone knows what the deal is?

Doesn't Altera make use of the MainWin runtime environment to allow their tools to
run on Linux or Solaris? If so, then they cannot give away free copies of their
own Altera tools on Linux without having to pay royalties to MainSoft.

I have no real proof that this is the case, but it sounds plausible to me. That doesn't
mean I like it. Hell no, I really wish they would develop native Linux tools.
--
Kees

Article: 124955
Subject: Re: Xilinx OCM memory use limitations ?
From: xenix <lastval@gmail.com>
Date: Fri, 12 Oct 2007 11:46:28 -0000
Links: << >> << T >> << A >>

On Oct 12, 9:32 am, "SJU" <sjul...@adeneo.adetelgroup.com> wrote:
> Hi all,
>
> We are building a very simple SOC ( PPC 405, internal memory, UART light)=
 in
> a V4FX60, with a very simple firmware.
> The point is that when we use the PLB_BRAM memory, the GDB debugger works
> fine, but wneh we use the OCM memories, the debugger behaves in astrange
> way. When we download the file then it goes in a assembly state and execu=
tes
> nothing, I guess it went in some exceptions or executed some unexpected
> instructions.
>
> Is there something to know to use the OCM memories ?
> Are there some configuration to make in EDK ?
>
> Thanks for your help.
>
> St=E9phane.

Hello Stephane. How do you write to the OCM Bram? i am using a VHDL
file in the PORTB. probably i dont write in the correct location. But
the simulation is strange to me also. Dont forget if you are using
port B to set the clk to sys_clk_pin and the Reset to sys_bus_rst.

regards

Article: 124956
Subject: Re: Graphical VHDL Viewer ?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 12 Oct 2007 05:50:40 -0700
Links: << >> << T >> << A >>

Stéphane Julhes wrote:

> I saw the RTL viewer but you have to synthesis your design.
> My goal is to view a simple level of design without providing the source 
> file of each sub component.

I use the quartus rtl viewer.
  example:
  http://home.comcast.net/~mike_treseler/uart.pdf

If I synthesize a structural entity with
null architectures, I get just the top
level block diagram.

        -- Mike Treseler

Article: 124957
Subject: Re: Graphical VHDL Viewer ?
From: SKatsyuba@gmail.com
Date: Fri, 12 Oct 2007 07:17:24 -0700
Links: << >> << T >> << A >>

On Oct 12, 11:32 am, "St=E9phane Julhes"
<sjul...@adeneo.adetelgroup.com> wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

There are Advanced Dataflow Viewer in Aldec Active-HDL and Dataflow
Viewer in ModelSim. But they are not free. They are both pretty
similar, after compiling the design you can browse its graphical
representation consisting of architectures, processes, ports and
connections. You can also use Dataflow Viewer for debugging during
simulation.

Advanced Dataflow demo from Aldec:
http://www.aldec.com/products/active-hdl/multimediademo/movies/advanced_dat=
aflow/

Article: 124958
Subject: Re: HELP, how to time constraint part of a design?
From: fpgabuilder <fpgabuilder-groups@yahoo.com>
Date: Fri, 12 Oct 2007 14:28:34 -0000
Links: << >> << T >> << A >>

On Oct 11, 10:51 am, Duane Clark <junkm...@junkmail.com> wrote:
> fpgabuilder wrote:
>
> > There may be other issues with you design, but to solve your immediate
> > problem you can declare the 40MHz clock a separate clock/timing group.
>
> Yes, that is what I said in my first post in this thread ;)

Sorry! I missed that.

Article: 124959
Subject: Re: Graphical VHDL Viewer ?
From: "dadabuley@gmail.com" <dadabuley@gmail.com>
Date: Fri, 12 Oct 2007 09:05:28 -0700
Links: << >> << T >> << A >>

On 10=D4=C212=C8=D5, =CF=C2=CE=E74=CA=B132=B7=D6, "St=A8=A6phane Julhes" <s=
jul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=A8=A6phane.

you can try FPGA Advantage, it's mentor product. I use this for
develop for years and it's very easy for generate graphic VHDL.

Article: 124960
Subject: Re: Unrouted nets (Xilinx FPGA Editor)
From: "dadabuley@gmail.com" <dadabuley@gmail.com>
Date: Fri, 12 Oct 2007 09:10:41 -0700
Links: << >> << T >> << A >>

On 10 10 ,   4 50 , "Ju, Jian" <ee...@polyu.edu.hk> wrote:
> Hi all,
>
> I meet some problems in the P&R process of my design.
>
> The Place & Route Report shows the following messages. Because it stoped at
> Phase 6 for a long time, I paused it and it shows there's 1 net unrouted.
>
> ----------------- Place & Route Report ------------------------
> Phase 6: 2645 unrouted; (0)      REAL time: 17 secs
>
> Ctrl-C interrupt detected.
>
> Please choose one of the following options:
>  1. Ignore interrupt and continue processing.
>  2. Exit program normally at next checkpoint.
>     This will save the best results so far
>     after concluding the current processing.
>  3. Exit program immediately.
>  4. Cancel the current job and move to the next one
>      at the next check point.
>
> Enter choice --> 2
> User requested termination
> Phase 7: 1 unrouted; (0)      REAL time: 3 mins 2 secs
> -------------------------------------------------------------------------
>
> I opened the ncd file and shows the Unrouted Nets visually. I changed the
> position of one of the SLICE  and then it automatically re-route. The
> previously Unrouted Nets dissapered and are no longer listed.
>
> But I'm not completely sure that all of the nets have been routed properly,
> because in the following step, Generated Programming File, it complains that
> ERROR:PhysDesignRules:801 - The network <digital_inst/inst1/fir1/N42592> has
> <1>   routing conflicts.
> ERROR:PhysDesignRules:801 - The network <digital_inst/inst1/fir1/N42591> has
> <1>   routing conflicts.
> ERROR:Bitgen:25 - DRC detected 2 errors and 24 warnings.
>
> I checked the ncd file again in the FPGA Editor, however, it seems these two
> nets have already been routed. what is "the routing conflicts" meant to? Any
> possible solutions?
>
> I would appreciated your help,
> Ju, Jian

maybe what you need to do is run generate program file again

Article: 124961
Subject: Re: Graphical VHDL Viewer ?
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 12 Oct 2007 16:19:42 GMT
Links: << >> << T >> << A >>

"Stéphane Julhes" <sjulhes@adeneo.adetelgroup.com> wrote:

>Hi all,
>
>Does anyone know a free/simple software that would use vhdl files to produce 
>a graphical view ?
>The goal is to have a easier and faster read of the architecture of a vhdl 
>file and its components.

doxygen?

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 124962
Subject: NgdBuild:455 Multiple Drivers
From: lzkelley@gmail.com
Date: Fri, 12 Oct 2007 18:55:00 -0000
Links: << >> << T >> << A >>

I'm working with XILINX ise 9.2i; designing a deserializer & using 2
DCM's in sequence to generate 4 100MHz clocks (each 90 degrees out of
phase) from the 50MHz local clock on a Spartan-3 FPGA

The error i'm getting:

ERROR:NgdBuild:455 - logical net 'CLK100X' has multiple driver(s):
     pin CLK2X on block clockdoubler/DCM_INST with type DCM,
     pin PAD on block CLK100X with type PAD

regarding the following code:

dcm1 clockdoubler (
    .CLKIN_IN(CLKIN), //50MHz local spartan-3 clock
    .RST_IN(RST),
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT1),
    .CLK0_OUT(CLK0),
    .CLK2X_OUT(CLK100X), //100MHz clock out
	 .LOCKED_OUT(LOCKED1)
    );


dcm2 clockseparater (
    .CLKIN_IN(CLK100X), //100MHz input
	 .RST_IN(LOCKED1),
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT2),
    .CLK0_OUT(CLK100A),    //0 phase diff
    .CLK90_OUT(CLK100B),   //90 deg
    .CLK180_OUT(CLK100C),  //180 deg
    .CLK270_OUT(CLK100D),  //270 deg
    .LOCKED_OUT(LOCKED2),
    .STATUS_OUT(STATUS2)
    );

For the
i changed the buffered output of the first DCM to be "local routing"
instead of a global buf, which i know can cause this same error
message, but im still getting the error... i have no idea whats wrong
with it, any help would be greatly appreciated! Thanks

Article: 124963
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Fri, 12 Oct 2007 12:35:43 -0700
Links: << >> << T >> << A >>

Kees Bakker wrote:
> 
> Doesn't Altera make use of the MainWin runtime environment to allow their tools to
> run on Linux or Solaris? If so, then they cannot give away free copies of their
> own Altera tools on Linux without having to pay royalties to MainSoft.
> 
> I have no real proof that this is the case, but it sounds plausible to me. That doesn't
> mean I like it. Hell no, I really wish they would develop native Linux tools.
> 

That has certainly been the case in the past (although only for the GUI 
tools -- the CLI tools worked just fine without.)  I was hoping that the 
announcement meant they had fixed that (after all, Xilinx already 
cleaned that up.)

There are some really good cross-platform development environments 
without the issues of MainWin; Qt comes to mind.

	-hpa

Article: 124964
Subject: Re: NgdBuild:455 Multiple Drivers
From: "John_H" <newsgroup@johnhandwork.com>
Date: Fri, 12 Oct 2007 12:45:58 -0700
Links: << >> << T >> << A >>

<lzkelley@gmail.com> wrote in message 
news:1192215300.249202.47690@y27g2000pre.googlegroups.com...
> I'm working with XILINX ise 9.2i; designing a deserializer & using 2
> DCM's in sequence to generate 4 100MHz clocks (each 90 degrees out of
> phase) from the 50MHz local clock on a Spartan-3 FPGA
>
> The error i'm getting:
>
> ERROR:NgdBuild:455 - logical net 'CLK100X' has multiple driver(s):
>     pin CLK2X on block clockdoubler/DCM_INST with type DCM,
>     pin PAD on block CLK100X with type PAD
>
> regarding the following code:
>
> dcm1 clockdoubler (
>    .CLKIN_IN(CLKIN), //50MHz local spartan-3 clock
>    .RST_IN(RST),
>    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT1),
>    .CLK0_OUT(CLK0),
>    .CLK2X_OUT(CLK100X), //100MHz clock out
> .LOCKED_OUT(LOCKED1)
>    );
>
>
> dcm2 clockseparater (
>    .CLKIN_IN(CLK100X), //100MHz input
> .RST_IN(LOCKED1),
>    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT2),
>    .CLK0_OUT(CLK100A),    //0 phase diff
>    .CLK90_OUT(CLK100B),   //90 deg
>    .CLK180_OUT(CLK100C),  //180 deg
>    .CLK270_OUT(CLK100D),  //270 deg
>    .LOCKED_OUT(LOCKED2),
>    .STATUS_OUT(STATUS2)
>    );
>
> For the
> i changed the buffered output of the first DCM to be "local routing"
> instead of a global buf, which i know can cause this same error
> message, but im still getting the error... i have no idea whats wrong
> with it, any help would be greatly appreciated! Thanks

Read the message carefully.  It appears that you have another item (an 
input, perhaps) called CLK100X.  If you have that input *and* the DCM both 
generating a signal called CLK100X, you'll have a conflict.  If you search 
your code for all instances of that name, you might find a forgotten signal.

Article: 124965
Subject: Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?
From: Eric <sendthis@removethis.yahoo_andthis.com>
Date: Sat, 13 Oct 2007 00:07:26 -0400
Links: << >> << T >> << A >>

I've been scouring the newsgroups for DRAM discussions and I ran into 
several that discussed the timing even over "short" distances.

I'm trying to design a DRAM controller to write/read a pattern to DRAM 
at 18-20 inches. I'm having problems with the controller right now, but 
am I wasting my time? It has to be DRAM b/c we are testing the devices 
for a radiation environment.

I was thinking of running it at ~10-20Mhz.

Thanks,
Eric

Article: 124966
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com>
Date: Sat, 13 Oct 2007 01:30:24 -0700
Links: << >> << T >> << A >>

No, it seems you still have to pay $2000 more if you want to use Linux
and stay legal.
Altera sucks.

Article: 124967
Subject: Quartus II Web Edition License - SOPC Builder generation?
From: Eric <sendthis@removethis.yahoo_andthis.com>
Date: Sat, 13 Oct 2007 04:42:21 -0400
Links: << >> << T >> << A >>

If I have the web edition license, is it still possible to use the SOPC 
builder?

I'm just trying to build one of the projects in the tutorial...

Thanks,
Eric


------------------------
This is the error I get
------------------------

Altera SOPC Builder Version 7.00 Build 33
Copyright (c) 1999-2006 Altera Corporation.  All rights reserved.

# 2007.10.13 04:40:11 (*) mk_custom_sdk starting
# 2007.10.13 04:40:11 (*) Reading project 
F:/fpga_stuff/dram_system_sopc/nios_system.ptf.
# 2007.10.13 04:40:12 (*) Finding all CPUs
# 2007.10.13 04:40:12 (*) Finding all available components
# 2007.10.13 04:40:12 (*) Reading 
F:/fpga_stuff/dram_system_sopc/.sopc_builder/install.ptf
# 2007.10.13 04:40:12 (*) Found 67 components
# 2007.10.13 04:40:13 (*) Finding all peripherals
# 2007.10.13 04:40:13 (*) Finding software components
# 2007.10.13 04:40:13 (*) (Legacy SDK Generation Skipped)
# 2007.10.13 04:40:13 (*) (All TCL Script Generation Skipped)
# 2007.10.13 04:40:13 (*) (No Libraries Built)
# 2007.10.13 04:40:13 (*) (Contents Generation Skipped)
# 2007.10.13 04:40:13 (*) mk_custom_sdk finishing
# 2007.10.13 04:40:13 (*) Starting generation for system: nios_system.
..
# 2007.10.13 04:40:15 (*) Running Generator Program for cpu_0
# 2007.10.13 04:40:17 (*)   Checking for plaintext license.
# 2007.10.13 04:40:17 (*)   Plaintext license not found.
# 2007.10.13 04:40:17 (*)   Checking for encrypted license (non-evaluation).
# 2007.10.13 04:40:18 (*)   Encrypted license not found.  Defaulting to 
OCP evaluation license (produces a time-limited SOF)

ERROR:
In object '' of class e_process: can't access `user_attributes_names' field
known fields are:
  _AUTOLOAD_ACCEPT_ALL
  _asynchronous_contents
  _built
  _clock
  _contents
  _creation_history
  _object_list
  _order
  _parent_set
  _project_set
  _reset
  _reset_default
  _signal_list
  _vhdl_files
  _vhdl_fixes
  _vhdl_variables
  clock_level
  comment
  indent
  isa_dummy
  name
  output_as_muxes_and_registers
  paragraph
  reset_level
  sensitivity_list
known pointers are:
  _parent
  _project
keys:
  _AUTOLOAD_ACCEPT_ALL
  _permitted
  _pointers
by the way, this object is a dummy

           Error: Generator program
                  for module 'cpu_0' did NOT run successfully.
generator cmd was 'c:/altera/70/quartus//bin/perl/bin/perl 
-Ic:/altera/70/quartus/sopc_builder/bin 
-Ic:/altera/70/quartus/sopc_builder/bin/europa 
-Ic:/altera/70/quartus/sopc_builder/bin/perl_lib -I. 
-IC:/altera/72/ip/nios2_ip/altera_nios2 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pio 
-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_interrupt_vector 
-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instruction 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_onchip_memory2 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_onchip_memory 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_mutex 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_burst_adapter 
-IC:/altera/72/ip/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler_adapter 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cf 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_spi 
-IC:/altera/72/ip/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_user_defined_interface 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pipeline_bridge 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_2s60_rohs 
-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_bitswap 
-IC:/altera/72/ip/sopc_builder_ip/altera_sopc_builder 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cfi_flash 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pll 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_sgdma 
-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_floating_point 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_epcs_flash_controller 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_upstream_pipeline 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_kit_stratix_edition_sram 
-IC:/altera/72/ip/triple_speed_ethernet/lib/sopc_builder/altera_triple_speed_ethernet 
-IC:/altera/72/ip/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_lan91c111 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_kit_stratix_edition_sram2 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_1s40 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_uart 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_new_sdram_controller 
-IC:/altera/72/ip/ddr2_high_perf/lib/sopc_builder/ddr2_high_perf 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_waitrequest_pipeline 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_slave_y 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_clock_adapter 
-IC:/altera/72/ip/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler_adapter 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_mailbox 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_asmi 
-IC:/altera/72/ip/sopc_builder_ip/amd_avalon_am29lv065d_flash 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_lcd_16207 
-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_endian_converter 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_jtag_uart 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_master_y 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_endian_adapter 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_cyclone_1c20 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_1s10_es 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_tri_state_bridge 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_cyclone_2c35 
-IC:/altera/72/ip/sopc_builder_ip/no_legacy_module 
-IC:/altera/72/ip/sopc_builder_ip/amd_avalon_am29lv128m_flash 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cy7c1380_ssram 
-IC:/altera/72/ip/nios2_ip/altera_nios2 
-IC:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder/ddr_sdram_component 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cs8900 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_performance_counter 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_sysid 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_fifo 
-IC:/altera/72/ip/ddr_high_perf/lib/sopc_builder/ddr_high_perf 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_2s60_es 
-IC:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder/ddr2_sdram_component 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_timer 
-IC:/altera/72/ip/ddr3_high_perf/lib/sopc_builder/ddr3_high_perf 
-IC:/altera/72/ip/nios2_ip/altera_nios_multiply 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_dma 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_1s10 
-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_clock_crossing 
-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_2s60 
C:/altera/72/ip/nios2_ip/altera_nios2/cpu_core_select.pl 
--system_name=nios_system --target_module_name=cpu_0 
--system_directory=F:/fpga_stuff/dram_system_sopc 
--sopc_directory=c:/altera/70/quartus/sopc_builder 
--sopc_lib_path=F:/fpga_stuff/dram_system_sopc+C:/altera/72/ip/pci_express_compiler/lib/sopc_builder+C:/altera/72/ip/ddr3_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr2_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr_high_perf/lib/sopc_builder+C:/altera/72/ip/sopc_builder_ip+C:/altera/72/ip/nios2_ip+C:/altera/72/ip/triple_speed_ethernet/lib/sopc_builder+C:/altera/72/ip/pci_compiler/lib/sopc_builder+C:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder+c:/altera/70/quartus/sopc_builder/components 
--generate=1 --verbose=0 --software_only=0 
--module_lib_dir=C:/altera/72/ip/nios2_ip/altera_nios2 
--sopc_quartus_dir=c:/altera/70/quartus/ --projectname=dram_system.quartus'


Error in processing.  System NOT successfully generated.

Article: 124968
Subject: Re: Graphical VHDL Viewer ?
From: csantos <cayetanosantos@gmail.com>
Date: Sat, 13 Oct 2007 02:52:55 -0700
Links: << >> << T >> << A >>

Hi,

    There is a simple solution, just use the 'black_box' constraint
applied to your top lovel blocks, you can synthetize without needing
to provide the code of the components, this will create a schematic of
the top level, does it help?

csb

On 12 oct, 12:44, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi,
>
> Thanks for your answer.
>
> I saw the RTL viewer but you have to synthesis your design.
> My goal is to view a simple level of design without providing the source
> file of each sub component.
> Which can be quite long for complexe designs.
>
> St=E9phane.
>
> "csantos" <cayetanosan...@gmail.com> a =E9crit dans le message de news:
> 1192181411.264969.300...@q5g2000prf.googlegroups.com...
> Hi St=E9phane,
>
>     You can use ISE (or not!) from Xilinx, since release 8 you have
> the possibility to show the schematic equivalent of your hdl, try
> right mouse button over 'design tools' or similar, after synthesis
> using XST, then you can browse into the blocks, and so on. I guess
> that using symplify or other tools you have something equivalent.
>
> good luck
>
> csb
>
> On 12 oct, 10:32, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
> wrote:
>
> > Hi all,
>
> > Does anyone know a free/simple software that would use vhdl files to
> > produce
> > a graphical view ?
> > The goal is to have a easier and faster read of the architecture of a v=
hdl
> > file and its components.
>
> > Thanks.
>
> > St=E9phane.

Article: 124969
Subject: Newbie,the simplest way to program an FPGA at home?
From: "blisca" <bliscachiocciolinatiscali.it>
Date: Sat, 13 Oct 2007 15:14:20 +0200
Links: << >> << T >> << A >>

Hi
i 'm trying to practice VHDL at home,until today i did some things using
obsolete Lattice and Xilinx CPLD.
One year ago i bought a Spartan educational board from  Digilent with a
programming cable included,so i can program obsolete Virtex FPGAs via JTAG
and this could be enough for educational purposes.

Now i would like to implement some kind of self programming at power-on,for
Xilinx Virtex.

I know the somepossible methods are :

Flash memory via microcontroller ,the problem is how can i program the Flash
itself?
Specific memory in master serial mode,are they available by distributor as
Rs or Farnell in Italy?
EEprom via CPLD as shown in
www.xilinx.com/bvdocs/appnotes/xapp137.pdf

What do you suggest?


Thanks
diego

Article: 124970
Subject: Re: JTAG interconnect testing, prototypes
From: "Tony Burch" <tony@burched.com.au>
Date: Sat, 13 Oct 2007 23:33:42 +1000
Links: << >> << T >> << A >>

Thanks Gary, Bob, Laurent, Parag, sk, & John for your comments. That is much 
appreciated.

Gary, thanks. Wow, it's cool that you have bit-banged JTAG and have 
obviously tackled interconnect testing before.

Thanks Bob for the Corelis recommendation. A friend of mine here in Sydney 
uses Corelis. Definitely the higher-end and powerful stuff. I couldn't find 
any prices on their site but I belive it's expensive, as Parag also 
mentioned.

Thanks Laurent, UniversalScan looks good. I didn't know that J-Scan was a 
licensed version of UniversalScan, but now that I look at their websites 
again I can see it. The possibility of storing SVF output format with that 
tool looks nice. I note from their website that the price of UniversalScan 
is US$845.

Also, Laurent, by the way I really like the look of JTAGkey. Very nice 
product. I will have to get myself one of those:)...but just at the moment I 
am pretty happy with my parallel port Xilinx, Altera & Lattice cables. I 
also like that JTAGkey works with Scanseer (I am a fan of Scanseer:) ) & and 
other JTAG software.

sk, that's interesting about Scanseer being faster than UniversalScan, in 
terms of samples per second. Definitely I love the waveform viewer in 
Scanseer. I also like that you can slow down the sample rate with Scanseer 
if you want to. I do that when I just need to look at DC levels (it still 
gives me some indication that the clock and other signals are toggling). A 
few samples per second is good enough for that, but the higher sample rate 
is essential for other tests.

Scanseer's price is Euro$150, which is less than US$220. Great value.

Thanks John for the onTAP Flynn Systems pointer. That does look good. I note 
from their website the price starts at about $2,895.

Just to expand the list a little, I have also looked at the websites for:
xjtag
acculogic
intellitech
jtag technologies

Guys, I am writing an ebook & videos on low-cost JTAG interconnect testing. 
This is a resource for those that want to do simple interconnect testing on 
a prototype board (with BGAs etc.), but can't justify spending much on tools 
or time.

For example, for a small company, freelance designer, or hobbyist that does 
not do alot of development and has a limited budget. I guess there aren't 
alot of hobbyists buying Corelis:)

I have some valuable tips, tricks and techniques that I have found and 
developed that I would like to offer. If there's anything that you would 
like to see in an ebook like this, please drop me a line. I would really 
apprecate it.

I will release the ebook & videos soon at http://www.TestBGAsoldering.com

Thanks & cheers,

Tony Burch

"Tony Burch" <tony@burched.com.au> wrote in message 
news:47097d29$0$18984$afc38c87@news.optusnet.com.au...
> Hi,
> I am looking at various alternatives for interconnect testing, especially 
> for prototype boards that have BGAs. I am very interested to know what 
> other people are using for JTAG interconnect testing, and what your 
> debugging experiences are?
>
> I have Scanseer, and I like it very much. I can do some interconnect 
> testing and real-time monitoring with Scanseer. Another one out there is 
> JSCAN from Macraigor Systems. I have not used JSCAN. The test script 
> recorder stores in SVF looks like it could be good.
>
> Does anyone do prototype interconnect testing with:
> * Amontec JTAGkey?
> * the Lattice tools - ispVM?
>
> Any other suggestions or experiences with interconnect testing (besides 
> X-ray:) )?
>
> Thanks & cheers,
> Tony Burch

Article: 124971
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 13 Oct 2007 08:15:24 -0700
Links: << >> << T >> << A >>

Sebastien Bourdeauducq wrote:
> No, it seems you still have to pay $2000 more if you want to use Linux
> and stay legal.

That includes oem modelsim and the rtl and state viewers.
I'd call that a bargain.

         -- Mike Treseler

Article: 124972
Subject: MIG for Linux?
From: Duane Clark <junkmail@junkmail.com>
Date: Sat, 13 Oct 2007 11:39:26 -0700
Links: << >> << T >> << A >>

So I thought I would try out this MIG thing I see mentioned 
occasionally, But according to
http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=25406

Software Requirements

- ISE 9.2.01i
- Windows XP (32 bit)

So is MIG really windows only?

I currently have ISE 8.2. That same page says:
- MIG is no longer provided as a separate download, but is now 
incorporated into IP Updates. MIG v1.73 is available through 9.2i IP 
Update 1.

So does anyone know if older versions of MIG are available somewhere (I 
have not been able to find them)? Does it run under Wine maybe? Is it 
worth bothering with (I am specifically interested in a plain DDR 
interface)?

Article: 124973
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Sat, 13 Oct 2007 23:31:58 -0000
Links: << >> << T >> << A >>

On Oct 13, 1:30 am, Sebastien Bourdeauducq
<sebastien.bourdeaud...@gmail.com> wrote:
> No, it seems you still have to pay $2000 more if you want to use Linux
> and stay legal.
> Altera sucks.

Sebastien, can I have your car? No? Well, you suck!

Seriously, a more constructive discussion here might be what the state
of running Quartus II under Wine is. I gather that some have
succeeded. I regularly run Quartus II in a WinXP VM on my Mac (using
VMware Fusion). I tried to install Quartus II 7.1sp1 Web Ed. with
CrossOver 6.1 in a Win2K bottle, but alas the installation hung.

Personally I'd care more about having a version that worked under Wine/
CrossOver than a native Linux port.

My $0.0145,
Tommy

Article: 124974
Subject: Re: Graphical VHDL Viewer ?
From: Alex <enginven@gmail.com>
Date: Sat, 13 Oct 2007 17:55:59 -0700
Links: << >> << T >> << A >>

On Oct 12, 1:32 am, "St=E9phane Julhes" <sjul...@adeneo.adetelgroup.com>
wrote:
> Hi all,
>
> Does anyone know a free/simple software that would use vhdl files to prod=
uce
> a graphical view ?
> The goal is to have a easier and faster read of the architecture of a vhdl
> file and its components.
>
> Thanks.
>
> St=E9phane.

I'd like to mention Lattice HDL Explorer. As far as I understand it's
exactly the thing you're looking for. It's not exactly free, it's part
of Lattice tool ispLever. The tools aren't too expensive and also
you'll be able to get a 60 days free evaluation if you'd like, just
contact Lattice local person for this.

Hope this helps,
Alex Y.

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