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On Jul 11, 12:10 pm, Nicolas Matringe <nicolas.matri...@fre.fre> wrote: > > Please define DDFS as accurately as possible > > Nicolas Distant Disease-Free Survival <http://www.ncbi.nlm.nih.gov/pubmed/17952592> How one does breast cancer research in VHDL is puzzling to me too.Article: 133726
Nicolas Matringe wrote: > megha a 閏rit : >> hello, i want a simple VHDL code for DDFS. its really very urgent. anyone >> who is having that VHDL code plz plz send me as soon as possible. >> thank you! >> my email address is roji.sweet@gmail.com > > Please define DDFS as accurately as possible > > Nicolas Device Driver File System? Direct Digital Frequency Synthesis? Do Doofuses Find Smileys? RBArticle: 133727
On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > >On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: > >> Hai, > > >> I want to know which is the right way of implementing and usage of > >> fixed point number data types in hardware(industry standard)..I have > >> referred various FIR > >> implementations where they are mostly handling filter coefficients as > >> integer(truncating from fixed or floating point using MATLAB) or > >> binary.Is it difficult to handle and implement real(fraction) numbers > >> i.e.,filter > >> coefficients values directly in the hardware? > > >Google for fixed point VHDL to_ufixed and you'll get the code for the > >standard (or soon to be a standard) VHDL fixed point package. > > >http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27... > >fixed+point+VHDL+to_ufixed > > >Kevin Jennings > > Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. I > have found these packages you mentioned in response to this guy's question, > very good. But I don't exactly understand how to use these packages? > Any other comments welcome. > I am designing a butterworth lowpass filter (atm just 2nd order filter). I > have implemented it in simulink and could generate VHDL code as well but I > am trying to write the code myself. or atleast with a different approach > because that HDL code generated from Simulink just converts the > coefficients values manually and treat it as a signed number (converted > from an integer value of a fractional binary conversion of a floating point > number). > Anyways, If I couldn't explain this Simulink thing very well, then I beg > ur pardon but it'll be handy if u could tell about that ficed point > packages? And I could discuss this SIMULINK thing further if u wish. > Thanks very much, > Kami I'm not sure the other posts have made this clear, the package described here is not a signal processing tool. It is just a fixed point math library. You still have to figure out how to do the signal processing. This library gives you the low level tools to implement fixed point math in the FPGA. RickArticle: 133728
>On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: >> >On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: >> >> Hai, >> >> >> I want to know which is the right way of implementing and usage of >> >> fixed point number data types in hardware(industry standard)..I have >> >> referred various FIR >> >> implementations where they are mostly handling filter coefficients as >> >> integer(truncating from fixed or floating point using MATLAB) or >> >> binary.Is it difficult to handle and implement real(fraction) numbers >> >> i.e.,filter >> >> coefficients values directly in the hardware? >> >> >Google for fixed point VHDL to_ufixed and you'll get the code for the >> >standard (or soon to be a standard) VHDL fixed point package. >> >> >http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27... >> >fixed+point+VHDL+to_ufixed >> >> >Kevin Jennings >> >> Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. I >> have found these packages you mentioned in response to this guy's question, >> very good. But I don't exactly understand how to use these packages? >> Any other comments welcome. >> I am designing a butterworth lowpass filter (atm just 2nd order filter). I >> have implemented it in simulink and could generate VHDL code as well but I >> am trying to write the code myself. or atleast with a different approach >> because that HDL code generated from Simulink just converts the >> coefficients values manually and treat it as a signed number (converted >> from an integer value of a fractional binary conversion of a floating point >> number). >> Anyways, If I couldn't explain this Simulink thing very well, then I beg >> ur pardon but it'll be handy if u could tell about that ficed point >> packages? And I could discuss this SIMULINK thing further if u wish. >> Thanks very much, >> Kami > >I'm not sure the other posts have made this clear, the package >described here is not a signal processing tool. It is just a fixed >point math library. You still have to figure out how to do the signal >processing. This library gives you the low level tools to implement >fixed point math in the FPGA. > >Rick > Hi Rick, Yes that's right. I am trying to implement fixed-point math in VHDL (for FPGA implementation). and this is for filter coefficients. If I am able to implement that DF-II diagram of the IIR butterworth lowpass filter, won't it be signal processing? I guess so. That's what I am trying to do. I mean perform some additions and multiplications on the input data (which ideally should be a sinusoidal wave or sth but anyhow,) and the filter coefficients which i can take as the constants coz I already know their values. so, that's what it basically is. Any comments/suggestions welcome. Much Appreciated, KamiArticle: 133729
On Jul 11, 1:40=A0pm, "megha" <roji.sw...@gmail.com> wrote: > hello, i want a simple VHDL code for DDFS. its really very urgent. anyone > who is having that VHDL code plz plz send me as soon as possible. > thank you! > my email address is roji.sw...@gmail.com Can someone do my homework too, please? I swear it is really really reaaaally important. It is a traffic light and I need the code ASAP. Thanks!Article: 133730
On Jul 11, 9:02 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > >On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > >> >On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: > >> >> Hai, > > >> >> I want to know which is the right way of implementing and usage of > >> >> fixed point number data types in hardware(industry standard)..I > have > >> >> referred various FIR > >> >> implementations where they are mostly handling filter coefficients > as > >> >> integer(truncating from fixed or floating point using MATLAB) or > >> >> binary.Is it difficult to handle and implement real(fraction) > numbers > >> >> i.e.,filter > >> >> coefficients values directly in the hardware? > > >> >Google for fixed point VHDL to_ufixed and you'll get the code for the > >> >standard (or soon to be a standard) VHDL fixed point package. > > >http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27... > >> >fixed+point+VHDL+to_ufixed > > >> >Kevin Jennings > > >> Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. > I > >> have found these packages you mentioned in response to this guy's > question, > >> very good. But I don't exactly understand how to use these packages? > >> Any other comments welcome. > >> I am designing a butterworth lowpass filter (atm just 2nd order > filter). I > >> have implemented it in simulink and could generate VHDL code as well > but I > >> am trying to write the code myself. or atleast with a different > approach > >> because that HDL code generated from Simulink just converts the > >> coefficients values manually and treat it as a signed number > (converted > >> from an integer value of a fractional binary conversion of a floating > point > >> number). > >> Anyways, If I couldn't explain this Simulink thing very well, then I > beg > >> ur pardon but it'll be handy if u could tell about that ficed point > >> packages? And I could discuss this SIMULINK thing further if u wish. > >> Thanks very much, > >> Kami > > >I'm not sure the other posts have made this clear, the package > >described here is not a signal processing tool. It is just a fixed > >point math library. You still have to figure out how to do the signal > >processing. This library gives you the low level tools to implement > >fixed point math in the FPGA. > > >Rick > > Hi Rick, > Yes that's right. I am trying to implement fixed-point math in VHDL (for > FPGA implementation). and this is for filter coefficients. If I am able to > implement that DF-II diagram of the IIR butterworth lowpass filter, won't > it be signal processing? I guess so. That's what I am trying to do. I mean > perform some additions and multiplications on the input data (which ideally > should be a sinusoidal wave or sth but anyhow,) and the filter coefficients > which i can take as the constants coz I already know their values. so, > that's what it basically is. > Any comments/suggestions welcome. > Much Appreciated, So the question is, do you understand the signal processing? If you understand that, then you need to analyze the algorithm in fixed point arithmetic before you try to implement it in hardware. I prefer to use fractions for all of my numbers, both the input data and the coefficients. Then the multiply won't overflow. Of course it can underflow, but that is not as hard to handle. So start by working in floating point arithmetic using numbers between 1 and -1. Then scale this to fixed point values. Once you have the simulation running you can try implementing it in hardware. RickArticle: 133731
I've gotten the following code for the baudrate generator from
opencores
I've created a Test Bench Waveform for it from my ISE.
Using single clock, Rising edge, Clock High/Low time as 3, Input setup/
Output Valid delay/ Offset as 0
when i run it in modelsim, I dont get any errors, neither do I get any
waves from baud_x_en or baud_en.
======================
-----------------------------------------------------------------------------
-- Filename: am_baud_rate_gen.vhd
--
-- Description:
-- a paramatizable baud rate generator
--
-- input a 'high speed' clock, and get out a clock enable of x times
the baud rate, and the baud rate.
-- paramiters are the high speed clock frequency, the baud rate
required, and the over sample needed.
--
-- works by having two counters,
-- fast counter, counts down to x time baud rate
-- slow counter, then divides this to give baud rate.
--
--
-- Copyright (c) 2007 by Andrew Mulcock
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 26/Nov/07 A Mulcock Initial revision
--
-----------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity am_baud_rate_gen is
generic(
baudrate : integer := 115200;
clock_freq_mhz : real := 200.0;
over_sample : integer := 4
);
port(
clk : in std_logic;
rst : in std_logic;
baud_x_en : out std_logic;
baud_en : out std_logic
);
end entity;
--
==========================================================================================
architecture baud_rtl of am_baud_rate_gen is
-- calculate from the clock freq, the baud rate, and the over sample
ratio
-- the size and count of the two counters.
constant div_ratio_real : real := ( clock_freq_mhz * 1000000.0) /
((real(baudrate) * real(over_sample)) );
constant div_ratio_int : integer := integer ( div_ratio_real - 0.5);
-- 0.5 gives rounding up / down
constant over_sample_ratio : integer := over_sample -1;
constant max_count : integer := div_ratio_int;
signal fast_counter : integer range 0 to div_ratio_int;
signal slow_counter : integer range 0 to over_sample_ratio;
signal slow_cnt_en : std_logic;
begin
------------------------------------------------------------
------------ baud rate counter -----------------------------
------------------------------------------------------------
-- in an fpga, don't need to reset a wrap around counter,
-- but somepeople still like to for simulation
-- so comparmise and reset syncronously, as suits the syncronous
counter.
process(clk)
begin
if rising_edge(clk) then
if ( (rst = '1') or (fast_counter = 0) )
then
fast_counter <= max_count;
slow_cnt_en <= not( rst );
else
fast_counter <= fast_counter - 1;
slow_cnt_en <= '0';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') or ( slow_counter = 0 and slow_cnt_en = '1' )
then
slow_counter <= over_sample_ratio;
baud_en <= not( rst);
elsif slow_cnt_en = '1' then
slow_counter <= slow_counter - 1;
baud_en <= '0';
else
slow_counter <= slow_counter;
baud_en <= '0';
end if;
end if;
end process;
baud_x_en <= slow_cnt_en;
end baud_rtl;
Article: 133732"Zhane" <me75@hotmail.com> wrote in message news:4fea5c5c-f3d4-43e6-9a2a-2759c4b3c9e1@59g2000hsb.googlegroups.com... > I've gotten the following code for the baudrate generator from > opencores Holy crap! - you mean places actually exist for downloading such trivial code? You cannot be THAT interested in FPGA design if you have to download such stuff as this - I summize that this is not your real vocation as you cannot have enough interest to work out such trivia - get a job elsewhere! > I've created a Test Bench Waveform for it from my ISE. Well wooppee doooo > > Using single clock, Rising edge, Clock High/Low time as 3, Input setup/ > Output Valid delay/ Offset as 0 > > when i run it in modelsim, I dont get any errors, neither do I get any > waves from baud_x_en or baud_en. LOL - I would have thought no output was a fundamental major error? > > ====================== > ----------------------------------------------------------------------------- snipped - loadsa copied crapArticle: 133733
On Sat, 12 Jul 2008 02:18:02 -0700 (PDT), Zhane <me75@hotmail.com>
wrote:
>I've gotten the following code for the baudrate generator from
>opencores
>
>I've created a Test Bench Waveform for it from my ISE.
>
>Using single clock, Rising edge, Clock High/Low time as 3, Input setup/
>Output Valid delay/ Offset as 0
>
>when i run it in modelsim, I dont get any errors, neither do I get any
>waves from baud_x_en or baud_en.
Use this trick, or something like it, so that you can simulate in a
reasonably short time but still have the correct baud rate in synthesis.
function calc_divide_ratio is
variable div_r : real := ( clock_freq_mhz * 1000000.0) /
((real(baudrate) * real(over_sample)) );
begin
-- pragma translate off;
div_r := 16.0; -- or some other fast baud rate for sim
-- pragma translate on;
return div_r;
end function calc_divide_ratio;
constant div_ratio_real : real := calc_divide_ratio;
The function detects whether you are in simulation or synthesis, and
initialises the constant to a different value in each case.
Now in simulation you only need to wait 16 clocks per bit.
- Brian
Article: 133734I think you should have this idea on mind when you make your design. you just use the multi cycle or false path constraint to let this path not so important that the design can avoid the timing violations.Article: 133735
On 6=D4=C218=C8=D5, =CF=C2=CE=E78=CA=B109=B7=D6, faza <fazulu.v...@gmail.co= m> wrote: > Hai, > > I want to know which is the right way of implementing and usage of > fixed point number data types in hardware(industry standard)..I have > referred various FIR > implementations where they are mostly handling filter coefficients as > integer(truncating from fixed or floating point using MATLAB) or > binary.Is it difficult to handle and implement real(fraction) numbers > i.e.,filter > coefficients values directly in the hardware? > > for example: > > sample Filter coefficients generated by FDA tool: > > fixed point=3D0.211944580078125 or > 16-bit signed integer=3D 13890 or > fixed point binary =3D0011011001000010 > > all the above are equivalent but belongs to different data type..Now > i > am confused which to select for implementation in my code.. > > Note: > > Fixed point representation is looking challenging for some synthesis > tool as it not supported. > Signed integer looks simple but less accurate > Fixed point binary looks tedious.. > > Pls suggest if anyone knew how to convert fixed point to integer or > binary ?using which tool?I suspect MATLAB fixed point tool will be > useful but i dont know the procedure.. > > regards, > faza You can use matlab simulink+dspbuilder to implement it. should be simple than coding by your self. it can save time and I am also study it now.Article: 133736
Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller tester to test the DDR interface of FPGA(virtex5), after a long time run it appers just fine. but when I reset the FPGA. and run the tester again, I got errors when read back data from DDR. and I want to know does reset FPGA can cause the unstable working of DDR controller? someone can analysis it for me? Thanks and Best Regards. BuleyArticle: 133737
"HT-Lab" <hans64@ht-lab.com> wrote in message news:GEEdk.197564$8k.113349@newsfe18.ams2... > > It is not going to be easy or quick especially for false path. If done manually, it's most likely going to be done incorrectly. KJArticle: 133738
On Jul 12, 7:56 am, "dadabu...@gmail.com" <dadabu...@gmail.com> wrote: > Hi all: > I am meet a very strange ddr controller bugs on board. > since system power up. I turn on the ddr controller tester to test the > DDR interface of FPGA(virtex5), after a long time run it appers just > fine. > but when I reset the FPGA. and run the tester again, I got errors when > read back data from DDR. > and I want to know does reset FPGA can cause the unstable working of > DDR controller? > someone can analysis it for me? > Thanks and Best Regards. > Buley A little more information would help. When you say "reset the FPGA" do you mean re-load the configuration, i.e. pretty much the same as power-on reset? When you say "errors on read back data", did you read data from the first session or data you wrote after resetting the FPGA? Regards, GaborArticle: 133739
On Jul 12, 7:15=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sat, 12 Jul 2008 02:18:02 -0700 (PDT), Zhane <m...@hotmail.com> > wrote: > > >I've gotten the following code for the baudrate generator from > >opencores > > >I've created a Test Bench Waveform for it from my ISE. > > >Using single clock, Rising edge, Clock High/Low time as 3, Input setup/ > >Output Valid delay/ Offset as 0 > > >when i run it in modelsim, I dont get any errors, neither do I get any > >waves from baud_x_en or baud_en. > > Use this trick, or something like it, so that you can simulate in a > reasonably short time but still have the correct baud rate in synthesis. > > function calc_divide_ratio is > variable div_r : real :=3D ( clock_freq_mhz * 1000000.0) / > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ((real(baudrate) * real(o= ver_sample)) ); > begin > -- pragma translate off; > =A0 =A0 =A0 =A0 div_r :=3D 16.0; =A0-- or some other fast baud rate for s= im > -- pragma translate on; > =A0 =A0 =A0 =A0 return div_r; > end function calc_divide_ratio; > > constant =A0 =A0 =A0 =A0div_ratio_real =A0: real =A0 =A0 :=3D calc_divide= _ratio; > > The function detects whether you are in simulation or synthesis, and > initialises the constant to a different value in each case. > > Now in simulation you only need to wait 16 clocks per bit. > > - Brian hmm when I set my baudrate to 9600, clock_freq_mhz to 50 and over_sample to 4, with simulated clock at 20ns clock period, the period for baud_x_en is 26060ns How do I know if the generated baudrate is correct? putting ur function in, I get 354ns period for baud_x_en instead, which is around 17.25 clocks ..which isnt exactly 16. and.. i've no idea what is over_sample for..Article: 133740
On Jul 12, 10:49 am, Zhane <m...@hotmail.com> wrote: > On Jul 12, 7:15 pm, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > > > On Sat, 12 Jul 2008 02:18:02 -0700 (PDT), Zhane <m...@hotmail.com> > > wrote: > > > >I've gotten the following code for the baudrate generator from > > >opencores > > > >I've created a Test Bench Waveform for it from my ISE. > > > >Using single clock, Rising edge, Clock High/Low time as 3, Input setup/ > > >Output Valid delay/ Offset as 0 > > > >when i run it in modelsim, I dont get any errors, neither do I get any > > >waves from baud_x_en or baud_en. > > > Use this trick, or something like it, so that you can simulate in a > > reasonably short time but still have the correct baud rate in synthesis. > > > function calc_divide_ratio is > > variable div_r : real := ( clock_freq_mhz * 1000000.0) / > > ((real(baudrate) * real(over_sample)) ); > > begin > > -- pragma translate off; > > div_r := 16.0; -- or some other fast baud rate for sim > > -- pragma translate on; > > return div_r; > > end function calc_divide_ratio; > > > constant div_ratio_real : real := calc_divide_ratio; > > > The function detects whether you are in simulation or synthesis, and > > initialises the constant to a different value in each case. > > > Now in simulation you only need to wait 16 clocks per bit. > > > - Brian > > hmm > > when I set my baudrate to 9600, clock_freq_mhz to 50 and over_sample > to 4, > with simulated clock at 20ns clock period, > > the period for baud_x_en is 26060ns > How do I know if the generated baudrate is correct? > 1 / 9600 = 104.166... microseconds 4x oversampling means baud_x_en should come 4 times every 104.16 microseconds. So 26.041666... microseconds would be the exact frequency and 26.06 microseconds is very close (for 8-bit asynchronous transmission you only need about 1% clock accuracy). Without looking through the code (not my job :) I'm not sure why the closer value of 26.04 microseconds wasn't used, but as I said 26.06 is close enough (about 700 ppm). > putting ur function in, > I get 354ns period for baud_x_en instead, which is around 17.25 > clocks ..which isnt exactly 16. Strange, A clocked process usually only changes on the clock edge so it would have to be a multiple of 20 nS... Where did you get 354nS? Is this measures from the simulation waveform? > > and.. i've no idea what is over_sample for.. Oversampling is for the UART receiver. This allows the UART to find the center of a bit time. 4x is usually a minimum number for the receiver to work reliably. Modern UARTs usually have 16x oversampling. I would suggest finding a paper on UARTs and getting an understanding of the process involved in receiving asynchronous data. It's really not complex and at some point you may actually enjoy designing your own UART. Regards, GaborArticle: 133741
On Jul 12, 11:28=A0pm, Gabor <ga...@alacron.com> wrote: > On Jul 12, 10:49 am, Zhane <m...@hotmail.com> wrote: > > > > > On Jul 12, 7:15 pm, Brian Drummond <brian_drumm...@btconnect.com> > > wrote: > > > > On Sat, 12 Jul 2008 02:18:02 -0700 (PDT), Zhane <m...@hotmail.com> > > > wrote: > > > > >I've gotten the following code for the baudrate generator from > > > >opencores > > > > >I've created a Test Bench Waveform for it from my ISE. > > > > >Using single clock, Rising edge, Clock High/Low time as 3, Input set= up/ > > > >Output Valid delay/ Offset as 0 > > > > >when i run it in modelsim, I dont get any errors, neither do I get a= ny > > > >waves from baud_x_en or baud_en. > > > > Use this trick, or something like it, so that you can simulate in a > > > reasonably short time but still have the correct baud rate in synthes= is. > > > > function calc_divide_ratio is > > > variable div_r : real :=3D ( clock_freq_mhz * 1000000.0) / > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ((real(baudrate) * re= al(over_sample)) ); > > > begin > > > -- pragma translate off; > > > =A0 =A0 =A0 =A0 div_r :=3D 16.0; =A0-- or some other fast baud rate f= or sim > > > -- pragma translate on; > > > =A0 =A0 =A0 =A0 return div_r; > > > end function calc_divide_ratio; > > > > constant =A0 =A0 =A0 =A0div_ratio_real =A0: real =A0 =A0 :=3D calc_di= vide_ratio; > > > > The function detects whether you are in simulation or synthesis, and > > > initialises the constant to a different value in each case. > > > > Now in simulation you only need to wait 16 clocks per bit. > > > > - Brian > > > hmm > > > when I set my baudrate to 9600, clock_freq_mhz to 50 and over_sample > > to 4, > > with simulated clock at 20ns clock period, > > > the period for baud_x_en is 26060ns > > How do I know if the generated baudrate is correct? > > 1 / 9600 =3D 104.166... microseconds > 4x oversampling means baud_x_en should come 4 times every > 104.16 microseconds. =A0So 26.041666... microseconds would > be the exact frequency and 26.06 microseconds is very > close (for 8-bit asynchronous transmission you only need > about 1% clock accuracy). > > Without looking through the code (not my job :) I'm not > sure why the closer value of 26.04 microseconds wasn't > used, but as I said 26.06 is close enough (about 700 ppm). > > > putting ur function in, > > I get 354ns period for baud_x_en instead, which is around 17.25 > > clocks ..which isnt exactly 16. > > Strange, A clocked process usually only changes on the clock edge > so it would have to be a multiple of 20 nS... =A0Where did you > get 354nS? =A0Is this measures from the simulation waveform? > > ya... from the simulation waveform > > > and.. i've no idea what is over_sample for.. > > Oversampling is for the UART receiver. =A0This allows the > UART to find the center of a bit time. =A04x is usually > a minimum number for the receiver to work reliably. > Modern UARTs usually have 16x oversampling. =A0I would > suggest finding a paper on UARTs and getting an > understanding of the process involved in receiving > asynchronous data. =A0It's really not complex and at > some point you may actually enjoy designing your > own UART. > > Regards, > Gabor hmm.. actually i only want to transmit...so 4x should be more than sufficient right?Article: 133742
"Zhane" <me75@hotmail.com> wrote in message news:78158230-6b76-447c-b0d6-6ab57c7b207f@w7g2000hsa.googlegroups.com... On Jul 12, 11:28 pm, Gabor <ga...@alacron.com> wrote: > > UART to find the center of a bit time. 4x is usually > a minimum number for the receiver to work reliably. > Modern UARTs usually have 16x oversampling. I would > suggest finding a paper on UARTs and getting an > understanding of the process involved in receiving > asynchronous data. It's really not complex and at > some point you may actually enjoy designing your > own UART. > > Regards, > Gabor hmm.. actually i only want to transmit... > Oversampling is for the UART receiver so 4x should be more than sufficient right? 1x is sufficient for transmit KJArticle: 133743
>On Jul 11, 9:02 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: >> >On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: >> >> >On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: >> >> >> Hai, >> >> >> >> I want to know which is the right way of implementing and usage of >> >> >> fixed point number data types in hardware(industry standard)..I >> have >> >> >> referred various FIR >> >> >> implementations where they are mostly handling filter coefficients >> as >> >> >> integer(truncating from fixed or floating point using MATLAB) or >> >> >> binary.Is it difficult to handle and implement real(fraction) >> numbers >> >> >> i.e.,filter >> >> >> coefficients values directly in the hardware? >> >> >> >Google for fixed point VHDL to_ufixed and you'll get the code for the >> >> >standard (or soon to be a standard) VHDL fixed point package. >> >> >http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27... >> >> >fixed+point+VHDL+to_ufixed >> >> >> >Kevin Jennings >> >> >> Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. >> I >> >> have found these packages you mentioned in response to this guy's >> question, >> >> very good. But I don't exactly understand how to use these packages? >> >> Any other comments welcome. >> >> I am designing a butterworth lowpass filter (atm just 2nd order >> filter). I >> >> have implemented it in simulink and could generate VHDL code as well >> but I >> >> am trying to write the code myself. or atleast with a different >> approach >> >> because that HDL code generated from Simulink just converts the >> >> coefficients values manually and treat it as a signed number >> (converted >> >> from an integer value of a fractional binary conversion of a floating >> point >> >> number). >> >> Anyways, If I couldn't explain this Simulink thing very well, then I >> beg >> >> ur pardon but it'll be handy if u could tell about that ficed point >> >> packages? And I could discuss this SIMULINK thing further if u wish. >> >> Thanks very much, >> >> Kami >> >> >I'm not sure the other posts have made this clear, the package >> >described here is not a signal processing tool. It is just a fixed >> >point math library. You still have to figure out how to do the signal >> >processing. This library gives you the low level tools to implement >> >fixed point math in the FPGA. >> >> >Rick >> >> Hi Rick, >> Yes that's right. I am trying to implement fixed-point math in VHDL (for >> FPGA implementation). and this is for filter coefficients. If I am able to >> implement that DF-II diagram of the IIR butterworth lowpass filter, won't >> it be signal processing? I guess so. That's what I am trying to do. I mean >> perform some additions and multiplications on the input data (which ideally >> should be a sinusoidal wave or sth but anyhow,) and the filter coefficients >> which i can take as the constants coz I already know their values. so, >> that's what it basically is. >> Any comments/suggestions welcome. >> Much Appreciated, > >So the question is, do you understand the signal processing? If you >understand that, then you need to analyze the algorithm in fixed point >arithmetic before you try to implement it in hardware. I prefer to >use fractions for all of my numbers, both the input data and the >coefficients. Then the multiply won't overflow. Of course it can >underflow, but that is not as hard to handle. > >So start by working in floating point arithmetic using numbers between >1 and -1. Then scale this to fixed point values. Once you have the >simulation running you can try implementing it in hardware. > >Rick > Well, Yes I do understand the signal processing (am not an expert thought) but I've already implemented the design in SIMULINK. it's a butterworth lowpass filter which can be used in a digital touch tone receiver. with the specs: Fc=852Hz, F2(stop-band freq = 2000Hz) Fs=8000Hz and SB Attenuation>=15dB. I have already implemented it in SIMULINK using FDA tool and generated HDL code as well. I have also implemented the DF-II block diagram in simulink after manually calculating the coefficients values and the difference equation. So, now I am trying to implement this block diagram for the filter in VHDL and I already know the values of coefficients and input can be anything. Now, I need to implement this using fixed-point arithematic. That's what I am trying to implement. Ofcourse I am looking for simulation at the moment but once I get the simulation right, I can implement it on FPGA. In short, if you meant, I need to do MATLAB implementation first, then as I've said earlier, I've done that. Thanks, KamiArticle: 133744
On 7=D4=C212=C8=D5, =CF=C2=CE=E710=CA=B113=B7=D6, Gabor <ga...@alacron.com>= wrote: > On Jul 12, 7:56 am, "dadabu...@gmail.com" <dadabu...@gmail.com> wrote: > > > Hi all: > > I am meet a very strange ddr controller bugs on board. > > since system power up. I turn on the ddr controller tester to test the > > DDR interface of FPGA(virtex5), after a long time run it appers just > > fine. > > but when I reset the FPGA. and run the tester again, I got errors when > > read back data from DDR. > > and I want to know does reset FPGA can cause the unstable working of > > DDR controller? > > someone can analysis it for me? > > Thanks and Best Regards. > > Buley > > A little more information would help. When you say "reset the FPGA" > do you mean re-load the configuration, i.e. pretty much the same > as power-on reset? > > When you say "errors on read back data", did you read data from > the first session or data you wrote after resetting the FPGA? > > Regards, > Gabor sorry for the confusion. I will clearify it. the reset is a global reset for the FPGA logic. just the reset pin connect to all the logic blocks. not reload configuration. and the error is bit error. after the reset, I wrote to the address 0x70A data 0x4E2F693C but the read back data from 0x70A is 0x4E2E691A, some bit errors. and almost every read back data has bit error. and in the different position. I think maybe caused by the DQS sampleing or the DDR initial process problem. is this problems seems like DDR SDRAM problem or The DDR Controller problem? Thanks.Article: 133745
<dadabuley@gmail.com> wrote in message news:3a37a0c3-7557-4774-8d80-6f5ca750775f@2g2000hsn.googlegroups.com... On 7月12日, 下午10时13分, Gabor <ga...@alacron.com> wrote: > I think maybe caused by the DQS sampleing or the DDR initial process > problem. > is this problems seems like DDR SDRAM problem or The DDR Controller > problem? It could be a read problem (like sampling at the wrong time) or a write problem. You need to perform timing analysis. In any case, it's most likely not a problem with the DDR Controller logic itself. Do a thorough timing analysis. KJArticle: 133746
On 7=D4=C212=C8=D5, =C9=CF=CE=E710=CA=B106=B7=D6, checo <chec...@gmail.com>= wrote: > On Jul 11, 1:40 pm, "megha" <roji.sw...@gmail.com> wrote: > > > hello, i want a simple VHDL code for DDFS. its really very urgent. anyo= ne > > who is having that VHDL code plz plz send me as soon as possible. > > thank you! > > my email address is roji.sw...@gmail.com > > Can someone do my homework too, please? > I swear it is really really reaaaally important. It is a traffic light > and I need the code ASAP. > > Thanks! Hey man, you must take the responsibility for yourself. We can answer your questions but we can not do your homework, just like we can not eat your food. And there are many DDFS based on FPGA articles on the web. just google it.Article: 133747
On 7=E6=9C=8813=E6=97=A5, =E4=B8=8A=E5=8D=881=E6=97=B602=E5=88=86, "KJ" <kk= jenni...@sbcglobal.net> wrote: > <dadabu...@gmail.com> wrote in message > > news:3a37a0c3-7557-4774-8d80-6f5ca750775f@2g2000hsn.googlegroups.com... > On 7=C3=94=C3=8212=C3=88=C3=95, =C3=8F=C3=82=C3=8E=C3=A710=C3=8A=C2=B113= =C2=B7=C3=96, Gabor <ga...@alacron.com> wrote: > > > I think maybe caused by the DQS sampleing or the DDR initial process > > problem. > > is this problems seems like DDR SDRAM problem or The DDR Controller > > problem? > > It could be a read problem (like sampling at the wrong time) or a write > problem. =C2=A0You need to perform timing analysis. =C2=A0In any case, it= 's most > likely not a problem with the DDR Controller logic itself. =C2=A0Do a tho= rough > timing analysis. > > KJ Thanks for your advice. I use osilliscope analysis the timing wave on board and find the timing for DATA and DQS are good. and DDR works good when system power up, error just happend after I reset all logic. and I also did timing analysis inside FPGA, there is a good setup/hold time for data and dqs. this is just a strange thing for me.Article: 133748
Hi
When running XST then XST is analysing an entity for ages that contains
the following piece of code.
if (signal1 = '1')
for I in 0 to 15 loop
if (signal2(I) = '0') then
Table0(conv_integer(Table(I)) <= '0';
end if;
end loop;
end if;
Maybe unrolling the loop should solve the problem? Or is there any other
thing that I could change so that the code sythesises?
THanks
Article: 133749>On Jul 11, 2:40=A0pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: >> >> Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. I >> have found these packages you mentioned in response to this guy's questio= >n, >> very good. But I don't exactly understand how to use these packages? >> Any other comments welcome. > >The packages come with a testbench and documentation that explains how >to use them. Read those first, then post more specific questions here >if you have any. > >KJ > Hi KJ, I've visited the site VHDL.org and read the following: http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf and http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html and i think the stuff on Accelera website is also the same apart from some nice powerpoint presentations. I could understand the logic behind these packages and they sounds really very good (especially in my case) I mean positive and negative indices have been used to differentiate the integer and fractional part. That's great. But, I can't understand how to compile and add these packages to my library? Do I need to use Modelsim for this purpose or Xilinx? I mean how to compile it? Do I need to copy the .vhdl files of those packages in the IEEE folder or vhdl source folder where some other libraries are or what? I'll be very thankful if you could give me a direction at least, Thanks, kami
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