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Bert wrote: > On 17 jul, 05:00, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal > Murray) wrote: >>> Anyway, this is not an academic exercise. Porting a very complex >>> Virtex4 design >>> to Stratix is not something that one can do in a few days, so I was >>> looking >>> for ballpark estimates about the equivalence between Xilinx and Altera >>> "gates". >> Have you looked at the Stratix data sheet? Did you find anything >> close to a CLB/FF pair? If so, assume they are 1:1. >> >> Then count the special things you use: BRAMs, clock buffers, multipliers >> and whatevber. Then see if Altera has something similar. >> >> -- >> These are my opinions, not necessarily my employer's. I hate spam. > > Hi, > > I have searched before about the comparison Logic Elements and Logic > Cells. Most of the result say LE = LC, but once (@ Altera website) I > found that LE = 1.125*LC > > Bye > Bert This highly depends on the actual design, there are some minor differences between LEs and LCs that might or might not have an advantage for certain designs. Nevertheless estimating 1:1 is a fairly good choice in my opinion. At least as long as you do not want to go without any reserve of LEs/LCs. Regards, LorenzArticle: 133851
you should check your reset signal. when you simulate it, it must remain asserted for atleast two clock cycles and then deassert. in your simulation code, for exp. if your clock cycle is 100ns #0 rst=1'b1;// (for active high reset) #200 rst=1'b0;Article: 133852
Please tell me any link from i would easily download usb core which will be free of bugs.Article: 133853
Please tell any link from i would easily download full timing diagram of all internal block diagrams of usb core. Please give me if any one have full timing diagram of all internal block diagrams of usb core(UTMI,PL,C/SR,RAM,Memory interface and Arbiter,WB). thanksArticle: 133854
please tell me if any one know or have core of PL (protocol layer) in usb core. please tell me if any one know about PL (protocol layer)functionality and timing diagram in usb core free of bugs. If any one know links which provide core in verilog free of bugs please tell me. thanksArticle: 133855
http://www.usb.org/developers/docs/usb_20_040908.zipArticle: 133856
Please tell me if any one know links or have UTMI interfacing core free of bugs in verilog. Please tell me if any one know functionality or timing diagram of UTMI interfacing in usb core. if any knows link then please tell me thanksArticle: 133857
On Wed, 16 Jul 2008 17:20:10 -0700 (PDT), dudesinmexico <dudesinmexico@gmail.com> wrote: >On Jul 16, 3:15 pm, austin <aus...@xilinx.com> wrote: >> dudes, >> >> If you contact your Xilinx FAE I am sure they would be happy to help you. >> > >So these days Xilinx FAEs help their customers to port their designs >to Altera? >Sorry Austin, I could not resist.. ;) maybe he means "help" as in "set you right about such a silly idea" :-) or, being optimistic, ... maybe he means, provide a discounted price to keep you with Brand X? - BrianArticle: 133858
hmmudassir82@gmail.com wrote: > Please tell me any link from i would easily download usb core which > will be free of bugs. have you already tried asking in comp.do.my.work or comp.do.my.work.for.free ?Article: 133859
Hi! > my clock frequency is 50MHz, the same as yours, I guess ;) Well, almost. I used 49.152 MHz. Probably your mouse wants more init code? You could try another mouse and check. MatthiasArticle: 133860
On 17 Jul, 12:24, hmmudassi...@gmail.com wrote: > Please tell me if any one know links or have UTMI interfacing core > free of bugs in verilog. > Please tell me if any one know =A0functionality or timing diagram of > UTMI interfacing in usb core. if =A0 any knows link then please tell me > thanks http://www.intel.com/technology/usb/spec.htmArticle: 133861
Hello, I implemented a design which uses DCM in Virtex-II Pro XC2VP30-7. I have used ISE 9.2. for design implementation. In the constraint .ucf file, I put the timing constraint for DCM to be 10 ns. Then, I ran the simulation of my placed-and-routed design and I used the generated .VCD file as an input simulation file for XPower. The frequency of DCM clock in the simulation file was set to 50MHz (period of 20 ns). However, in the XPower advanced report I saw that the clock frequency was set to 100MHz, and according to that the dynamic power was almost two times higher than it is in the case when no timing constraint is applied. Hence, the tool ignored the frequency I set in the simulation file. I need the timing constraint to generate the design, but it seems that later on I can not simulate it with any frequency other than the one that was set as a timing constraint. Is there a way I can change this and simulate my design with the frequency I choose? Thanks in advance. RuzicaArticle: 133862
raj wrote: > Hai, > > Unified protocol is MIPI standard. > > In general i would like to know what is the maximum data that can be > exchanged between the devices using this protocol? > > what are the various modes of data exchange? > > > regards, > raj The MIPI standards are available for download to any member, or employee of a member company. My company is a listed member, so I just went and registered. I got a registration response back in less than 5 minutes. Your question is unclear. Do you want to know how much data can be transferred in one packet, or the maximum throughput in units/secs? Note that the second answer depends on what level you are measuring the value (L1 - L4), what bit rate you are running at, and how many lanes (1-4) you have. RBArticle: 133863
hmmudassir82@gmail.com wrote: > please tell me if any one know or have core of PL (protocol layer) in > usb core. please tell me if any one know about PL (protocol > layer)functionality and timing diagram in usb core free of bugs. > If any one know links which provide core in verilog free of bugs > please tell me. > thanks Please see Lorenz Kolb's reply to "free of bugs" RBArticle: 133864
On 17 juil, 10:19, "ALu...@web.de" <ALu...@web.de> wrote: > Hi newsgroup, > > does someone know whether there are design files available > for Xilinx application note "XAPP240 - High-Speed Buffered Crossbar > Switch Design Using Virtex-EM Devices" ? > > I did not found any files on the Xilinx archives. > > Rgds > Andre Hi Google is your friend : http://www.xilinx.com/support/documentation/application_notes/xapp240.pdfArticle: 133865
Hi everey one, i am new to chipscope pro,i worked with verilog example of counter,and instantiated vio,icon and ila core.it works fine.now i want to try with vhdl.i have written a counter program in vhdl and when i tried to instantiate ila,vio,icon core i get lot of errors. can any one provide any tutorials link or help or suggession for writting a counter or any simple program and instatiating vio,ila,icon in vhdl. Any help will be highly appreciated Thanks in advance IrfanArticle: 133866
On Jul 17, 4:58=A0pm, Rob <BertyBoos...@googlemail.com> wrote: > On Jul 16, 3:49 pm, Zhane <m...@hotmail.com> wrote: > > > > > On Jul 16, 11:31 pm, Dave <dhsch...@gmail.com> wrote: > > > > On Jul 16, 10:51 am, Zhane <m...@hotmail.com> wrote: > > > > > On Jul 16, 10:39 pm, Zhane <m...@hotmail.com> wrote: > > > > > > On Jul 16, 8:58 pm, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > > > On Jul 16, 8:52 am, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > > > > On Jul 16, 5:39 am, Zhane <m...@hotmail.com> wrote: > > > > > > > Woops, failed basic mathematics myself on the previous post. = =A0115200 > > > > > > baud will translate to ~11KB/sec which is 3000x slower than the > > > > > > implied input rate of 33 MB/sec...not 3x. =A0Replace all 3x wit= h 3000x > > > > > > in the previous post...get a reeeeeally big memory buffer > > > > > > > KJ > > > > > > :( > > > > > im trying to sample the LPC bus though... I've already reduced to= the > > > > > minimal that I think I need...and with what I have now, there are > > > > > weird extra cycles appearing at places where they shuoldnt be. Wi= thout > > > > > these samples, I cant determine if those weird cycles are relevan= t or > > > > > not. > > > > > > >.< > > > > > > :( how? my Spartan 3E has a USB interface, but... it's used to pr= ogram > > > > > my board. > > > > > > Can I remove my usb cable after downloading my program, and use i= t to > > > > > transfer instead? > > > > > what kind of program (eg.hyperterminal for rs232) is required for= usb? > > > > > hmmm > > > > I guess I can give up on usb.. I cant find a VHDL usb core to use > > > > anyway ~_~ > > > > Maybe you could build a module to look for a condition on the bus tha= t > > > is interesting to you, and store everything just before and after tha= t > > > event? Then you could transmit the stored data out the UART. You just > > > need to figure out how to detect your error on-the-fly. > > > > Dave > > > ya > > im sort of trying to do it now > > but it's either my condition aint met > > > or the bus go crazy =3DP > > > A > > B > > C > > C > > D > > > It's supposed to be A,B,C,D,E, but sometimes it has repeats like ABCCD > > or ABBCDE o_o!! > > If I was you i'd go back to pen and paper and carefully think about > and plan the design. Then probably start again with the coding. Im having a small problem now. I tried to edit my tbw... but every signal that I try to set takes up to 1min for the changes to take place. It's very slow =3D( I've increased my vram and ram...but it doesnt help at all. I'm simulating up to 8000ns...Article: 133867
On Jul 17, 4:59=A0pm, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote: > hmmudassi...@gmail.com wrote: > > Please =A0tell me any link =A0from =A0i would easily download usb core = which > > will be free of bugs. > > have you already tried asking in comp.do.my.work or > comp.do.my.work.for.free ? no I have not tried asking in comp.do.my.work or > comp.do.my.work.for.free.Article: 133868
On Jul 17, 4:59=A0pm, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote: > hmmudassi...@gmail.com wrote: > > Please =A0tell me any link =A0from =A0i would easily download usb core = which > > will be free of bugs. > > have you already tried asking in comp.do.my.work or > comp.do.my.work.for.free ? sir I am trying by writting these "comp.do.my.work.for.free" and "comp.do.my.work" but page is not opening comp.arch.fpga is openingArticle: 133869
If any one use USB 1.1 Function IP Core from opencores site please tell me this core has bugs or not.Article: 133870
If any one use USB 1.1 Function IP Core from opencores site please tell me this core has bugs or not.Article: 133871
Hello, In your ISE directory, you have some tutorials. See xxx\ISE\ISEexamples \Sample_Projects.htm. See also http://www.xilinx.com/company/videos/index.htm: you have several videos concerning Chipscope. Regards.Article: 133872
I bought this board so that I can write the whole software using just VHDL. but only info i can find is... to use Power PC or microblaze core using EDK and then have periphirals using VHDL. I tried to use JTAG to program the PROM to install the basic VHDL software that returns a number on hyper terminal... but it doesn't seem to work... Anybody got any idea... I would really appreciate your help.Article: 133873
> sir > I am trying by writting these "comp.do.my.work.for.free" and > "comp.do.my.work" but page is not opening > comp.arch.fpga is opening LOL! But comp.do.my.work would be a good idea for freelancers and outsourcing...Article: 133874
module
chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum);
input [159:0] len_tcp;
input [31:0] src_addr;
input [31:0] dest_addr;
input [255:0] buff1;
//input [255:0] buff2;
//input [255:0] buff3;
input [15:0] word;
input [31:0] word32;
input [15:0] tcplen;
input [15:0] prot_tcp;
//input padding;
output [31:0] sum;
output led1;
output led2;
//parameter [15:0] padd=0;
//parameter [15:0] prot_tcp=6;
parameter i=0;
//parameter num1 = 16'hff00;
//p//arameter num2 = 8'hff;
//parameter prot_tcp;
//parameter tcplen;
//parameter num1 = 15'hFFFF;
reg led1;
reg led2;
reg [31:0] sum;
//wire [15:0] src_addr;
wire [255:0] buff1;
//wire [255:0] buff2;
//wire [255:0] buff3;
wire [15:0] num1 ;
wire [159:0] len_tcp ;
wire [31:0] src_addr ;
wire [31:0] dst_addr;
wire [15:0] tcplen;
wire [15:0] prot_tcp;
always @(len_tcp,src_addr,dest_addr,buff1,word,word32)
begin
//chk for even odd padding
//if (padding & 1==1)
//begin
//padd=1;
//buff[len_tcp]=0;
//end
//sum=0;
buff1 =
255'hcda9005095209e7d0de26866501010321a6f0000c0a806f3453f602800060014;
num1 = 15'hffff;
len_tcp = buff1[159:0];
src_addr = buff1[191:160];
dst_addr= buff1[223:192];
tcplen= buff1[239:224];
prot_tcp=buff1[255:225];
//claculate sum of all 16 bit words
for( i=0; i<39; i=i+2)
begin
word=((buff1[i]<<8) & 15'hFF00)+(buff1[i+1] & 15'hFF);
word32=word;
//sum = sum + 32'(word);
sum = sum + word32;
end
//add IP source & destination addr & pseudoheader
for(i=0; i<4; i=i+2)
begin
word=((src_addr[i]<<8) & 15'hFF00)+(scr_addr[i+1] &
15'hFF); // error at this line
word32=word;
//sum=sum+(32'(word));
sum=sum + word32;
end
for(i=0; i<4; i=i+2)
begin
word=((dest_addr[i]<<8) & 15'hFF00)+(dest_addr[i+1] & 15'hFF);
sum=sum+word;
end
//protocol number & length
sum= sum + prot_tcp + tcplen;
//keeping last 16 bits of the 32 bit & adding carry
while(sum>>16)
begin
sum=(sum & 15'hFFFF) + (sum>>16);
end
//ones complement
if(sum==num1)
begin
led1=1;
end
else
led2=1;
end
endmodule
Hi all, im getting the following error:
Compiling verilog file "chkchk.v" in library work
ERROR:HDLCompilers:28 - "chkchk.v" line 93 'scr_addr' has not been
declared
Module <chkchk> compiled
Analysis of file <"chkchk.prj"> failed.
-->
Total memory usage is 138176 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize" failed
im unable to understand this error. please help me.
thanks
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