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Yes, Google is my friend, but I already do have the paper. I was asking where to get the design files ! Rgds AndreArticle: 133876
On Thu, 17 Jul 2008 23:57:34 -0700 (PDT), Ambreen Ashfaq Afridi <amboafridi@gmail.com> wrote: >module >chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum); > ... >Compiling verilog file "chkchk.v" in library work >ERROR:HDLCompilers:28 - "chkchk.v" line 93 'scr_addr' has not been >declared The error is referring to a identifier named "scr_addr" but probably it should be "src_addr". In the version of the rtl you have a typo. But interestingly the code you posted doesn't have a scr_addr in it.Article: 133877
On Thu, 17 Jul 2008 23:57:34 -0700 (PDT), Ambreen Ashfaq Afridi <amboafridi@gmail.com> wrote: >module >chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum); >Hi all, im getting the following error: > >Compiling verilog file "chkchk.v" in library work >ERROR:HDLCompilers:28 - "chkchk.v" line 93 'scr_addr' has not been >declared The error is referring to an identifier named "scr_addr" but probably it should be "src_addr". In the version of the rtl you have a typo. But interestingly the code you posted doesn't have a scr_addr in it.Article: 133878
On Jul 18, 1:49=A0am, Wasif Shams <wasifsh...@gmail.com> wrote: > I bought this board so that I can write the whole software using just > VHDL. but only info i can find is... to use Power PC =A0or microblaze > core using EDK and then have periphirals using VHDL. > > I tried to use JTAG to program the PROM to install the basic VHDL > software that returns a number on hyper terminal... but it doesn't > seem to work... > > Anybody got any idea... I would really appreciate your help. You really cannot write the whole software in VHDL. VHDL (VHSIC hardware description language) reference http://en.wikipedia.or= g/wiki/VHDL is often used as a design-entry language for FPGA's. The peripherals you mentioned were probably designed using VHDL. When the VHDL is synthesized and routed, the bitstream is used to configure the FPGA hardware. The bitstream from the VHDL does not run as a program on a processor but configures the FPGA resources into a unique function like a UART. One typically writes the software for the Power PC or Microblaze in a C/C++ type language, not VHDL. Someone might argue that ADA could be used to program the PowerPC and that it is similar in syntax to VHDL but I think that argument just leads to confusion because I think a good ADA programmer would be lost if you asked them to design something using an FPGA and VHDL. Likewise there are C to FPGA compilers. Never had the pleasure to use one. My thoughts are that unless you are or strongly want to be a hardware designer, stay away from VHDL. For others to help you, I think you need to state your background and what you are trying to achieve.Article: 133879
Hi Guys, I am new to Xilinx tools. I am facing some problem while creating the "Base system Builder project" for ML403 Rev B board. The steps as follows: 1. I have downloaded the "ml403_emb_ref_ppc_81.zip" from Xilinx website. 2. I have used the tools EDK10.SP2 and ISE10.1SP4. Problem: When I am creating the base system builder project. I am able to see the UART_LITE, XPS_UARTLITE, ETHERNETLITE, XPS_ETHERNETLITE How can I get the actual devices like OPB_ETHERNET, PLB_ETHERNET..different options like NO DMA, Scattered DMA..etc Please Help me on this. -- Naresh BhatArticle: 133880
Ambreen Ashfaq Afridi wrote: > module > chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum); > input [159:0] len_tcp; > input [31:0] src_addr; You do declare src_addr here >... > word=((src_addr[i]<<8) & 15'hFF00)+(scr_addr[i+1] & here you are trying to use scr_addr not src_addr. Thus > Compiling verilog file "chkchk.v" in library work > ERROR:HDLCompilers:28 - "chkchk.v" line 93 'scr_addr' has not been > declared is a logical result your compiler produces. As compilers are not as clever as humans in guessing what a person really wanted to tell him ;-) Regards, LorenzArticle: 133881
nareshgbhat@gmail.com wrote: > Hi Guys, > > I am new to Xilinx tools. I am facing some problem while creating the > "Base system Builder project" for ML403 Rev B board. > > The steps as follows: > 1. I have downloaded the "ml403_emb_ref_ppc_81.zip" from Xilinx > website. > 2. I have used the tools EDK10.SP2 and ISE10.1SP4. > > Problem: > When I am creating the base system builder project. I am able to see > the UART_LITE, XPS_UARTLITE, ETHERNETLITE, XPS_ETHERNETLITE > > How can I get the actual devices like OPB_ETHERNET, > PLB_ETHERNET..different options like NO DMA, Scattered DMA..etc > Did I get you right? You are now using the Base System Builder Wizzard though You downloaded a complete and concrete design (the ref-design)? > Please Help me on this. > Just uncompress ml403_emb_ref_ppc_81.zip into a folder and open the project as a "recent project". > -- > Naresh Bhat Regards, LorenzArticle: 133882
There is a comparision done by Altera between Stratix III an Virtex-5 http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/performance/st3-opencores.html Maybe I missed it, maybe it is not mentioned, but I cannot find the HDL-compiler used and its settings thus the results might vary and You should not fully rely on a vendor's result (especially if the vendor wins against his competitor in the result). But there You will find a technical description on how to perform such a test-case. This possibly might help. Regards, LorenzArticle: 133883
Hi, I'm currently working in a POSIX thread management and synchronization library upon xilkernel + (powerpc/microblaze). This library really provides to user all thread-related xilkernel services plus conditional variables and thread-specific data). Now, I'm interested in measuring the size of this library in a specific executable application. I have generated the map file but there are a few sections, such us, .stab, .stabstr, .comment, or things as "size before relaxing" that I don't understand. I can't find good documentation in Internet about this matter. 1. Can anyone explain me the purpose of these sections? 2. Where can I find documentation about this issue in Internet? PD. Sorry for my English. Best regards, PacoArticle: 133884
On Jul 18, 5:23=A0am, ppero...@gmail.com wrote: > Hi, > > I'm currently working in a POSIX thread management and synchronization > library upon xilkernel + (powerpc/microblaze). This library really > provides to user all thread-related xilkernel services plus > conditional variables and thread-specific data). Now, I'm interested > in measuring the size of this library in a specific executable > application. > > I have generated the map file but there are a few sections, such > us, .stab, .stabstr, .comment, or things as "size before relaxing" > that I don't understand. I can't find good documentation in Internet > about this matter. > > 1. Can anyone explain me the purpose of these sections? > 2. Where can I find documentation about this issue in Internet? > > PD. Sorry for my English. > > Best regards, > Paco I did a google of stab linker and got a bunch of hits. http://developer.apple.com/documentation/DeveloperTools/gdb/stabs/stabs_13.= htmlArticle: 133885
On 18 Jul, 09:20, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote: > Ambreen Ashfaq Afridi wrote: > > module > > chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led= 1,le=ADd2,sum); > > input [159:0] len_tcp; > > input [31:0] src_addr; > > You do declare src_addr here > > >... > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0word=3D((src_addr[i]<<8) & 15'hFF00)= +(scr_addr[i+1] & > > here you are trying to use scr_addr not src_addr. Thus > > > Compiling verilog file "chkchk.v" in library work > > ERROR:HDLCompilers:28 - "chkchk.v" line 93 'scr_addr' has not been > > declared > > is a logical result your compiler produces. As compilers are not as > clever as humans in guessing what a person really wanted to tell him ;-) You should try one of the Java compilers from IBM. When it sees an undeclared variable, it looks for variables with similar names and then suggests what you should change it to! JonArticle: 133886
On Jul 18, 11:44 am, Newman <newman5...@yahoo.com> wrote: > On Jul 18, 5:23 am, ppero...@gmail.com wrote: > > > > > Hi, > > > I'm currently working in a POSIX thread management and synchronization > > library upon xilkernel + (powerpc/microblaze). This library really > > provides to user all thread-related xilkernel services plus > > conditional variables and thread-specific data). Now, I'm interested > > in measuring the size of this library in a specific executable > > application. > > > I have generated the map file but there are a few sections, such > > us, .stab, .stabstr, .comment, or things as "size before relaxing" > > that I don't understand. I can't find good documentation in Internet > > about this matter. > > > 1. Can anyone explain me the purpose of these sections? > > 2. Where can I find documentation about this issue in Internet? > > > PD. Sorry for my English. > > > Best regards, > > Paco > > I did a google of stab linker and got a bunch of hits. > > http://developer.apple.com/documentation/DeveloperTools/gdb/stabs/sta... Newman, I had already visited that url, but I didn't do a deeply search. Sorry. I have found more info about stabs in the next url: http://developer.apple.com/documentation/DeveloperTools/gdb/stabs/stabs_1.html#SEC1 It seems to be that this section is used for debugging purposes (gdb), but all my applications, my library and xilkernel are compiled without the -g option (and with -O2), so no debug information should appear in the map file. Does anybody have more precise information about this? Best regards, PacoArticle: 133887
Jon Beniston wrote: > > You should try one of the Java compilers from IBM. When it sees an > undeclared variable, it looks for variables with similar names and > then suggests what you should change it to! > > Jon > > I know those "did you mean" messages. Nevertheless they do not automatically repair the code. A human can read any text as lnog as the frsit and the lsat lteetrs are ccrerot and the lttrees in bwteeen are in ttaol dsroiedr. This has been proven ;-) (Sorry for the disordered letters above I couldn't resist, personally I thing dsroiedr is the hardest one). Regards, LorenzArticle: 133888
My problem is explained here... While creating the new XPS project using Base system Builder: Step 1. New Project->Base System builder Project-> Create a new XPS project using Base system Builder->Browse system.xps project from "ml403_emb_ref_ppc_81" directory and overwrite it. Step 2. I am selecting "I would like to create the new design" and then Board Vendor "Xilinx" Board name "ML403" Board version "1" Step 3: I just click "Next" Step 4: I am selecting the Processor Cloclk Frequency as "300Mhz" Step 5: Configuring the IO interfaces Here is my problem. In RS232 UART I am having the only 2 option 1. XPS_UARTLITE 2. XPS_UART16550 If I use the same base system builder (ml403_emb_ref_ppc_81) with other version of the EDK tools (like 8.1iSP2, 9.2iSP2). and repeat the same steps I am able to see the options like 1. OPB_UARTLITE 2. OPB_UART16550 3. PLB_UART16550 Do you have any idea on this Why it is not getting displayed on the EDK10.1iSP2 version? Thanks Naresh BhatArticle: 133889
Hi Lorenz Thanks for the HELP in advance My problem is explained here... While creating the new XPS project using Base system Builder: Step 1. New Project->Base System builder Project-> Create a new XPS project using Base system Builder->Browse system.xps project from "ml403_emb_ref_ppc_81" directory and overwrite it. Step 2. I am selecting "I would like to create the new design" and then Board Vendor "Xilinx" Board name "ML403" Board version "1" Step 3: I just click "Next" Step 4: I am selecting the Processor Cloclk Frequency as "300Mhz" Step 5: Configuring the IO interfaces Here is my problem. In RS232 UART I am having the only 2 option 1. XPS_UARTLITE 2. XPS_UART16550 If I use the same base system builder (ml403_emb_ref_ppc_81) with other version of the EDK tools (like 8.1iSP2, 9.2iSP2). and repeat the same steps I am able to see the options like 1. OPB_UARTLITE 2. OPB_UART16550 3. PLB_UART16550 Do you have any idea on this Why it is not getting displayed on the EDK10.1iSP2 version? I have the complete License to use this tool. I think it might not be license problem right? Thanks Naresh Bhat On Jul 18, 1:24=A0pm, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote: > nareshgb...@gmail.com wrote: > > Hi Guys, > > > I am new to Xilinx tools. I am facing some problem while creating the > > "Base system Builder project" for ML403 Rev B board. > > > The steps as follows: > > 1. I have downloaded the "ml403_emb_ref_ppc_81.zip" from Xilinx > > website. > > 2. I have used the tools EDK10.SP2 and ISE10.1SP4. > > > Problem: > > When I am creating the base system builder project. =A0I am able to see > > the UART_LITE, XPS_UARTLITE, ETHERNETLITE, XPS_ETHERNETLITE > > > How can I get the actual devices like OPB_ETHERNET, > > PLB_ETHERNET..different options like NO DMA, Scattered DMA..etc > > Did I get you right? You are now using the Base System Builder Wizzard > though You downloaded a complete and concrete design (the ref-design)? > > > Please Help me on this. > > Just uncompress ml403_emb_ref_ppc_81.zip into a folder and open the > project as a "recent project". > > > -- > > Naresh Bhat > > Regards, > > LorenzArticle: 133890
So you do want to create a completely new design? Which has components (like opb_ethernet) used in the old design? Ok, best thing to to this is open the old design and adopt it to create a new design. The wizzard for new designs lacks some "old" ipcores as Xilinx' opinion on what's good and what's bad has shifted since. Another solution might be to use an older version (8.1 or 8.2) of the Xilinx tools to create Your design. And then open that design with the newer tools. Regards, LorenzArticle: 133891
Hi Lorenz, I tried to open "project as a recent project". But it is throwing the message saying that this BSB is build using the older version of EDK and it is asking for some check list I said for all just "next". But the xilinx tool through lots of the error messages. Thats it....:( Regards Naresh BhatArticle: 133892
nareshgbhat@gmail.com wrote: > Hi Lorenz, > > I tried to open "project as a recent project". But it is throwing the > message saying that this BSB is build using the older version of EDK > and it is asking for some check list I said for all just "next". But > the xilinx tool through lots of the error messages. Thats it....:( > Ah, maybe the good old bug since EDK7.1 Now with the changes done close the project, close EDK, reopen EDK and reopen the project. ;-) > Regards > Naresh Bhat > Regards, LorenzArticle: 133893
Hi, If I use the same base system builder (ml403_emb_ref_ppc_81) with other version of the EDK tools (like 8.1iSP2, 9.2iSP2). and repeat the same steps I am able to see the options like 1. OPB_UARTLITE 2. OPB_UART16550 3. PLB_UART16550 But in the design it is showing the "$" symbol (Is it means My license is not correct?). I have tried all the Xilinx tools on the Linux platform (FC9). I have never tried it on the Windows platform. Cheers!!! Naresh BhatArticle: 133894
nareshgbhat@gmail.com wrote: > Hi, > > If I use the same base system builder (ml403_emb_ref_ppc_81) with > other version of the EDK tools (like 8.1iSP2, 9.2iSP2). and repeat the > same steps I am able to see the options like > > 1. OPB_UARTLITE > 2. OPB_UART16550 > 3. PLB_UART16550 > > But in the design it is showing the "$" symbol (Is it means My license > is not correct?). I have tried all the Xilinx tools on the Linux > platform (FC9). I have never tried it on the Windows platform. > Though Xilinx might kill me for this: how about taking a trip back in time (the date command (man date) might help you ...). Nevertheless You should also try my proposed answer in the other subthread. > Cheers!!! > Naresh Bhat > Regards, LorenzArticle: 133895
Hai, I want to know how different is unified protocol compared with OSI and TCP/IP? regards, rajArticle: 133896
On Jul 18, 3:16 am, "ALu...@web.de" <ALu...@web.de> wrote: > Yes, Google is my friend, but I already do have the paper. I was > asking where > to get the design files ! > > Rgds > Andre I took a look at the paper and didn't see any mention of design files... This sounds like a "look what you can do" rather than "look what we have done" type of paper.Article: 133897
raj wrote: > Hai, > > I want to know how different is unified protocol compared with OSI and > TCP/IP? > > regards, > raj I'd say that you need to get attached to a member company and get the documents. There is a good comparison between the L1-L4 stack and the OSI stack in the reference. I'm not sure it can be compared to TCP/IP since one is truly point-to-point, in a small device such as a camera or phone, and the other is for multipoint, usually much larger, networks. RBArticle: 133898
Hi every body, I am new to fpga design and I d like to know if there is anyone who knows where I can find free video course on fpga or asic. thanks in advance for your reply,\ dabaf, From me@home.org Fri Jul 18 10:21:52 2008 Path: unlimited.newshosting.com!dartmaster!s03-b21.iad01!nx02.iad01.newshosting.com!newshosting.com!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.freenet.de!news.germany.com!newsfeed.datemas.de!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4880d12d$0$25951$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <me@home.org> Subject: Re: ps2 mouse initialization fails Newsgroups: comp.arch.fpga Date: Fri, 18 Jul 2008 19:21:52 +0200 References: <4877c1ba$0$25950$6e1ede2f@read.cnntp.org> <g5et1b$jqs$1@news.uni-kl.de> <487d0408$0$25949$6e1ede2f@read.cnntp.org> <g5nce4$5gl$1@news.uni-kl.de> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 20 Organization: CNNTP NNTP-Posting-Host: e590cfd6.read.cnntp.org X-Trace: DXC=;K?[ehAdC`?aRKjieWKRK=WoT\PAgXa?13QObBb3c?J=CWCf629N194iB41cD4W0^?j;L0M]EiS`;IgDGd]8^D29 X-Complaints-To: abuse@cnntp.org Xref: unlimited.newshosting.com comp.arch.fpga:109465 Matthias Alles wrote: > Hi! > >> my clock frequency is 50MHz, the same as yours, I guess ;) > > Well, almost. I used 49.152 MHz. Probably your mouse wants more init > code? You could try another mouse and check. > > Matthias Hi, I bought a new mouse, and now it works fine ;) I got the info, that the voltage level of the FPGA output pin is 3.3V and the PS2 standard wants 5V. Maybe that is the problem ?!? Thanks for your help. Best Regards ThorstenArticle: 133899
Which affordable FPGA has the most dual port block-ram type resources in a TQFP144 or smaller quad flat pack (non-BGA) package, that's actually stocked by distributors? I/O requirements and internal logic are fairly limited, but I need a lot of buffer memory and to fit the device on a very narrow PCB without the assembly issues of a BGA package. So far spartan XC3S200 or XC3S250E with 12 x 16K-bit block rams seems the largest memory in a device that fully meets this constraint. I'd really like the 16 block rams of the 400 or 500 gate parts or more, but squeezing in the PQFP-208 they come in is going to be dicey, and I'd like to avoid going to a BGA package. Altera does not seem to offer the mid-size cyclones in quad flat packs, or at least they aren't stocked. Any other makers with interesting parts?
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