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On Mon, 09 Jun 2008 21:30:17 +0200, David Brown <david.brown@hesbynett.removethisbit.no> wrote: >This is a common misconception about volatile in C. The compiler cannot >change volatile accesses with respect to other volatile accesses - but >it can happily re-order non-volatile accesses around the volatile >access. Thus it is perfectly allowed to do "...do stuff..." either >before or after the two volatile reads of the timer. Even if you write >something like : > >int timer_value = * (volatile int *) TIMED_REG_ADDRESS; >volatile int result = doSomething(); >timer_value = (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; > >The compiler can call doSomething(), storing the result in a temporary >register, then read TIMED_REG_ADDRESS, store the result in "result", >then re-read TIMED_REG_ADDRESS - all without violating the volatile >requirements. Pardon me for jumping in, but doesn't the above violate the constraints on all side-effects of previous expressions, and none of subsequent expressions, being evaluated at each sequence point? -- Rich Webb Norfolk, VAArticle: 132876
Andy Botterill wrote:
> WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
> unconnected signal will be trimmed during the optimization process.
>
> What I would like to do is to find out which lines are caing this
> warning and see if I have missed something or the synthesis tool has
> made a mistake.
It is most likely a logical error in the code.
> All sixteen op-codes assign something to borrow. Sometimes true,
> sometimes inverse and sometimes 0.
OK, but what xst is claiming is that
no register is being assigned *to* by
the "borrow" register.
In other words, "borrow" does not appear
on the right side of any active assignment
that affects a top port output..
-- Mike Treseler
Article: 132877FP wrote: > Can a DDR SDRAM controller be used to drive SDR SDRAM? No, unless it is a combined DDR/SDR controller, and those aren't common. > What other options do I have? An SDR DRAM controller.Article: 132878
Mike Treseler wrote:
> Andy Botterill wrote:
>
>
>>WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
>>unconnected signal will be trimmed during the optimization process.
>>
>>What I would like to do is to find out which lines are caing this
>>warning and see if I have missed something or the synthesis tool has
>>made a mistake.
>
>
> It is most likely a logical error in the code.
I agree with that I'm trying to figure out how to track it down.
>
>
>>All sixteen op-codes assign something to borrow. Sometimes true,
>>sometimes inverse and sometimes 0.
>
>
> OK, but what xst is claiming is that
> no register is being assigned *to* by
> the "borrow" register.
(* KEEP = "TRUE" *){borrow, Rd_contents}=Rn_contents - shifter_operand;
There are at least three occurences similar to above.
Some are assigned to zero which may give the synthesis tool the idea
that it could be optimised.
>
> In other words, "borrow" does not appear
> on the right side of any active assignment
> that affects a top port output..
borrow does not go to a top level port but it is used in the carry logic
which goes to a primary output.
>
> -- Mike Treseler
Article: 132879
Andy Botterill wrote:
> (* KEEP = "TRUE" *){borrow, Rd_contents}=Rn_contents - shifter_operand;
^ that's on the left side.
Borrow is being updated, not used, in that assignment.
> There are at least three occurrences similar to above.
It doesn't matter how many there are.
> Some are assigned to zero which may give the synthesis tool the idea
> that it could be optimised.
Unless there is an assignment like
my_top_port <= some_function_of_borrow;
Then synthesis is correct in removing the register.
I would run a sim to see what is really going on.
-- Mike Treseler
Article: 132880Andy Botterill wrote: > Using verilog and ISE 10.1. > > I add a reg to modify the design's behaviour. It works and it works > correctly. The change is intended to invert the carry logic for some > op-codes. > > However synthesis , using XST , gives the following warning message. > > WARNING:Xst:646 - Signal <borrow> is assigned but never used. This > unconnected signal will be trimmed during the optimization process. > Hi Andy, Do you have a signal such as 'carry' which is the exact inverse of 'borrow'? I.e. borrow = not carry? If you do, the synthesis tool might optimise 'borrow' away and use carry throughout. HTH., Syms.Article: 132881
On Jun 9, 3:30 pm, David Brown <david.br...@hesbynett.removethisbit.no> wrote: > PFC wrote: > > >> In short, I am trying to keep tab of how fast various sections of code > >> takes to run using a timer running on Microblaze. > > > I've done that before, like this : > > > int timer_value = * (volatile int *) TIMED_REG_ADDRESS; > > > .. do stuff.. > > > timer_value = (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; > > > printf( "Elapsed cycles : %d", timer_value ) > > >> volatile Xuint32 countvalue; > > > It is the timer register which is incremented unbeknowst to gcc, not > > your int variable. > > Therefore it is the pointer to the timer register you read which > > must be declared (volatile int *), not the int variable (this is useless). > > > I put the explicit code in the example above. You can use defines or > > functions to make it prettier. > > > Note also that this handles wraparound : > > > instant 1 : you get 0xFFFFFFFF from timer > > instant 2 : you get 0x00000001 from timer (it wrapped) > > > (int)0xFFFFFFFF = -1 > > (int)0x00000001 = 1 > > > Difference : 1 - (-1) = 2 cycles. > > int arithmetic handles the wraparound nicely for you. > > > Note that if you set the timer to wraparound at some random value it > > won't work. > > > "volatile int x" is a contradiction so gcc optimized away which is > > the expected behaviour. > > However *(volatile *)address has a very specific meaning which is > > what you want. Accesses to volatiles create barriers that gcc > > instruction reordering cannot skip so it will do what you want. > > This is a common misconception about volatile in C. The compiler cannot > change volatile accesses with respect to other volatile accesses - but > it can happily re-order non-volatile accesses around the volatile > access. Thus it is perfectly allowed to do "...do stuff..." either > before or after the two volatile reads of the timer. Even if you write > something like : > > int timer_value = * (volatile int *) TIMED_REG_ADDRESS; > volatile int result = doSomething(); > timer_value = (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; > > The compiler can call doSomething(), storing the result in a temporary > register, then read TIMED_REG_ADDRESS, store the result in "result", > then re-read TIMED_REG_ADDRESS - all without violating the volatile > requirements. Can you declare doSomething() itself to be volatile?Article: 132882
hi, I am trying to run the aurora example given by xilinx on fpga board which have xc2vp50 I am using refclock which is connected to 125MHz single clock. I am not able to initialize the channel. LANE_UP and CHANNEL_UP signals are always zero and tx_dst_rdy and rx_src_rdy signals are always high. The example is working perfectly for xup board where I am using BREFCLK as clock. thanks in advance for your valuable suggestion. ajithArticle: 132883
rickman wrote: (snip) > But there is also the issue of knowledge. I have *no* experience with > *nix... well, no good experience. Some years ago I bought a $200 > Walmart machine which came with Lindows, a version of Linux. It had a > number of apps which were flaky and I didn't see much utility to it. > I couldn't figure out how to do a lot of things and I ended up > installing Win2000 over it. The company was also pretty poor about > meeting the license requirements. I thought they had to make the > sources available in the same manner that they distributed the > binary. When I first asked them about it they feigned ignorance. > After nagging they shipped me a hand copied CD. When I received an > update there were no sources. This time I was told that they were > available on the web site. Yes, they were there, but as individual > files which had to be downloaded one at a time. That is what wget is good for. > I have just never had a positive experience with linux. I don't know > how much time it would take, but I can't see spending the investment > to convert and I seldom have the time to investigate. There is also > the research I would have to do to figure out *which* version of Linux > I would want. How can Linux be standard if there are so many versions > and each software vendor only supports a few? I like scientific linux, see http://www.scientificlinux.org/Article: 132884
"Gabor" <gabor@alacron.com> wrote in message
news:<e3538f86-b448-4bb4-91da-bf172b836b78@8g2000hse.googlegroups.com>...
> If you want to remove the buffer delay, you need to route the output
> of the BUFG
> back to the CLKFB input of the DCM. You have the CLK0 output routed
> directly
> (internal feedback) which only removes delay to the CLK0 output itself
> before
> the BUFG.
>
> HTH,
> Gabor
Thanks Gabor,
I explicitly added an BUFG between the DCM's CLK0 output to CLK before
feeding it back as well as an explicit IBUFG from the input pad to CLKIN of
the DCM and the delay is nulled out.
It is noteworthy though, that even when there is no BUFG instantiated
explicitly, the tool does add a BUFG in the feedback path as well as an
IBUFG from the input pad to DCM CLKIN. This can be seen in the .twr report
showing details for the CLK path which is shown below:
-------------------------------------------------------
Maximum Clock Path: LCLK_IN to READY_CARRIER
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D14.I Tiopi 0.963 LCLK_IN
LCLK_IN
LCLK_IN_IBUFG
DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.260 LCLK_IN_IBUFG
DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -2.213 DCM_BASE_inst
DCM_BASE_inst
BUFGCTRL_X0Y23.I0 net (fanout=3) 1.504 CLK1
BUFGCTRL_X0Y23.O Tbgcko_O 0.900 CLK_BUFG
CLK_BUFG
SLICE_X52Y103.CLK net (fanout=123) 2.565 CLK
------------------------------------------------- ---------------------------
Total 4.979ns (-0.350ns logic,
5.329ns route)
-------------------------------------------------------
The similar detail for the explicitly instantiated IBUFG and BUGF is shown
below - note
the much larger 'minus' delay introduced by the DCM:
-------------------------------------------------------
Maximum Clock Path: LCLK_IN to ASTATE_FFd2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B17.I Tiopi 0.988 LCLK_IN
LCLK_IN
IBUFG_LCLK_IN
DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.191 LCLK_INf
DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -7.207 DCM_BASE_inst
DCM_BASE_inst
BUFGCTRL_X0Y25.I0 net (fanout=1) 1.504 DCM_CLK0
BUFGCTRL_X0Y25.O Tbgcko_O 0.900 BUFG_CLK
BUFG_CLK
SLICE_X0Y53.CLK net (fanout=174) 2.676 CLK
------------------------------------------------- ---------------------------
Total 0.052ns (-5.319ns logic,
5.371ns route)
-------------------------------------------------------
I don't understand the difference - both reports show similar connections
for the global buffers.
Bill
Article: 132885> int timer_value =3D * (volatile int *) TIMED_REG_ADDRESS; > volatile int result =3D doSomething(); > timer_value =3D (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; > > The compiler can call doSomething(), storing the result in a temporary= = > register, then read TIMED_REG_ADDRESS, store the result in "result", = > then re-read TIMED_REG_ADDRESS - all without violating the volatile = > requirements. Does the compiler know that doSomething() will never access any volatil= e = variable ? (the generated assembly code was correct last time I checked). Anyway you can always put your timer code in functions. I don't think g= cc = reorders function calls ?... >> "volatile int x" is a contradiction so gcc optimized away whi= ch = >> is the >> expected behaviour. > > How is it a contradiction? > > You can still get it's address and modify or examine it that way > behind the compiler's back, so the compiler must assume that when you > say it's volatile, you might mean it. Granted you want to be careful > that you only do this during a time when the compiler is obligated to > ensure that the variable exists, but that's not unreasonable within > the scope, or when playing with a hardware-based debugger. Sounds like a big shiny foot-gun. But you're right... C is so perverse, lol.Article: 132886
On Mon, 9 Jun 2008 12:02:34 -0700 (PDT), cs_posting@hotmail.com wrote
in comp.arch.embedded:
> On Jun 9, 1:43 pm, PFC <li...@peufeu.com> wrote:
>
> > "volatile int x" is a contradiction so gcc optimized away which is the
> > expected behaviour.
>
> How is it a contradiction?
>
> You can still get it's address and modify or examine it that way
> behind the compiler's back, so the compiler must assume that when you
> say it's volatile, you might mean it. Granted you want to be careful
> that you only do this during a time when the compiler is obligated to
> ensure that the variable exists, but that's not unreasonable within
> the scope, or when playing with a hardware-based debugger.
Actually, the compiler can still optimize this away. To simplify:
void some_function(void)
{
volatile int x = func1();
/* do stuff */
x = func2();
return;
}
Since the variable, even though it is declared volatile, has automatic
storage duration and its address is never taken, it cannot possibly be
modified without the compiler's knowledge.
On the other hand, if it was defined at file scope, and therefore had
external linkage, that would be a different story.
--
Jack Klein
Home: http://JK-Technology.Com
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Article: 132887"Mike Treseler" <mtreseler@gmail.com> wrote in message news:484C29A9.6010000@gmail.com... >> But Aldec seems to distribute the same vendor library-update in the form >> of a download, up to a month later. > > 1. Aldec is not an oem for the major brands, however... > 2. Compiling a library is not a big deal and ... Ok, so there are no issues with the user re-compiling the Verilog/VHDL simprim, unisims, xilinxcorelib, from source? That's what I wanted to hear. I was worried that the vendor's libs used weird (non-standard) Verilog modeling, and that it might not work 'out of the box' with non-Modelsim simulators. (My coworker told me this was a BIG problem with the whole Verilog scene in general, back when the original Verilog-XL was king.) > 3. If I am using synthesis, I don't need any libraries for simulation. > Use the source Luke. ?!? If your synthesizeable-RTL only uses generic statements (i.e. infered FPGA-structures) , and not hand-instantiations, I can understand. But what about when you instantiate specific I/O-cells, or a DCM? Don't those have to come from the library? And let's not forget Xilinx's Smartmodels for the TEMAC, Microblaze, among other IP. (I hope the Smartmodel 10.1i installer has finally gotten around to supporting Windows/Vista.)Article: 132888
hi.... how many times cain i download .bit files onto an fpga? i use virtex2pro.... thanks vikramArticle: 132889
thanks a lot ppl..... PFC wrote: > > hello.... i wanted to know if fpgas were reprogrammable... > > Sure, your Virtex stores configuration in RAM. While testing and > debugging, use JTAG to configure it, when it's ready program the > configuration flash on the board.Article: 132890
On Jun 9, 10:32=A0pm, vikram <vikram...@gmail.com> wrote: > hi.... > > how many times cain i download =A0.bit files onto an fpga? i use > virtex2pro.... > > thanks > vikram Billions of times. Since the configuration is stored in latches (commonly called SRAMs) there is no known wear-out mechanism. You might wear out the Flash storage device after tens of thousands of changes, but nevevr the FPGA itself. Peter Alfke, XilinxArticle: 132891
Hi, I have described a state machine running with an external pixel clock. As I could see on the oscilloscope the ScanDetect signal becomes high indicating that the pixel clock is stable. BUT the clock is not stable for some while after Scdt becomes high. The clock seems to tune after some us. (stable clock should have around 100MHz) The clock is changing its frequency, high and low phases are symmetrical. If the FSM is running with that clock and if Scdt='1' is used to start the FSM, can I trust the state changes of the FSM ? Thank you for your opinion. Rgds AndreArticle: 132892
I have to use the Trimode Ethernet MAC core for my FPGA project, which will send and recieve data while connected to LAN though an Ethernet cable. For that obviously some IP address should be assigned to the FPGA, I couldn't find the part of code where this is happening ... Can anyone help me identify that part of code where IP address assignment is taking place? I'm using Xilinx Application Notes, XAPP443. http://www.xilinx.com/support/documentation/application_notes.htm I really need help, immediately.Article: 132893
PFC wrote: > >> int timer_value = * (volatile int *) TIMED_REG_ADDRESS; >> volatile int result = doSomething(); >> timer_value = (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; >> >> The compiler can call doSomething(), storing the result in a temporary >> register, then read TIMED_REG_ADDRESS, store the result in "result", >> then re-read TIMED_REG_ADDRESS - all without violating the volatile >> requirements. > > Does the compiler know that doSomething() will never access any > volatile variable ? > (the generated assembly code was correct last time I checked). > > Anyway you can always put your timer code in functions. I don't > think gcc reorders function calls ?... > >>> "volatile int x" is a contradiction so gcc optimized away >>> which is the >>> expected behaviour. >> >> How is it a contradiction? >> >> You can still get it's address and modify or examine it that way >> behind the compiler's back, so the compiler must assume that when you >> say it's volatile, you might mean it. Granted you want to be careful >> that you only do this during a time when the compiler is obligated to >> ensure that the variable exists, but that's not unreasonable within >> the scope, or when playing with a hardware-based debugger. > > Sounds like a big shiny foot-gun. > But you're right... C is so perverse, lol. > In answer to this and the other replies to my post: You are right that the compiler can only re-order "doSomething()" around volatile accesses if it knows that doSomething() does not make volatile accesses itself. But the compiler can be surprisingly knowledgeable about such things - if the doSomething() function is in the same source file, and you have at least some optimisations enabled, then it probably has this knowledge. In fact, in many common cases when you are writing test code like this, the doSomething() function is not only in the same file, but it is only used the one time, and the compiler may well inline the function. Thus even if it *does* use volatile accesses, non-volatile accesses in doSomething() can be shuffled around about and below the timer accesses. Just to add to the fun, the compiler might also figure out that parts of the code in doSomething() can be calculated at compile time, and eliminated from the object code. You can't make a function itself "volatile", but you can use the "noinline" function attribute to ensure it is not inlined - that's probably enough to make sure it is called properly. As has been said, check the assembly listing to make sure you are measuring the code you want to measure.Article: 132894
John:Matlab is fun to play with but it gives you no sense of what it takes to truly implement a design. Faza:Have a look at the following link in which MATLAB plays a vital to implement a FIR filter in FPGA http://asic-soc.blogspot.com/2008/06/fpga-implementation-of-fir-filter.html John:The cutoff frequency is a function of your FIR. FIR filters with fewer taps have poorer characteristics in things like passband flatness, stopband attenuation, and the steepness of the cutoff than longer filters. ARE YOU FAMILIAR WITH THESE PARAMETERS? faza:yes,cutoff frequency is the design parameter choosen based on the application..and it is the highest frequency at which the filter gain is equal to or above the minimum gain within the filter's pass band... PFC:Get it ? Faza:Yes,now i got..I was confused with the sampling frequency of input signal which decide Fclk and sampling frequency setted to generate the filter coefficients which is independent of Fclk...Thanks for the clarification..And also i learned Fclk is setted based on timing analysis.... PFC:Say your Fsample is 1 MHz you have N =3D 10 taps in your filter for each sample you need 10 multiplications and 10 additions it takes a clock cycle to do a multiply + accumulate Faza:I have coded as per direct form structure..so for N-taps it requires N-multiplication and N-1 addition...And also for fs=3D 1Mhz ,1 million samples will be generated, since N=3D10,it has 10 filter coefficients.. Here number of Input samples> number of filter coefficients samples... as per my code i will get 1 million o/p samples ...Is it correct?? But i know as per convolution i should get 10+1 million-1 samples.. In general i will get number of output samples =3D number of input samples If i have number of input samples < coefficients i have to zero pad the end of input samples to process all the coefficients.. pls clarify on this?? PFC:What is the signal you want to filter ? Faza:An audio signal for audio applications and signals used in multimedia applications are my real time inputs PFC:Who chose the sample frequency ? Faza:sampling frequency of input signal will be choosen by me in software to generate the samples as an input to FPGA PFC:it a REAL application which NEEDS that speed IN REAL TIME ? If it is, it is going to be very EXPENSIVE. Faza:Yes it should be real time...But i am not sure whether my design target to xilinx FPGA as I am planning to support 256-taps with direct form FIR filter which suffers from less speed and more hardware resources compared to distributed arithmetic architecture( i dont know about this) PFC: What is it that you want to do ? Faza:A generic FIR filter which can support upto 256-taps for audio and multimedia applications... regards, faza On Jun 9, 10:29=A0pm, PFC <li...@peufeu.com> wrote: > > =A0 =A0 =A0If your FPGA clock frequency is the same as your Fs then it's= > > simple. > > =A0 =A0 =A0 =A0 Sorry, I mixed up the words ;) here's the correct one... > > =A0 =A0 =A0 =A0 You have a clock frequency Fclock. > =A0 =A0 =A0 =A0 And a sample frequency Fsample. > > =A0 =A0 =A0 =A0 Suppose your impulse response length is N taps. > > =A0 =A0 =A0 =A0 If Fclock =3D N * Fsample this is simple. > > =A0 =A0 =A0 =A0 Every N periods of Fclock it receives a sample. > =A0 =A0 =A0 =A0 Then, N times, it takes a coefficient, and multiplies it w= ith the =A0 > appropriate sample of the input : > > =A0 =A0 =A0 =A0 sum of Coeff(n) * Input(T-n) for n in [0,1 ... N-1] > > =A0 =A0 =A0 =A0 So it takes N clocks to process a sample because you use 1= multiplier and =A0 > you have N taps. > > =A0 =A0 =A0 =A0 Now if you use N multipliers you can process everything in= one clock and =A0 > therefore use Fclock =3D Fsample. But you are going to use much more slice= s =A0 > in your FPGA. > > =A0 =A0 =A0 =A0 And if you have Fclock =3D N * X * Fsample > > =A0 =A0 =A0 =A0 Then your filter is faster than what you need, but that is= not a problem, =A0 > once an input sample is processed, it will just sit idle waiting for the = =A0 > next input sample. > =A0 =A0 =A0 =A0 In this case you could process X channels instead of 1 cha= nnel still =A0 > using 1 multiplier, by using the time the silicon is idle to process the = =A0 > other channels. > > =A0 =A0 =A0 =A0 Get it ? > > > If you then clock this filter with a frequency of kFs, the cut off > > frequency > > will be kFc . > > =A0 =A0 =A0 =A0 Not necessarily ;) > > =A0 =A0 =A0 =A0 An impulse response is just a list of numbers. It does not= have a cutoff =A0 > frequency. If it is a filter all it can have is a cutoff frequency ratio = =A0 > which is a number without a Unit (no hertz, just a number), for instance r= =A0 > =3D 0.1 for a lowpass filter. > =A0 =A0 =A0 =A0 Only when you say "the sample rate is Fs" then you can say= "the cutoff of =A0 > this impulse response when used on a signal of frequency Fs is r * Fs" or = =A0 > 0.1 Fs in this case. > > =A0 =A0 =A0 =A0 If you change the Fs it will just scale. > > =A0 =A0 =A0 =A0 Now if your processing is not done in real time, say for i= nstance you =A0 > sample a chunk of data at Fs then you store the data in a buffer then you = =A0 > stop sampling and you take the time to filter it, you can use any clock = =A0 > you want since it's not in real time anymore. > > > so u mean to say eventhough i generate the filter coefficients before > > hand using FDA tool,i should set the Fclk by considering =A0the sampling= > > frequency and cutoff frequency for which i have generated the filter > > coefficients..am i correct?? > > =A0 =A0 =A0 =A0 No, you should set the clock frequency so that it's practi= cal for you. > > =A0 =A0 =A0 =A0 Say your Fsample is 1 MHz > =A0 =A0 =A0 =A0 you have N =3D 10 taps in your filter > =A0 =A0 =A0 =A0 for each sample you need 10 multiplications and 10 additio= ns > =A0 =A0 =A0 =A0 it takes a clock cycle to do a multiply + accumulate > > =A0 =A0 =A0 =A0 So you need a Fsample * N =3D 10 MHz clock at least. > > =A0 =A0 =A0 =A0 But if you have other stuff in the FPGA running at 50 MHz = you can use 50 =A0 > MHz instead. > =A0 =A0 =A0 =A0 The filter will just sleep during 40 clock cycles then wor= k for 10 cycles =A0 > then sleep again etc. > > > In that case how it is possible to fix fclk =A0which can support a > > maximum sampling frequency till 600Mhz? > > =A0 =A0 =A0 =A0 Well I have bad news for you lol. > =A0 =A0 =A0 =A0 Since the multipliers in your FPGA don't reach that freque= ncy you will =A0 > need to use several multipliers and adders in parallel. > =A0 =A0 =A0 =A0 For instance if you have 10 taps and 600 MHz you need 6 bi= llion MACs/s =A0 > and if your multipliers run at 100 MHz (for example) each provides 100 =A0= > million MAC/s so you're going to need 60 multipliers and a spaghetti =A0 > monster of logic. > > =A0 =A0 =A0 =A0 And since the FPGA fabric doesn't run at 600 MHz (unless y= ou're rich) =A0 > you'll need to input several samples in parallel and add still more =A0 > spaghetti logic to coordinate all this stuff. > > =A0 =A0 =A0 =A0 What is the signal you want to filter ? > =A0 =A0 =A0 =A0 Who chose the sample frequency ? > =A0 =A0 =A0 =A0 Is it a REAL application which NEEDS that speed IN REAL TI= ME ? If it is, =A0 > it is going to be very EXPENSIVE. > =A0 =A0 =A0 =A0 What is it that you want to do ?Article: 132895
FP <FPGA.unknown@gmail.com> writes: > I am looking for a SDRAM controller for Xilinx Spartan3 device in > Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG > can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller be > used to drive SDR SDRAM? > What other options do I have? Write one? Assuming you have relatively modest performance requirements (which seems reasonabnle, or you'd be using DDR), it's not a huge task. My first significant piece of VHDl was an SDRAM controller, years ago using a FLEX10KE part! SDR is really not that complicated, and the timing is fairly easy for modern devices to handle. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 132896
Ambreen Ashfaq Afridi wrote: > I have to use the Trimode Ethernet MAC core for my FPGA project, which > will send and recieve data while connected to LAN though an Ethernet > cable. For that obviously some IP address should be assigned to the > FPGA, I couldn't find the part of code where this is happening ... Can > anyone help me identify that part of code where IP address assignment > is taking place? From the description, it doesn't sound like it should have an IP address. Ethernet MAC addresses are 48 bit addresses, independent of IP addressing. Is it the MAC address you are trying to locate? You will need an IP stack as well as Ethernet to communicate via IP. RLArticle: 132897
>Hi, > >I have described a state machine running with an external pixel clock. >As I could see >on the oscilloscope the ScanDetect signal becomes high indicating that >the pixel clock >is stable. BUT the clock is not stable for some while after Scdt >becomes high. The clock >seems to tune after some us. (stable clock should have around 100MHz) >The clock is changing its frequency, high and low phases are >symmetrical. > >If the FSM is running with that clock and if Scdt='1' is used to start >the FSM, can I trust >the state changes of the FSM ? > >Thank you for your opinion. > >Rgds >Andre > I would have thought that if the pixel clock frequency is lower than standard before it locks, then you should be OK. Otherwise need to apply the maximum clock frequency as constraint to P&R tool.Article: 132898
> I have to use the Trimode Ethernet MAC core for my FPGA project, which= > will send and recieve data while connected to LAN though an Ethernet > cable. For that obviously some IP address should be assigned to the > FPGA, I couldn't find the part of code where this is happening ... Can= > anyone help me identify that part of code where IP address assignment > is taking place? An Ethernet MAC does not know about IP addresses, only Ethernet MAC = addresses. Ethernet sees IP packets as just data with a label that says = = "protocol=3DIP", it does not use the IP address in any way. Ethernet rou= ting = is based on the MAC address. Now your PC which is on Ethernet uses the ARP protocol to query the = network for "which is the MAC address of the machine with IP xx.xx.xx.xx= = ?", it is a broadcast packet that all machines receive and the one which= = feels concerned responds. So as a first step you can set an entry in the ARP cache on your PC (on= = Linux use command arp) to tell the PC that your FPGA's IP corresponds to= = its MAC address. You should chose the IP yourself, something like = 192.168.0.xx if your network is in the 192.168.0.xx form. Once you do that the PC will set the packets' destination address to th= e = right value and your FPGA's MAC will see it and understand that the = packets are targeted at it. Then use an IP stack with ARP to automate this process.Article: 132899
> Faza:I have coded as per direct form structure..so for N-taps it > requires N-multiplication and N-1 addition...And also for fs=3D 1Mhz ,= 1 > million samples will be generated, > since N=3D10,it has 10 filter coefficients.. > Here number of Input samples> number of filter coefficients > samples... > as per my code i will get 1 million o/p samples ...Is it correct?? Well with N input samples and M taps you get N+M-1 output samples but i= f = you are streaming a real time signal, noone cares about the boundary = conditions, so you can say that roughly number of input samples =3D numb= er = of output samples > But i know as per convolution i should get 10+1 million-1 samples.. > In general i will get number of output samples =3D number of input > samples > If i have number of input samples < coefficients i have to zero pad > the end of input samples to process all the coefficients.. > pls clarify on this?? Yes you have to zero pad. If you stop the input stream, your filter wil= l = go to sleep waiting for more data which doesn't come, so the output will= = be truncated. > PFC:What is the signal you want to filter ? > Faza:An audio signal for audio applications and signals used in > multimedia applications are my real time inputs OK then if it's audio why do you mention crazy sample rates like 600 MH= z ? For audio ultimate quality is 192 kHz which is easy to do in FPGA. > PFC:Who chose the sample frequency ? > Faza:sampling frequency of input signal will be choosen by me in > software to generate the samples as an input to FPGA Then choose a realistic input frequency... > PFC:it a REAL application which NEEDS that speed IN REAL TIME ? If it > is, it is going to be very EXPENSIVE. > Faza:Yes it should be real time...But i am not sure whether my design > target to xilinx FPGA as I am planning to support 256-taps with direct= > form FIR filter which suffers from less speed and more hardware > resources compared to distributed arithmetic architecture( i dont know= > about this) > > PFC: What is it that you want to do ? > Faza:A generic FIR filter which can support upto 256-taps for audio > and multimedia applications... Suppose you have 8 channels of 192 kHz audio in real time that's = 1.536.000 samples/s, now if you use 256 taps that's about 400 million = MAC/s which means you can do it with a $10 FPGA.
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