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rickman <gnuarm@gmail.com> writes: > On Jun 7, 12:13 am, Randy Yates <ya...@ieee.org> wrote: >> rickman <gnu...@gmail.com> writes: >> > [...] >> > But if I want a laptop, I won't have much choice but to run Win XP >> > (for the next few weeks) or Vista. I only wish I had a choice. >> >> You do. I have successfully installed Fedora 8 on an HP Pavillion >> DV9620US. >> >> However one thing to be careful of in running linux on laptops is >> Broadcom's stubborn refusal to open up their wireless card >> specifications so that open source drivers can be developed. Translated: >> don't buy a laptop with a Broadcom wireless card (or chipset) if you >> want to run linux on it. Atheros I've heard is very good and supported >> by madwifi.org. >> >> But, even though Broadcom is stubborn, I have still been successful at >> getting the card to work on my home network. Unfortunately the reverse >> engineered drivers (b43-fwcutter...) do not seem to support the Master >> modes used in public hotspots. > > I knew someone would mention Linux. Linux is still an alien platform > to me and there is any amount of software that is not supported under > it... or I should say that there is any amount of software that is > only supported on specific versions of Linux. If I run Fedora 8, > maybe vendor X gives me support and vendor Y doesn't. I run Redhat > and vendor X gives me support and vendor Z doesn't... etc, etc, etc. > > The reason that I still run windows at all is because for me, it is > the only option. Currently Win2000 is the best that runs the minimum > required set of software. If I want a laptop, my only choice > currently is to buy a machine running XP which I can do for the next > few weeks. After that there will be no choice on a new machine except > for Vista. With a number of vendors not supporting that still, I will > not have the option of buying a new laptop with an installed OS that > runs the software I need. I have been able to operate just fine for 3 years without most of the Microsoft-specific software. Most notably, OpenOffice replaces Microsoft Office. And for those occasions that I do need a MS-based OS, such as once a year to run TaxCut, or when I need to run TI Code Composer Studio, I use Win2000 running in a virtual machine under a linux host. I previously used VMWare and currently use VirtualBox for this. What software do you use that demands a MS OS? -- % Randy Yates % "She has an IQ of 1001, she has a jumpsuit %% Fuquay-Varina, NC % on, and she's also a telephone." %%% 919-577-9882 % %%%% <yates@ieee.org> % 'Yours Truly, 2095', *Time*, ELO http://www.digitalsignallabs.comArticle: 132826
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:54b764e5-906e-4ad8-8198-8634b916f7c4@j33g2000pri.googlegroups.com... > On Jun 6, 8:42 am, "Steve Knapp" <steveD.O.TknappA.Tprevailing- > technologyD.O.Tcom> wrote: [snip] > > Thanks, this is pretty interesting. A quick question, can the PLLs be > reconfigured dynamically? The iCE65 parts don't have a PLL, probably due to the extra power consumption. For the projects that I've been working on, a PLL would be nice, but I've been able to implement a lower-power solution in logic. -- Steve Knapp Prevailing Technology, Inc. www.prevailing-technology.comArticle: 132827
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:4849d448$1@clear.net.nz... > Steve Knapp wrote: [snip] > >> The iCE65L04 part on the evaluation board exclusively loads from SPI >> Flash or can be downloaded. > > So it can self-load from SPI, which means a SPI part allows > more-frequent design revisions, at an incremental cost ? > Yes, that's one of the cool things about it. If you want it to be an SRAM-based FPGA, it works just like one. If you want it to be an SPI processor peripheral, then you write the configuration image to it like it's an SPI peripheral. If you want it to be like an ASIC, then you permanently program the NVCM memory. In one of the modes, the iCE65 part loads its configuration image directly from an SPI PROM. The iCE65L04 that I'm using only needs slightly over half a megabit so the image comfortably fits in a 1Mbit SPI PROM. There's also supposedly a mode, which I haven't used yet, where you can store up to four images in the PROM. If you enable the right mode, then the iCE65 part wakes up, looks at two pins, and then loads the configuration image selected by the pins. They call it ColdBoot. After configuration, you can do something similar from inside the fabric and they call this WarmBoot. These functions even allow you to jump from the internal NVCM memory to SPI PROM and vice versa. -- Steve Knapp Prevailing Technology, Inc. www.prevailing-technology.comArticle: 132828
"Gabor" <gabor@alacron.com> wrote in message news:805facd4-5dd4-49dd-b2d1-89ccf2c06f97@k30g2000hse.googlegroups.com... > On Jun 4, 9:48 pm, Jim Granville <no.s...@designtools.maps.co.nz> [snip] > > By the way, the FPGA Journal article seems to imply that the > OTP non-volatile memory can hold more than one configuration. > The datasheet does not bear this out. > If I understand correctly, the nonvolatile memory stores a single image. You can store multiple images if you use an SPI PROM. -- Steve KnappArticle: 132829
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:484858aa$1@clear.net.nz... [snip] > [ I think some other vendors OTP is VERY slow to pgm ? ] > This may be true for some other vendors but the nonvolatile memory on the iCE65 part supposedly programs in about the same time as NOR Flash. If I remember correctly, one of the issues with other OTP or anti-fuse architectures is that the memory cell directly connects to the programmable logic function. These memory cells are small and low-resistance, which good, but you can only program them once. Consequently, you can't pre-test the logic part without programming the OTP memory meaning that you have to perform both memory programming _and_ logic testing during the programming process. This is slow. The iCE65 parts are different. The programmable logic function is controlled by an SRAM memory cell, which can be re-programmed any number of times. As an FPGA manufacturer, you can quickly program and erase the logic hundreds of times during device testing as still ship it to customers. This is also why so many FPGA architectures are SRAM based. The nonvolatile configuration memory (NVCM) on the iCE65 device is a small array off to the side and doesn't directly connect to the logic structure. The NVCM value is copied to a fully-tested SRAM-based memory cell that then controls the fully-tested logic. Because the NVCM is just a memory (and one-time programmable at that), you can quite easily add redundancy and error correction to it, which greatly improves programming yield. Redundancy and error correction becomes more difficult if the OTP memory cell directly controls the programmable logic structure. -- Steve Knapp Prevailing Technology, Inc. www.prevailing-technology.comArticle: 132830
"Nico Coesel" <nico@puntnl.niks> wrote in message
news:484abd50.3010252544@news.planet.nl...
> "jtw" <wrightjt @hotmail.invalid> wrote:
>
>>I disagree; however, I would include 'pipelining' as part of the coding
>>style/trick. You can also try to code such that the critical path(s) with
>>have small enough blocks of logic between flip-flops to enable timing
>>closure. You may add attributes to signals to try to coerce the
>>synthesizer
>>into doing 'the right thing'; if it doesn't come automatically, you might
>>do
>>some low-level coding, synthesize that, and then use the resultant edif
>>file
>>as a black box to the the next level up.
>>
>>Before troubling with all that, though, do some bottom-up evaluations,
>>particularly of things you feel will have trouble meeting timing. The
>>tools
>>will often produce sub-optimal solutions when trying to solve many
>>simultaneous, conflicting requirements (resource location, timing, ...),
>>and
>>thus have trouble for the total design. Generally, the timing performance
>>achieved at the chip level is less optimal that at the block level, so
>>make
>>sure your blocks will meet timing. If they do, and the whole doesn't, you
>>might try incremental design techniques, where you solve one problem,
>>build
>>on it for the next, etc... If they don't, you can try re-coding and/or
>>re-architecting to get the block(s) to meet timing, and then try the
>>whole.
>>Solve the relatively simple problems first... and sometimes the big
>>problems
>>become simple.
>>
>>Other (non-coding) tricks: location constraints, multi-cycle constraints,
>
> This will work, but the time involved to get the design finished will
> increase exponentially. A simpler way to do the same is using more
> than one clock. I usually have 3 clocks: slow (several MHz), main
> processes (tens of MHz) and high speed.
>
> --
> Programmeren in Almere?
> E-mail naar nico@nctdevpuntnl (punt=.)
Somehow, several of the designs I recently finished had:
320 MHz+ data clock, DDR
160 MHz+, coherent with data clock
160 MHz+, system clock
80 MHz+, system clock coherent with 160 MHz system clock
I still used multi-cycle constraints, TIG (Timing Ignore) constraints,
location constraints, .... and had to 'play tricks' to force the tool not to
remove redundant FFs, and insert FFs to break up combinational logic, and
...
Adding clocks will not particularly make meeting timing easier; it is
comparable to using multi-cycle constraints, which imply a virtual clock.
(It may add value in power saving on the clock trees.) Adding clocks adds
complexity, because now you must manage the clock domain crossings. But,
sometimes, that is just part of the job...
JTW
Article: 132831Hi,everyone,I am now doing a work about ALTERA nios-II.The FPGA I use is cycII-60,and the cpu is NIOS-II f,sdram ,lan91c11,dma controller and so on,the main work I should do is to conmunicate the PCs and nios- II with lan91c111,I chose UDP to send and receive data,also It can work properly if I do'nt use dma to send and receive data,but the speed is low about 18Mbps,cpu freq is 50MHZ,so I want to use dma ,but It doesn't work ,I have a look at the soruce file ,the dma send function have call the callback function s91_dma_tx_done(),but the PC can't catch the udp packet,can some give me some advice ,I have no idear.Thanks!Article: 132832
Hi,everyone,I am now doing a work about ALTERA nios-II.The FPGA I use is cycII-60,and the cpu is NIOS-II f,sdram ,lan91c11,dma controller and so on,the main work I should do is to conmunicate the PCs and nios- II with lan91c111,I chose UDP to send and receive data,also It can work properly if I do'nt use dma to send and receive data,but the speed is low about 18Mbps,cpu freq is 50MHZ,so I want to use dma ,but It doesn't work ,I have a look at the soruce file ,the dma send function have call the callback function s91_dma_tx_done(),but the PC can't catch the udp packet,can some give me some advice ,I have no idear.Thanks!Article: 132833
void
s91_senddata(SMSC smsc, unsigned char *data, int len)
{
u_long base = smsc->regbase; /* device base address */
#if 0
unshort *word; /* even byte pointer */
#endif
void s91_dma_tx_done(void *);
int rc;
int *send_buf =(int*)alt_uncached_malloc(0x800);
/* sanity check */
if ((len < 60) || (((int)data) & 0x1))
{
dtrap();
}
/* Send status word first. This seems to be just a required
* placeholder in the devices memory. It's filled in by the
* device upon TX complete.
*/
IOWR_ALTERA_AVALON_LAN91C111_DATA_HW(base, 0);
/* Followed by the byte count; count includes the 6 control bytes.
*/
IOWR_ALTERA_AVALON_LAN91C111_DATA_HW(base, (len & ~0x1) + 6);
#if 0
word = (unshort *)data;
while (len >= 2)
{
IOWR_ALTERA_AVALON_LAN91C111_DATA_HW(base, *word);
word++;
len -= 2;
}
#else
#ifndef ALTERA_DMA_A_TX
if (((u_long)data) & 0x02)
{
IOWR_ALTERA_AVALON_LAN91C111_DATA_HW(base, *(unshort *)data);
data += 2;
len -= 2;
}
while ((len -= 4) >= 0)
{
IOWR_ALTERA_AVALON_LAN91C111_DATA_WORD(base, *(unsigned int
*)data);
data += 4;
}
smsc->snd_odd = len + 4;
smsc->snd_data = data;
s91_dma_tx_done((void *)smsc);
#else
/* disable 91C111 interrupts until DMA completes */
IOWR_ALTERA_AVALON_LAN91C111_MSK(base, 0);
/* do the odd half-word at the beginning by PIO */
if (((u_long)data) & 0x02)
{
IOWR_ALTERA_AVALON_LAN91C111_DATA_HW(base, *(unshort *)data);
data += 2;
len -= 2;
}
//printf ("Start dma send\n");
printf(" len = %d\n",len & ~0x3);
//len = len & ~0x3;
if ((rc = alt_dma_txchan_send(dma_tx, (void *)(((u_long)data) &
~0x80000000), len & ~0x3,
s91_dma_tx_done, (void *)smsc)) < 0)
{
printf ("Failed to post transmit request, reason = %i\n", rc);
exit (1);
}
smsc->snd_odd = len & 0x3;
smsc->snd_data = data + (len & ~0x3);
#endif /* ALTERA_DMA_TX */
#endif
}
Hi$B!$(BI think I have find the problem,when the dma done,it don't call the
callback function s91_dma_tx_done,and the lan91c111 buffer is not
receive the new data,but I don't know why the dma not send the
data,and the rc is correct.
Article: 132834I've noticed Modelsim directly compiles the vendor's simulation-libraries from the HDL-source (either VHDL or Verilog.) I simply run the library-generator applet that comes with ISE/EDK. But Aldec seems to distribute the same vendor library-update in the form of a download, up to a month later. Could an Aldec user explain why this is the case? Can the Aldec simulator compile the libraries directly? Or are there incompatibilities if you try to do this yourself (and hence, the Aldec official library-update.) I really wanted to mention Aldec as an alternative to Modelsim/PE, but before I do that, I'd like to get this cleared up.Article: 132835
kookoo4systemverilog wrote:
> I've noticed Modelsim directly compiles the vendor's
> simulation-libraries from
> the HDL-source (either VHDL or Verilog.) I simply run the
> library-generator
> applet that comes with ISE/EDK.
Those libraries are available anytime
on the device vendor sites.
The device *vendors* A and X provide this
"service" for their own devices with their oem modelsim tools,
perhaps in hope that I chose their non-portable netlists
over their synthesis tools.
> But Aldec seems to distribute the same vendor library-update in the form
> of a download, up to a month later.
1. Aldec is not an oem for the major brands, however...
2. Compiling a library is not a big deal and ...
3. If I am using synthesis, I don't need any libraries for simulation.
Use the source Luke.
-- Mike Treseler
Article: 132836In comp.arch.fpga, rickman <gnuarm@gmail.com> wrote: > On Jun 4, 5:16 pm, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> > wrote: >> >> when STATE_CHECK => >> if datain /= lastval_v then >> control_state_v := STATE_UPDATE >> else >> control_state_v := STATE_OTHER; >> end if; >> >> when STATE_UPDATE => >> lastval_v := datain; >> control_state_v := STATE_CHANGED; >> >> This works in both pre- and post-synthesis simulation and also in real >> hardware. There is now an 8-bit comparator found for the compare line >> and no more warning about constant values. > > This can be significant. Do you have the tools to "see" the logic > produced by this code? It will be a *lot* easier to understand the > logic produced if you can reduce the problem code to a minimum set. > Look at exactly what is being produced in the way of logic. You talk > about an 8 bit comparator, but I only see an equivalence check. If > the variables are 8 bits, this only takes 5 LUTs in two levels. I > supposed it might use 4 LUTs with the carry chain, but I don't think > that is essential. Xst actually reports "Found 8-bit comparator not equal for signal..." So I presume it will implement something like you describe. >> So my question is: Is there a problem with comparing and updating a >> value in the same state (clock)? > > No, certainly the language does not know what you are doing in terms > of updating or comparing. It only knows what you tell it. If you > said to compare values and update the register that is used in the > compare, it is happy doing that... as long as that is what you are > telling it. Somehow I must have failed telling that in the one-state approach. ;-) Why, I still don't know. If there's a real error in my logic, I would expect the pre-synth simulation to fail as well. To my relief, there is no problem with that type of coding, as I have used this in more places in the design (but mostly with 1-bit flags). The 2-state approach solved the curent problem, but it would indeed be interesting to see if I can reproduce the problem in a minimal design, but that will have to wait. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 132837
Hello All,
A new version beta 0.83 is now available. The following changes and
additions have occurred.
* Improved Image Preview Display.
* Context sensitive popup menus to edit objects.
* Path set in image save dialog works.
* Metric paper sizes added to image preview.
* Lower case z, and x now work bus value combobox in toolbar.
* Move signals up and down commands now respect any space in
diagrams used for Text.
* Objects attached to any signal being deleted are deleted
automatically.
* Save file now includes some more error checking before saving
objects.
* Delays can not be added to DigitalClocks.
You can download the Free Edition now and read all about the
TimingAnalyzer at:
www.timing-diagrams.com
----------------------------------------------------------------------------------------------------------------------------------------
The TimingAnalyzer can be used to quickly and easily draw timing
diagrams. Signals, clocks, buses, delays, constraints, and states are
easily added from the GUI.
It can also be used to quickly do a timing analysis and check for
timing faults. Minimum, typical, and worst case analysis can be
performed. Delays and constraints are easily specified and changed to
see if faster clocks or slower parts can be used without any timing
faults.
There are 3 editions planned. The Free Edition(FE), a Standard
Edition(SE), and the Professional Edition(PE).
Article: 132838
I am having difficulties in trying to deskew the Clock on a synchronous
local bus interface between a Virtex4 FPGA and a PowerPC chip.
The instantiation port map of a DCM to provide 0 phase-shift between the
external LCLK_IN and the internal CLK is shown below.
---------------------
port map (
CLK0 => CLK, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
CLKFB => CLK, -- DCM clock feedback
CLKIN => LCLK_IN, -- Clock input (from IBUFG, BUFG or DCM)
RST => RESET -- DCM asynchronous reset input
);
---------------------
The timing constraint is shown below; I believe that the OFFSET constraints
should be effective since the phase-shift, 0 in this case, due to the DCM on
LCLK_IN, is accounted for by the PAR tool.
---------------------
NET "LCLK_IN" TNM_NET = LCLK_IN;
TIMESPEC TS_LCLK_IN = PERIOD "LCLK_IN" 10 ns HIGH 50%;
OFFSET = IN 8 ns BEFORE "LCLK_IN";
OFFSET = OUT 7 ns AFTER "LCLK_IN";
---------------------
A portion of the timing report (.twr) is shown below:
Note the Clock Path Delay of 4.979ns which the DCM usage has failed to
eliminate in this attempt. I was expecting that the delay would be 0ns or
very close to 0ns.
---------------------
Slack: -5.472ns (requirement - (clock arrival + clock path
+ data path + uncertainty))
Source: READY_CARRIER (FF)
Destination: LAD<30> (PAD)
Source Clock: CLK rising at 0.000ns
Requirement: 7.000ns
Data Path Delay: 7.313ns (Levels of Logic = 3)
Clock Path Delay: 4.979ns (Levels of Logic = 3)
Clock Uncertainty: 0.180ns
:
:
Maximum Clock Path: LCLK_IN to READY_CARRIER
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D14.I Tiopi 0.963 LCLK_IN
LCLK_IN
LCLK_IN_IBUFG
DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.260 LCLK_IN_IBUFG
DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -2.213 DCM_BASE_inst
DCM_BASE_inst
BUFGCTRL_X0Y23.I0 net (fanout=3) 1.504 CLK1
BUFGCTRL_X0Y23.O Tbgcko_O 0.900 CLK_BUFG
CLK_BUFG
SLICE_X52Y103.CLK net (fanout=123) 2.565 CLK
------------------------------------------------- ---------------------------
Total 4.979ns (-0.350ns logic,
5.329ns route)
---------------------
Can anyone shed light on this problem?
Bill Ngo
Article: 132839hello.... i wanted to know if fpgas were reprogrammable... if i have a virtex2pro board, use it for a system, and later want to make changes/ additions (hardware), do i lose the already used gates? also, if applications are changed, and downloaded, are the older ones overwritten or do i lose the space? thanks vArticle: 132840
On Jun 9, 1:42=A0pm, vikram <vikram...@gmail.com> wrote: > hello.... i wanted to know if fpgas were reprogrammable... if i have a > virtex2pro board, use it for a system, and later want to make changes/ > additions (hardware), do i lose the already used gates? also, if > applications are changed, and downloaded, are the older ones > overwritten or do i lose the space? > > thanks > > v Yes they are reprogrammable. Most FPGAs load configuration data from an external FLASH memory chip every time they are switched on (or reset). In the case of your Virtex2Pro board, that Flash chip is probably included on the board too. So all you have to do is to reprogram the Flash chip with your new programming file, and the FPGA will load that new configuration after power cycle or reset. Alternatively. you can directly program the FPGA from your PC (without using the Flash). But when you turn off the power, the FPGA loses the configuration. There's absolutely no sense of "overwriting" space or losing it. As I say, the FPGA cannot permanently store configuration data itself. (A few recent FPGAs have integrated the Flash onto the same die or chip, but that is not relevant to your situation and the same principles apply). TomArticle: 132841
Hai,
Jonathan:simple, common case - then
you need to run the clock at exactly Fsample.
Faza:Still iam unable to trace how Fs will decide Fclk :
consider the following experiment i carried out in simulation level:
I generated the filter coefficients with the following parameters
using MATLAB FDA tool:
fc=3D3khz
fs=3D8khz
N=3D8
type=3DLP filter
design method=3Dconstra. least square
The generated 8 filter coefficients before hand is given as an input
to my design and it performs convolution operation with 8 impulse
samples{1,0,0,0,0,0,0,0} .To get all the 8 coefficients come out
properly the following condition should be satisfied:
number of input samples =3D number of coefficients.
Number of clock cylces to process each coefficient =3D number of taps
+2=3D10
so to process all the 8 coefficients with 8 impulse it is taking
10*8=3D80 clock cycles
I got the same number of clock cycle(80 clock cycles) count for the
following:
fc=3D3khz
fs=3D12khz(different sampling frequency)
N=3D8
type=3DLP filter
design method=3Dconstra. least square
I guess u understood my design now...
so in the design number of clock cycles are decided only with number
of taps not with sampling frequency as suggested by u since i am not
using xilinx core generator..
My questions to u:
pls explain...So for the above example wat is the fclk value ?(fs=3D8khz
and fs=3D12kHz with N=3D8)
In general for N=3D256 ,
My design will take (256+2) *256=3D66048 clock cycles
wat is the Fclk value with N=3D256?which xilinx device i can select for
implementation?
In general convolution process:
number of o/p samples=3Dnumber of input sample + number of coeffie -1
But in my design
number of o/p sample =3Dnumber of input sample=3Dnumber of coeffie
I have to append zero to my input samples so that it should be equal
to the filter coefficients to get all the coefficients otherwise i
will miss the o/p sample..
Is the above correct?pls clarify..
Thanks in advance
regards,
faza
On Jun 7, 2:29=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 06 Jun 2008 16:16:56 -0700, Mike Treseler wrote:
> >Perhaps the staircase could be
> >accelerated to an appropriate velocity. ;)
>
> > L_v :=3D L*(1-v**2/c**2)**0.5 ;
>
> Ah. =A0Thanks for your relatively novel suggestion [sorry]
> which I had overlooked...
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
Article: 132842faza wrote: > > Faza:Still iam unable to trace how Fs will decide Fclk : > Hi Faza, I'll have a go. Design your filter with Fs = 1 . Let's say you designed it with a cutoff frequency of Fc where Fc < Fs/2 . If you then clock this filter with a frequency of kFs, the cut off frequency will be kFc . Mmmm, hotwings. HTH., Syms.Article: 132843
> hello.... i wanted to know if fpgas were reprogrammable... Sure, your Virtex stores configuration in RAM. While testing and debugging, use JTAG to configure it, when it's ready program the configuration flash on the board.Article: 132844
You must understand the difference between sample frequency (Fs) and FP= GA = clock frequency... If your FPGA clock frequency is the same as your Fs then it's simple. If your FPGA clock frequency is higher (say, N times higher) than your = Fs = then, the multiplier and adders could make N operations per sample (but = = still only one operation per FPGA clock) If your FPGA clock frequency is lower than your Fs then you will need t= o = use a parallel implementation since you have more samples than the FPGA = = can deal with... > pls explain...So for the above example wat is the fclk value ?(fs=3D8= khz = > and fs=3D12kHz with N=3D8) = Well you decide the clock frequency... it should be equal or greater th= an = Fs, for instance you can process your 12k signal with a 12k clock or a 1= 2 = MHz clock... Also on these filters it's latency that is of interest, not the total = number of clocks to process a signal, since generally you operate on = continuous signals which have no known length (the data just comes...) = unless the signal is something like a video frame where you do have a = fixed amount of data...Article: 132845
Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are very time consuming and an hardware parallel solution can help to satisfy time constraints. Finally I decided for a mixed SW and HW that consists in a TI DSP and a Virtex-5 connected togheter on EMIF. Initially I choosed a Virtex-5SX, because it has a large number of DSP blocks and a good number of logic cells (usefull for parallel hardware implementations), but on the net I saw that people tend to use Virtex-4FX as co-processor for TI DSP. I suppose that this choice is strictly related to the presence of an hard core PowerPC on Virtex-4FX, but I'm not sure. In addition I didn't found any reference design for EMIF interface in Virtex-5 (there are only for Virtex-4 or Virtex-II). Could be this a good reason to choose a Virtex-4 instead of Virtex-5?Article: 132846
> Hi，I think I have find the problem,when the dma done,it don't call the > callback function s91_dma_tx_done,and the lan91c111 buffer is not > receive the new data,but I don't know why the dma not send the > data,and the rc is correct. OK so it works with CPU but not DMA. Did you try DMA from SDRAM to SDRAM just to copy a block of data ? Did it work ? Is the peripheral controller capable of bursts ? Did you configure the FIFO access correctly ? The callback uses an interrupt so make sure you did not mask out the DMA interrupt, that you connected the DMA controller's interrupt line to where it should go, etc. Stick scope probe on the 91c11's RD,WR,CS pins to check if you got your data out. If this is a new design I strongly recomment LAN9117 or LAN9217, much easier to use and faster.Article: 132847
The V4 is thant the V5 older, so it is only natural that there are more published designs for it. The EMIF is a rather generic bus interface, very similar to dozens of other CPU or SRAM interfaces. There is nothing specific about it that affects FPGA choice. You probably can use V4 HDL code for an EMIF interface without modifications in an V5. Also: If you can't code the interface yourself you probably should not start this project. The EMIF interface is not more complicated than what you would use internally to interface to the components of your design. Using existing code therefore provides next to no abstraction. Did you see XAPP573? The circuits to interface to a FIFO inside the FPGA are not much more than half a dozen gates. Kolja Sulimma On 9 Jun., 11:24, techG <giuliopul...@gmail.com> wrote: > Hi all, > I'm working on a realtime application that requires to elaborate a > digital video stream 25fps. Algorithms are very time consuming and an > hardware parallel solution can help to satisfy time constraints. > > Finally I decided for a mixed SW and HW that consists in a TI DSP and > a Virtex-5 connected togheter on EMIF. > > Initially I choosed a Virtex-5SX, because it has a large number of DSP > blocks and a good number of logic cells (usefull for parallel hardware > implementations), but on the net I saw that people tend to use > Virtex-4FX as co-processor for TI DSP. I suppose that this choice is > strictly related to the presence of an hard core PowerPC on > Virtex-4FX, but I'm not sure. > > In addition I didn't found any reference design for EMIF interface in > Virtex-5 (there are only for Virtex-4 or Virtex-II). Could be this a > good reason to choose a Virtex-4 instead of Virtex-5?Article: 132848
If you then clock this filter with a frequency of kFs, the cut off
frequency
will be kFc .
so u mean to say eventhough i generate the filter coefficients before
hand using FDA tool,i should set the Fclk by considering the sampling
frequency and cutoff frequency for which i have generated the filter
coefficients..am i correct??
If your FPGA clock frequency is the same as your Fs then it's
simple.
If your FPGA clock frequency is higher (say, N times higher)
than your Fs
then, the multiplier and adders could make N operations per sample
(but
still only one operation per FPGA clock)
If your FPGA clock frequency is lower than your Fs then you
will need to
use a parallel implementation since you have more samples than the
FPGA
can deal with.....
In that case how it is possible to fix fclk which can support a
maximum sampling frequency till 600Mhz?
regards,
faza
On Jun 9, 2:22=A0pm, PFC <li...@peufeu.com> wrote:
> =A0 =A0 =A0 =A0 You must understand the difference between sample frequenc=
y (Fs) and FPGA =A0
> clock frequency...
>
> =A0 =A0 =A0 =A0 If your FPGA clock frequency is the same as your Fs then i=
t's simple.
> =A0 =A0 =A0 =A0 If your FPGA clock frequency is higher (say, N times highe=
r) than your Fs =A0
> then, the multiplier and adders could make N operations per sample (but =
=A0
> still only one operation per FPGA clock)
> =A0 =A0 =A0 =A0 If your FPGA clock frequency is lower than your Fs then yo=
u will need to =A0
> use a parallel implementation since you have more samples than the FPGA =
=A0
> can deal with...
>
> > =A0 =A0pls explain...So for the above example wat is the fclk value ?(fs=
=3D8khz =A0
> > and fs=3D12kHz with N=3D8) =A0 =A0
>
> =A0 =A0 =A0 =A0 Well you decide the clock frequency... it should be equal =
or greater than =A0
> Fs, for instance you can process your 12k signal with a 12k clock or a 12 =
=A0
> MHz clock...
>
> =A0 =A0 =A0 =A0 Also on these filters it's latency that is of interest, no=
t the total =A0
> number of clocks to process a signal, since generally you operate on =A0
> continuous signals which have no known length (the data just comes...) =A0=
> unless the signal is something like a video frame where you do have a =A0
> fixed amount of data...
Article: 132849JeDi wrote: (jtw wrote, though I am redoing the indenting) >> "I disagree; however, I would include 'pipelining' as part of the >> coding style/trick. You can also try to code such that the critical >> path(s) with have small enough blocks of logic between flip-flops to >> enable timing closure." > I tried pipelining - mainly to break large combinational blocks into > smaller ones. But, the problem I run into is that the logic > utilization increase almost 15-20 % more than the already high > utilization !!! This creates a situation where the tool is not able to > place everything close enough to meet timing - because the > interconnect delay of the FPGA now becomes the bottle neck !!! The advantage of pipelining is that each part of the pipeline runs in parallel. If you have more data to process, it enters the pipeline on subsequent cycles. There are many books on the design of pipelined processors (from the 1960's and 1970's) that will explain that part. If you don't have more data to process, then you might do an iterative design that reuses the same logic on consecutive clock cycles, along with a state machine to keep track of what is being done and when. Consider multiplying two N digit numbers (in any base). You have to generate N partial products, and then add them together. As combinatorial logic, it may be N+1 levels deep. All the partial products are generated, and then N levels of adder to add them up. It takes O(N**2) logic units. Much of the logic isn't doing anything most of the time. Pipeline it as an N stage pipeline. Each stage generates a new partial product and adds it to the cumulative result. It still takes the same amount of logic, plus the registers to generate the pipeline stages, but new data can go in on each cycle. The results come out N (or N+1) cycles later. M products can be completed in M+N+1 clock cycles, where the cycle is long enough to do one partial product and one sum. (Even better, pipeline the sum separately.) If you don't have enough data to keep an N stage pipeline full, an iterative design works. Only O(N) logic units, though maybe an equivalent amount to keep the thing running. Results come out in N+1 cycles, new data goes in every N+1 cycles. Those are the tradeoffs between logic and throughput. You can also do something in between, with more logic and fewer pipeline stages than the latter design. It is all a tradeoff between logic and throughput. -- glen
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