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Hua wrote: <snip> > > Yes Ed, we found out too. In fact, the bottleneck was the clock toggle > rate for I/O pins. For LVDS the highest toggle rate was only 300+ MHz > for this part. > > Hua If you're targeting OC-12, the 622MHz is your bit rate. The 8B10B coder would typically be implemented at 78MHz. If all you need ruinning at the highest rate is the serdes, you should be able to hand-place the LEs and IOs to get the best routing. As for going beyond the 300 MHz limit, you will not be guaranteed to work under all conditions. - JohnArticle: 132626
Hello, I'm sorry for this post but I don't want to rant for nothing, being the optimistic guy that some people know... I have finally got the ProAsic3 kit that I ordered in december. When powered up, it displays some stuff on a 1x8 LCD and blinks LEDs. Wow, I can do the same with a dumb PIC. Now, I see that the kit has a 250K IC, and not a 1500K one. I just looked at the invoice and it was never clear what version was ordered (just "A3P-EVAL-KIT"). I feel really dumb, part one. The huge box contains boxes, air, foam... they could have spared 2x the volume, hence shipping, as well as a CDROM : i get Libero 8.1 and 8.2. Thanks...... Anyway I'm sure that the 8.2 will be forced into me by Actel, while 8.1 will work on the Win2K that I reserve for EDA. Pleaaaaaaaaase don't make me install XP ! Now, what if I built a prototype board on top of the .1mil headers ? Well, Actel decided that a specific board must be done "the hard way", not using cheap and easily soldered 0.1mil pitch predrilled boards. They have shifted the headers 0.05 or 0.025mil so a predrilled board can't fit. Or was it a beginner's mistake ? (I know, I did it once). And don't tell me it's a measure of precaution because there are better ways to prevent a board from being inserted the wrong way. I feel stupid, part two. I can stand the delay, or hack connectors. But now how do I register the software ? http://register.actel.com/ asks me for "a unique software ID number [that] is located on the CD jacket". I find it nowhere. I have looked everywhere in vain. I feel really annoyed, part three. I think that my patience has reached the limits. And nobody will buy this kit back, as it has already cost me almost 400 Euros. I thought that paying "the price" would provide me with something serious. Now all I got is a late, useless board with only 6,144 FlipFlop. I'm sure that there are countless better Xilinx/Actel boards, either by the makers or 3rd parties, cheaper and immediately available. I made a choice and I stand by it, but it's going to end soon if it does not get better. It's not a disapointment anymore, it's deception. Can anyone help me ? YGArticle: 132627
"Peter Alfke" <peter@xilinx.com> wrote in message news:14e54e94-bb9f-43f0-9412- The problem with a long accumulator is the carry ripple delay. That's why I cut up the accumulator into smaller chunks. Into the cut I insert a pipeline flip-flop that delays the rippling carry by one clock tick. Whenever there is a 1 in any of these pipeline registers, it represents an "undigested" carry, which means that the accumulator output is incorrect. Obviously, I must get rid of these stored carry bits before I look at the accumulator output. So I run a few cycles of dummy accumulation, with the data inputs at zero or disabled. Each clock tick will move the stored carry into the accumulator. Worst- case I need one clock tick for every carry-pipeline flip-flop. If you divide the accumulator in two halves, you need only one extra clock tick, and you need it only for read-out, not for the normal accumulator operation. Hello, Peter. Thanks for the expanded explanation. That is much clearer. I like this approach. The extra carry accumulation cycles are only needed when carry is generated. When no carry is generated, the answer is immediately available. Nice. Fast (most of the time in my design). Elegant. Thanks again. - Sam P.S. I often ask for HDL examples from others so I can learn how others have solved similar issues.Article: 132628
Hi Zoran, wasn't there something in your synthesis report telling you that Q_internal (or Q) will be tied to a constant value? Have a look at your code where you wrote if RST <='1' then well, RST less or equal '1' means always true, since '0' is less than one. (not caring about 'X','U' etc, since we are talking synthesis here ) And in that case Q_internal remains 0x00, and doesn't even change when CLR is asserted or anything else. You wrote proper syntax, but the semantic is just wrong for a counter. Take a look at the technology view too. Or even at the list of used ressources in the synthesis report. > if CLR = '1' then > Q_internal <= (others => '0'); > elsif C'event and C='1' then > if RST <='1' then > Q_internal <= (others => '0'); > elsif CE = '1' then > Q_internal <= Q_internal+'1'; > end if; Have a nice synthesis EilertArticle: 132629
On Jun 4, 7:46 am, backhus <n...@nirgends.xyz> wrote: > Hi Zoran, > wasn't there something in your synthesis report telling you that > Q_internal (or Q) will be tied to a constant value? > > Have a look at your code where you wrote > > if RST <='1' then > > well, RST less or equal '1' means always true, since '0' is less than > one. (not caring about 'X','U' etc, since we are talking synthesis here > ) > And in that case Q_internal remains 0x00, and doesn't even change when > CLR is asserted or anything else. > > You wrote proper syntax, but the semantic is just wrong for a counter. > Take a look at the technology view too. Or even at the list of used > ressources in the synthesis report. > > > if CLR = '1' then > > Q_internal <= (others => '0'); > > elsif C'event and C='1' then > > if RST <='1' then > > Q_internal <= (others => '0'); > > elsif CE = '1' then > > Q_internal <= Q_internal+'1'; > > end if; > > Have a nice synthesis > Eilert Thank you very much for the help. Yes you were right. My code wasn't good. The stupid mistake in code. I can't believe what I've wrote. But you must admit that warring that I was getting from ISE were totally unasociative. That confused me totally. :):) Thank you one more time for all your help ZoranArticle: 132630
On Jun 3, 8:42=A0pm, vikram <vikram...@gmail.com> wrote: > On Jun 3, 6:54=A0pm, morphiend <morphi...@gmail.com> wrote: > > > > > > > On Jun 3, 6:18 am, vikram <vikram...@gmail.com> wrote: > > > > hello > > > > when i add a peripheral (plb EMAC in this case) from BSB to my > > > embedded system (PPC405,ML300), do i have to explicitly write the > > > drivers and, especially, an interrupt handler,and download them too? > > > if yes, how do i add them? > > > > further, in the drivers and examples provided by xilinx, where can i > > > find out what the argument values are? (for example, an argument > > > instance pointer[InstancePtr] appears in most functions. for EMAC, > > > say, how do i find out what its value is? same thing with device id > > > etc) > > > > Or does xilinx EDK link the drivers too when the peripheral is added? > > > > please help me out asap... > > > > thanks > > > > vikram > > > > =A0 ps: i am new to this so please keep it simple.... > > > Well..... EDK comes with OS-independent drivers for most of its > > peripherals. So from that standpoint, no you don't have to write the > > low-level driver. Now, you do have to write the "glue" logic to > > interface to this low-level driver. For each driver provided by EDK, > > there is an example of it being used. I'm not sure where they're at, > > but they do exist. > > > The drivers are enabled when you select them in the Software > > configuration portion of your EDK project. After you have enabled > > them, you build them by running libgen. This is performed from the > > command line by "make libs" or from the gui : Build software > > libraries. > > > After the libraries have been built, you can view all the source code > > to them since they'll be in: > > > <EDK project root>/<name of the embedded processor: i.e. ppc405_0>/ > > libsrc/<driver name>. > > > HTH, > > > Mike- Hide quoted text - > > > - Show quoted text - > > thanks for the prompt reply... will check it out. > > regards > vikram- Hide quoted text - > > - Show quoted text - hi again... how do i find out the unique device id of a device in a system? or do i have to assign IDs to all devices manually (if yes, how?)? also as regards instance pointers.... do i assign pointers or is it done by EDK? thanks in advance vikramArticle: 132631
On Wed, 04 Jun 2008 07:46:34 +0200, backhus wrote: >Hi Zoran, >wasn't there something in your synthesis report telling you that >Q_internal (or Q) will be tied to a constant value? > >Have a look at your code where you wrote > >if RST <='1' then Whoops, I missed that! Good catch! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132632
"whygee" <whygee@yg.yg> wrote in message news:4845edb4$0$21147$7a628cd7@news.club-internet.fr... > Hello, > I'm sorry for this post but I don't want to rant for nothing, > being the optimistic guy that some people know... > > I have finally got the ProAsic3 kit that I ordered in december. > When powered up, it displays some stuff on a 1x8 LCD > and blinks LEDs. Wow, I can do the same with a dumb PIC. > > Now, I see that the kit has a 250K IC, and not a 1500K one. > I just looked at the invoice and it was never clear > what version was ordered (just "A3P-EVAL-KIT"). > I feel really dumb, part one. Yes, the Actel webpage clearly states the A3P-EVAL-KIT comes with a soldered A3P250 which is not particular big. However, the good news is that they use the PQ208 package so you might be able to change it for a A3P1000. > > The huge box contains boxes, air, foam... > they could have spared 2x the volume, hence shipping, > as well as a CDROM : i get Libero 8.1 and 8.2. > Thanks...... Anyway I'm sure that the 8.2 will be > forced into me by Actel, while 8.1 will work > on the Win2K that I reserve for EDA. > Pleaaaaaaaaase don't make me install XP ! I had the same problem last year with ISE, so I am afraid that you have to go to XP which is becoming more expensive and difficult to get. Unfortunately Linux is still not a low-cost option. > > Now, what if I built a prototype board > on top of the .1mil headers ? > Well, Actel decided that a specific board must > be done "the hard way", not using cheap and > easily soldered 0.1mil pitch predrilled boards. > They have shifted the headers 0.05 or 0.025mil > so a predrilled board can't fit. Or was it a > beginner's mistake ? (I know, I did it once). > And don't tell me it's a measure of precaution > because there are better ways to prevent a board > from being inserted the wrong way. > I feel stupid, part two. > > I can stand the delay, or hack connectors. > But now how do I register the software ? > http://register.actel.com/ asks me for > "a unique software ID number [that] is located on the CD jacket". > I find it nowhere. I have looked everywhere in vain. > I feel really annoyed, part three. Mine was on the CD carrier, I suspect you have one without a label. Speak to your local FAE/Distributor > > I think that my patience has reached the limits. > And nobody will buy this kit back, as it has already cost > me almost 400 Euros. That is indeed quite expensive, although comparing boards/fpga's is always difficult an equivalent S100 Spartan board can be had for as little as 45 Euros (Enterpoint Drigmorn1). > I thought that paying "the price" > would provide me with something serious. Now all I got > is a late, useless board with only 6,144 FlipFlop. It is not that small, a 6805 + UART + simple timer (System05) only takes 40% (50% of an 3S100), http://members.optushome.com.au/jekent/FPGA.htm Alternatively, you can turn it into a very simple ping-pong game :-) http://www.ht-lab.com/freecores/pingpong/pingpong.html > > I'm sure that there are countless better Xilinx/Actel > boards, either by the makers or 3rd parties, cheaper > and immediately available. I made a choice and I stand > by it, but it's going to end soon if it does not get better. > It's not a disapointment anymore, it's deception. > > Can anyone help me ? I would suggest you speak to your Actel FAE and see if he can change it for a Cortex-M1 board. It is a much better board and I got mine within 2 weeks so I assume they have some in stock (at least in the UK). Of course there is always eBay.... Hans www.ht-lab.com > YGArticle: 132633
On Jun 3, 11:58 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > discussi...@fpga.usenet wrote: > > > I had to remove the idc plug to make direct connection to> vdd/vss/tdo/tdi/tck/tms but still webpack impact will not > > recognise the cable. It seems to me some jtag programmers > > are not compatible with xilinx. > > The Xilinx tools (iMPACT, ChipScope) only work with cables that they > have been designed for, they will not work with any random JTAG cable. > > Ed McGettigan > -- > Xilinx Inc. Digilent (www.digilentinc.com) makes the Xilinx FPGA starter boards, and they have low-cost JTAG programming cables that work with Xilinx's iMPACT. HTH -Dave PollumArticle: 132634
Ambreen Ashfaq Afridi wrote: > Hi im looking for a vhdl to verilog converter. Im working with Trimode > Ethernet MAC core which is written in VHDL. I have to modify this code > but the problem is that I dont have any knowledge of VHDL. I do > programming in Verilog.Plz send me any link for the converter. > Thank you > Regards, > Ambreen Ashfaq http://doolittle.icarus.com/~larry/vhd2vl/ open source. It's doing a rough conversion but very usable for a first pass. tacoArticle: 132635
First of all let me apologize for any thing of things I"m ignorant about here. Up until very recenty my programming experience was limited to higher level programming language: Python, PHP, Perl, hell at this point I'd consider C high level. Anyway. I'm trying to use a Xilinx XUPV2P board to send data over ethernet. The board uses the intel LXT972alc to control the PHY and provide a MII interface. What I attempted to do was to build a valid packet, assert enable on the pin labeled TX_ENABLE and feed that packet nibble by nibble to the intel chip. The packet itself is UDP datagram using IP. I put in the preamble, ethernet header, IP header, UDP header, data and checksum. I used the Ethernet broadcast address. To try to test his out I thought I would plug my computer and the board into a router. I have a C program that I wrote which picks up and prints UDP packets sent to the appropriate port. I put the IP address of my computer as when plugged into the router and tried to send the packets there. However, no data seems to be getting through. Furthermore, the absence of link up lights on both the router and the board seem to indicate that the bord is not able to link to the router. For reference I programmed this in Verilog (which I learned about 2 weeks ago). If anyone could provide me with advice I would much appreciate. Thanks, ---AchatesAVCArticle: 132636
On Jun 4, 2:55=A0am, Zorjak <Zor...@gmail.com> wrote: > On Jun 4, 7:46 am, backhus <n...@nirgends.xyz> wrote: > > > > > > > Hi Zoran, > > wasn't there something in your synthesis report telling you that > > Q_internal (or Q) will be tied to a constant value? > > > Have a look at your code where you wrote > > > if RST <=3D'1' then > > > well, RST less or equal '1' means always true, since '0' is less than > > one. (not caring about 'X','U' etc, since we are talking synthesis here > > ) > > And in that case Q_internal remains 0x00, and doesn't even change when > > CLR is asserted or anything else. > > > You wrote proper syntax, but the semantic is just wrong for a counter. > > Take a look at the technology view too. Or even at the list of used > > ressources in the synthesis report. > > > > =A0 =A0 =A0 =A0 =A0 =A0if CLR =3D '1' then > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Q_internal <=3D= (others =3D> '0'); > > > =A0 =A0 =A0 =A0 =A0 =A0elsif C'event and C=3D'1' then > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if RST <=3D'1' then > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Q_internal <=3D= (others =3D> '0'); > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0elsif CE =3D '1' then > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Q_internal <=3D= Q_internal+'1'; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > > Have a nice synthesis > > But you must admit that warring that I > was getting from ISE were totally unasociative. That confused me > totally. :):) > A synthesis tool's job is to turn code into an implementation, it makes no assumptions about whether what you've written functions as you intended. A simulator's job is to model the functionality of the code and help you to find design errors in your code, the simulator couldn't care less about whether what you've written can be synthesized. When you use the wrong tool, don't complain about the results. Using both somewhat together can be useful, the preliminary synthesis results pointing to possible logical design errors. KJArticle: 132637
"AchatesAVC" <AchatesAVC@gmail.com> wrote in message news:93a5add5-3221-49e4-83d1-b27cee18a6d2@59g2000hsb.googlegroups.com... > Furthermore, the absence of link up lights on both the router and the > board seem to indicate that the bord is not able to link to the > router. If it turns out that the Ethernet components are not working, I will consider buying the board from you (assuming nothing else is broken). > > For reference I programmed this in Verilog (which I learned about 2 > weeks ago). The V2P has 2 onboard PPC405. Have you tried using an embedded core? Network stacks are not trivial components.Article: 132638
On Jun 2, 8:37 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > On Jun 2, 5:40 pm, Andy Peters <goo...@latke.net> wrote: > > > > > On Jun 2, 5:58 am,timinganalyzer<timinganaly...@gmail.com> wrote: > > > > Hello All, > > > > TheTimingAnalyzercan be used to quickly and easily draw timing > > > diagrams. > > > Signals, clocks, buses, delays, constraints, and states are easily > > > added > > > from the GUI. > > > > It can also be used to quickly do a timing analysis and check for > > > timing faults. Minimum, typical, and worst case analysis can be > > > performed. > > > Delays and constraints are easily specified and changed to see if > > > faster > > > clocks or slower parts can be used without any timing faults. > > > > There are 3 editions planned. The Free Edition(FE), the Standard > > > Edition(SE), > > > and the Professional Edition(PE). > > > > You can download the Free Edition now and read all about the > > >TimingAnalyzerat: > > > >www.timing-diagrams.com > > > > Comments and feedback are welcome at > > > > supp...@timing-diagrams.com > > > Hey, it's back! > > > It's good to see that this hasn't died. The commercial alternatives > > are WAAAAAY too expensive. > > > -a > > Yes, it's alive and doing well, and yes the competition is expensive. > TheTimingAnalyzerwill not be. I'm trying very hard to make it as > easy as > possible to use. > > Please feel free to request new features or suggest feature > improvements. > > Regards, > Dan I installed the program and it ran once. But when I try to run it a second time, it will not start. Any ideas?Article: 132639
On Jun 4, 1:36 pm, rickman <gnu...@gmail.com> wrote:
> On Jun 2, 8:37 pm, timinganalyzer <timinganaly...@gmail.com> wrote:
>
>
>
> > On Jun 2, 5:40 pm, Andy Peters <goo...@latke.net> wrote:
>
> > > On Jun 2, 5:58 am,timinganalyzer<timinganaly...@gmail.com> wrote:
>
> > > > Hello All,
>
> > > > TheTimingAnalyzercan be used to quickly and easily draw timing
> > > > diagrams.
> > > > Signals, clocks, buses, delays, constraints, and states are easily
> > > > added
> > > > from the GUI.
>
> > > > It can also be used to quickly do a timing analysis and check for
> > > > timing faults. Minimum, typical, and worst case analysis can be
> > > > performed.
> > > > Delays and constraints are easily specified and changed to see if
> > > > faster
> > > > clocks or slower parts can be used without any timing faults.
>
> > > > There are 3 editions planned. The Free Edition(FE), the Standard
> > > > Edition(SE),
> > > > and the Professional Edition(PE).
>
> > > > You can download the Free Edition now and read all about the
> > > >TimingAnalyzerat:
>
> > > >www.timing-diagrams.com
>
> > > > Comments and feedback are welcome at
>
> > > > supp...@timing-diagrams.com
>
> > > Hey, it's back!
>
> > > It's good to see that this hasn't died. The commercial alternatives
> > > are WAAAAAY too expensive.
>
> > > -a
>
> > Yes, it's alive and doing well, and yes the competition is expensive.
> > TheTimingAnalyzerwill not be. I'm trying very hard to make it as
> > easy as
> > possible to use.
>
> > Please feel free to request new features or suggest feature
> > improvements.
>
> > Regards,
> > Dan
>
> I installed the program and it ran once. But when I try to run it a
> second time, it will not start. Any ideas?
To get some info on why it won't run I ran it in a DOS box.
TimingAnalyzer Version 0.82 Free Edition(FE)
OS Name = Windows 2000
OS Version = 5.0
OS Arch = x86
Java Version = 1.6.0_03
installDir = C:\Program Files\TimingAnalyzer_b82
Settings File = C:\Program Files\TimingAnalyzer_b82\settings
\ta_defaults
Exception in thread "main" java.lang.NullPointerException
at org.dmad.ta.TimingDiagram.findEdge(TimingDiagram.java:2238)
at org.dmad.ta.TimFileIO.readDelay(TimFileIO.java:481)
at org.dmad.ta.TimFileIO.processFileRequest(TimFileIO.java:
1245)
at org.dmad.ta.TimFileIO.<init>(TimFileIO.java:103)
at org.dmad.ta.TimingDiagram.openFile(TimingDiagram.java:3641)
at
org.dmad.ta.TimingAnalyzer.openRecentFile(TimingAnalyzer.java:1682)
at
org.dmad.ta.TimingAnalyzer.loadOpenFileList(TimingAnalyzer.java:1511)
at org.dmad.ta.TimingAnalyzer.<init>(TimingAnalyzer.java:314)
at org.dmad.ta.TimingAnalyzer.main(TimingAnalyzer.java:138)
Article: 132640Does anybody know if it is possible to directly instantiate a Xilinx Fifo Generator asynchronous fifo in VHDL? I have a design that requires the use of them, and I think it would be easier to not to have to keep track of different coregen cores as opposed to just having it written into the VHDL. I've seen other xilinx cores that allow this (dds compiler, for instance) but the fifo generator user guide doesn't say anything about it. Thanks.Article: 132641
> Furthermore, the absence of link up lights on both the router and the > board seem to indicate that the bord is not able to link to the > router. You should have said so first. I don't know about the PHY you use, but usually after reset, an Ethernet PHY needs to be talked to softly using the MII protocol, which you then use to setup autonegociation, bring the link up, after which the LED will light on your router and you will be able to query the PHY to discover the actual link capabilities (duplex, speed, etc) and send and receive data. The PHY will also raise interrupts, which you should process, when the link state changes : disconnection, reconnection, etc. From what you say it seems you forgot to do this. In this case the PHY will simply stay in power down mode and frustrate you. You will need to have a look at the Linux kernel sources for an example, use the 2.4, the code is simpler than in 2.6, pick a NIC driver and grok. Ah, and yeah, you'll need somse sort of CPU to go through that initialization routine.Article: 132642
On Jun 4, 11:14 am, paragon.j...@gmail.com wrote: > Does anybody know if it is possible to directly instantiate a Xilinx > Fifo Generator asynchronous fifo in VHDL? I have a design that > requires the use of them, and I think it would be easier to not to > have to keep track of different coregen cores as opposed to just > having it written into the VHDL. I've seen other xilinx cores that > allow this (dds compiler, for instance) but the fifo generator user > guide doesn't say anything about it. > > Thanks. Yes, and it's pretty easy. Look at what coregen creates. You'll see a template with a bunch a parameters added. I have been successful instantiating the template and modifying the parameters myself, without the use of coregen. Good luck, G.Article: 132643
Thanks much for the replies. Would it just make more sense to get an IP core for this if I need the whole thing to be reliable? -AchatesAVCArticle: 132644
On Jun 2, 8:58 am, timinganalyzer <timinganaly...@gmail.com> wrote: > Hello All, > > The TimingAnalyzer can be used to quickly and easily draw timing > diagrams. > Signals, clocks, buses, delays, constraints, and states are easily > added > from the GUI. > > It can also be used to quickly do a timing analysis and check for > timing faults. Minimum, typical, and worst case analysis can be > performed. > Delays and constraints are easily specified and changed to see if > faster > clocks or slower parts can be used without any timing faults. > > There are 3 editions planned. The Free Edition(FE), the Standard > Edition(SE), > and the Professional Edition(PE). > > You can download the Free Edition now and read all about the > TimingAnalyzer at: > > www.timing-diagrams.com > > Comments and feedback are welcome at > > supp...@timing-diagrams.com I spent about 5 minutes working with this program before I gave up. My reason is not the problem posted below, but because of the user interface decisions made. I don't know why every new program has to reinvent something about the user interface. There is a standard call Common User Interface (CUI) that is even documented by Microsoft, IIRC. The one big difference that hit me up side my head was the way the Cntl key is used counter-intuitively with mouse clicks for selections. If you click on one item it is selected. If you click on an second item, it is *added* to the selections. To deselect something you have to either press the Cntl key while clicking on it or you have to use the ESC key. I have *never* seen a program use this sort of selection mechanism. I have seen variations on how you select multiple, but every other program I have ever worked with, the default action of clicking a new thing while an old thing was selected was to deselect the first thing and to select the new thing. It was more than once that I tried to move some things and ended up with a mess because extra moves kept happening. Combine this with the lack of a working undo feature and I ended up rather frustrated and gave up. I was looking for something that would save me time over a program like Visio. I suggest that the author get some references on CUI or better yet, use some other programs with graphical interfaces and go with the flow. It is so much more productive than trying to retrain the world... if you don't believe me, just look down at your keyboard. Do you think the keyboard layout we all use was a good idea? It's just easier to continue to use it than it is to retrain everyone that is using it now. RickArticle: 132645
Sorry about the title, everyone put down the flamethrowers, lol. I have a few questions about Xilinx and Altera (actually Spartan-3E versus Cyclone III) which relate to a particular project, so here are the specifics. Currently the prototype system is on a Spartan-3E 500 to validate the design, and it works. This was for development, though, as for the final version a larger FPGA is needed ; the 500E is starting to feel a bit tight. This FPGA system has : - Microblaze with caches (small caches) - 16 bit SDRAM with mch_opb_sdram controller (without OPB actually) - CPU connected to RAM through the MCH/XCL - Ethernet LAN9117 MAC+PHY, with DMA to SDRAM via MCH/XCL - IO peripheral, with DMA to SDRAM via MCH/XCL - And lots of IOs (well not so many on PQ208 but final version will have a larger FPGA). Here is what it does : - Receives data from PC over ethernet in UDP packets - Buffer in SDRAM - Output data in user's format of choice on the pins - Read data from pins - Buffer - Send back to PC in UDP packets A simple protocol (not finished) will handle UDP retransmissions etc a-la-TCP but with very low latency. Primary purpose is to transfer multichannel audio (up to about 8-9 megabytes/s) but also digital scope (sample, buffer, send to PC) and other data acquisition applications. It will also need to do some DSP work on the audio (resampling, dithering, and some complicated filtering, etc) and possibly DSP on the acquired signals in a DAQ scenario. Now. Three problems. Everything is good with Xilinx except the DSP part, I guess the logic would fit in a Spartan-E3 1200 with lots of room to spare except I might be short on multipliers. Now that would be a problem to realize that once the final board is made ! So I thought about Spartan-3A DSP but it has a packaging problem : 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. Second problem, this SDRAM is really crummy and so is mch_opb_sdram. Granted, I get 90 MB/s from a 16 bit SDRAM running at 50 MHz which is good. But it runs at 50 MHz !!! I should have put some DDR. So the second requirement is an easy interface to a 16 bit DDR chip with a FREE core that supports some good fast DMA like the mch_opb does. I really like this way of accessing memory, the CPU doesn't even have to touch it, my data IO core self-serves from memory, I like that. Ethernet is slow (20 MB/s) but as I said I want to use it also for some data acquisition which means writing lots of data very fast to the SDRAM, since the sample rate of the converters will depend on the memory bandwidth ! Third problem, most of my IO is 3.3V but I would like to use LVDS for some signals. There are only 4 IO banks... Cyclone III (like EP3C40) on the other hand is cheap, has looots of DSP power, the FPGA itself is faster than the Spartan 3, and it has 8 banks which means I can dedicate 1/8 of the pins to LVDS and still have enough for my 3.3V IO. In other words it looks nice but I don't know anything about Altera. I loaded up the free tools and played with them a bit without much success... NIOS vs Microblaze ? I don't care, CPU utilization is far from 100% anyway, so as long as it runs and has JTAG debug I'm happy. I would like to avoid having to purchase cores, also. EDK which I got on CD with a dev kit comes with a nice assortment of memory controllers... I'm having problems decrypting the Altera licensing stuff, like what is free, and what is not... Also this board will be used as part of an open source project. We'll make a board fab run and sell them so people can hack them. I would really prefer if those guys could use free (as in beer) software and EDK is a problem there. But, so is the small collection of free Altera cores... So, from my project description above, what could I do ?...Article: 132646
On Wed, 04 Jun 2008 20:31:30 +0200, <ghelbig@gmail.com> wrote: > On Jun 4, 11:14 am, paragon.j...@gmail.com wrote: >> Does anybody know if it is possible to directly instantiate a Xilinx >> Fifo Generator asynchronous fifo in VHDL? I have a design that >> requires the use of them, and I think it would be easier to not to >> have to keep track of different coregen cores as opposed to just >> having it written into the VHDL. I've seen other xilinx cores that >> allow this (dds compiler, for instance) but the fifo generator user >> guide doesn't say anything about it. >> >> Thanks. > > Yes, and it's pretty easy. > > Look at what coregen creates. You'll see a template with a bunch a > parameters added. > > I have been successful instantiating the template and modifying the > parameters myself, without the use of coregen. > > Good luck, > G. Thanks, I was in need of this information, too.Article: 132647
On Wed, 04 Jun 2008 21:43:39 +0200, AchatesAVC <AchatesAVC@gmail.com> wrote: > Thanks much for the replies. > > Would it just make more sense to get an IP core for this if I need the > whole thing to be reliable? > > -AchatesAVC Hm, well, if you want to do some more involved ethernet transfer (anything besides really basic stuff) yes you'll want an Ethernet MAC and some software to configure it and control it. If you just want to send raw data you can get away with configuring the PHY using the CPU and then sending pre-canned frames just like you've been doing. Xilinx has one in EDK, also one is on OpenCores. In my design I used a LAN9117 MAC+PHY chip from SMSC. I warmly recommend this chip to anyone, it is easy to use and will handle 100 Mbps full duplex without dropping packets. However you MUST NOT put it on a shared bus with, for instance, the RAM, because its bus is slow, and at full bandwidth it is busy a large percentage of the time. This is absolutely not a problem, unless it kills your memory bandwidth by the simple fact of sitting on the same bus ! Also the CPU interface is very simple, it's really a no-nonsense chip (unlike the LAN91c111 which is a PITA). Of course it eats more IO than a PHY, but it eats less slices than a MAC in the FPGA... (and it works)Article: 132648
Something simular to the following code fragments works in pre-synthesis
simulation, but not in real hardware and post P&R timing simulation.
entity controller is
port (
...
datain in : std_logic_vector(7 downto 0);
clock in : std_logic;
...
lastval out : std_logic_vector(7 downto 0);
);
end entity controller;
architecture rtl of controller is
begin
process(clock)
...
variable lastval_v : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
case control_state_v is
...
when STATE_CHECK =>
if datain /= lastval_v then
lastval_v := datain;
control_state_v := STATE_CHANGED
else
control_state_v := STATE_OTHER;
end if;
when STATE_CHANGED =>
...
when STATE_OTHER =>
...
end case;
end if;
lastval <= lastval_v;
end process;
end architecture;
This works in pre-synthesis simulation (modelsim) and "STATE_CHANGED" is
only reached when datain is actually different from lastval_v. After
synthesis however, STATE_CHANGED is always reached except when datain is
equal to X"00". If I check the synthesis report, I find something about
lastval_v_mux0000 has a constant value during circuit operation. There
is also no 8-bit comparator found for the check state. Both I find
amazing as the pre-synth simulation works and I know the data on datain
is changing.
To localize the problem, I have split the state in a separate check and
update state like this:
when STATE_CHECK =>
if datain /= lastval_v then
control_state_v := STATE_UPDATE
else
control_state_v := STATE_OTHER;
end if;
when STATE_UPDATE =>
lastval_v := datain;
control_state_v := STATE_CHANGED;
This works in both pre- and post-synthesis simulation and also in real
hardware. There is now an 8-bit comparator found for the compare line
and no more warning about constant values.
So my question is: Is there a problem with comparing and updating a
value in the same state (clock)?
And does the problem als exist for single bit values when used like
this:
if my_bit_v = '1' then
my_bit_v := '0';
-- do stuff
end if;
All inputs to the entity come from other parts in the fpga and are all
updated on the same clock. The synthesis report claims the design can
run at 58 MHz, actual clock is 50 MHz, no other constraints defined.
The hardware is Xilinx spartan-3e and synthesis is done with ISE9.2.
--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)
Article: 132649>> Ah, and yeah, you'll need somse sort of CPU to go through that >> initialization routine. > > Depending on the definition of CPU. It could presumably be done > by a state machine which may or may not follow one's definition > of CPU. > > -- glen > Actually I use Microblaze, but I was thinking if he doesn't need a CPU he could use PicoBlaze, then I remembered he uses a chip with a PPC core...
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